STM32G030_CRSF_TO_PWM.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000b8 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00005fa8 080000b8 080000b8 000010b8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000000e0 08006060 08006060 00007060 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08006140 08006140 00008194 2**0 CONTENTS 4 .ARM 00000000 08006140 08006140 00008194 2**0 CONTENTS 5 .preinit_array 00000000 08006140 08006140 00008194 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08006140 08006140 00007140 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08006144 08006144 00007144 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000194 20000000 08006148 00008000 2**2 CONTENTS, ALLOC, LOAD, CODE 9 .bss 0000039c 20000194 080062dc 00008194 2**2 ALLOC 10 ._user_heap_stack 00000600 20000530 080062dc 00008530 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 00008194 2**0 CONTENTS, READONLY 12 .debug_info 0001565c 00000000 00000000 000081bc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00003551 00000000 00000000 0001d818 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000012d8 00000000 00000000 00020d70 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00000ea9 00000000 00000000 00022048 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00017018 00000000 00000000 00022ef1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00016a5d 00000000 00000000 00039f09 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0009113f 00000000 00000000 00050966 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 000e1aa5 2**0 CONTENTS, READONLY 20 .debug_frame 00004368 00000000 00000000 000e1ae8 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000050 00000000 00000000 000e5e50 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000b8 <__do_global_dtors_aux>: 80000b8: b510 push {r4, lr} 80000ba: 4c06 ldr r4, [pc, #24] @ (80000d4 <__do_global_dtors_aux+0x1c>) 80000bc: 7823 ldrb r3, [r4, #0] 80000be: 2b00 cmp r3, #0 80000c0: d107 bne.n 80000d2 <__do_global_dtors_aux+0x1a> 80000c2: 4b05 ldr r3, [pc, #20] @ (80000d8 <__do_global_dtors_aux+0x20>) 80000c4: 2b00 cmp r3, #0 80000c6: d002 beq.n 80000ce <__do_global_dtors_aux+0x16> 80000c8: 4804 ldr r0, [pc, #16] @ (80000dc <__do_global_dtors_aux+0x24>) 80000ca: e000 b.n 80000ce <__do_global_dtors_aux+0x16> 80000cc: bf00 nop 80000ce: 2301 movs r3, #1 80000d0: 7023 strb r3, [r4, #0] 80000d2: bd10 pop {r4, pc} 80000d4: 20000194 .word 0x20000194 80000d8: 00000000 .word 0x00000000 80000dc: 08006038 .word 0x08006038 080000e0 : 80000e0: 4b04 ldr r3, [pc, #16] @ (80000f4 ) 80000e2: b510 push {r4, lr} 80000e4: 2b00 cmp r3, #0 80000e6: d003 beq.n 80000f0 80000e8: 4903 ldr r1, [pc, #12] @ (80000f8 ) 80000ea: 4804 ldr r0, [pc, #16] @ (80000fc ) 80000ec: e000 b.n 80000f0 80000ee: bf00 nop 80000f0: bd10 pop {r4, pc} 80000f2: 46c0 nop @ (mov r8, r8) 80000f4: 00000000 .word 0x00000000 80000f8: 20000198 .word 0x20000198 80000fc: 08006038 .word 0x08006038 08000100 <__udivsi3>: 8000100: 2200 movs r2, #0 8000102: 0843 lsrs r3, r0, #1 8000104: 428b cmp r3, r1 8000106: d374 bcc.n 80001f2 <__udivsi3+0xf2> 8000108: 0903 lsrs r3, r0, #4 800010a: 428b cmp r3, r1 800010c: d35f bcc.n 80001ce <__udivsi3+0xce> 800010e: 0a03 lsrs r3, r0, #8 8000110: 428b cmp r3, r1 8000112: d344 bcc.n 800019e <__udivsi3+0x9e> 8000114: 0b03 lsrs r3, r0, #12 8000116: 428b cmp r3, r1 8000118: d328 bcc.n 800016c <__udivsi3+0x6c> 800011a: 0c03 lsrs r3, r0, #16 800011c: 428b cmp r3, r1 800011e: d30d bcc.n 800013c <__udivsi3+0x3c> 8000120: 22ff movs r2, #255 @ 0xff 8000122: 0209 lsls r1, r1, #8 8000124: ba12 rev r2, r2 8000126: 0c03 lsrs r3, r0, #16 8000128: 428b cmp r3, r1 800012a: d302 bcc.n 8000132 <__udivsi3+0x32> 800012c: 1212 asrs r2, r2, #8 800012e: 0209 lsls r1, r1, #8 8000130: d065 beq.n 80001fe <__udivsi3+0xfe> 8000132: 0b03 lsrs r3, r0, #12 8000134: 428b cmp r3, r1 8000136: d319 bcc.n 800016c <__udivsi3+0x6c> 8000138: e000 b.n 800013c <__udivsi3+0x3c> 800013a: 0a09 lsrs r1, r1, #8 800013c: 0bc3 lsrs r3, r0, #15 800013e: 428b cmp r3, r1 8000140: d301 bcc.n 8000146 <__udivsi3+0x46> 8000142: 03cb lsls r3, r1, #15 8000144: 1ac0 subs r0, r0, r3 8000146: 4152 adcs r2, r2 8000148: 0b83 lsrs r3, r0, #14 800014a: 428b cmp r3, r1 800014c: d301 bcc.n 8000152 <__udivsi3+0x52> 800014e: 038b lsls r3, r1, #14 8000150: 1ac0 subs r0, r0, r3 8000152: 4152 adcs r2, r2 8000154: 0b43 lsrs r3, r0, #13 8000156: 428b cmp r3, r1 8000158: d301 bcc.n 800015e <__udivsi3+0x5e> 800015a: 034b lsls r3, r1, #13 800015c: 1ac0 subs r0, r0, r3 800015e: 4152 adcs r2, r2 8000160: 0b03 lsrs r3, r0, #12 8000162: 428b cmp r3, r1 8000164: d301 bcc.n 800016a <__udivsi3+0x6a> 8000166: 030b lsls r3, r1, #12 8000168: 1ac0 subs r0, r0, r3 800016a: 4152 adcs r2, r2 800016c: 0ac3 lsrs r3, r0, #11 800016e: 428b cmp r3, r1 8000170: d301 bcc.n 8000176 <__udivsi3+0x76> 8000172: 02cb lsls r3, r1, #11 8000174: 1ac0 subs r0, r0, r3 8000176: 4152 adcs r2, r2 8000178: 0a83 lsrs r3, r0, #10 800017a: 428b cmp r3, r1 800017c: d301 bcc.n 8000182 <__udivsi3+0x82> 800017e: 028b lsls r3, r1, #10 8000180: 1ac0 subs r0, r0, r3 8000182: 4152 adcs r2, r2 8000184: 0a43 lsrs r3, r0, #9 8000186: 428b cmp r3, r1 8000188: d301 bcc.n 800018e <__udivsi3+0x8e> 800018a: 024b lsls r3, r1, #9 800018c: 1ac0 subs r0, r0, r3 800018e: 4152 adcs r2, r2 8000190: 0a03 lsrs r3, r0, #8 8000192: 428b cmp r3, r1 8000194: d301 bcc.n 800019a <__udivsi3+0x9a> 8000196: 020b lsls r3, r1, #8 8000198: 1ac0 subs r0, r0, r3 800019a: 4152 adcs r2, r2 800019c: d2cd bcs.n 800013a <__udivsi3+0x3a> 800019e: 09c3 lsrs r3, r0, #7 80001a0: 428b cmp r3, r1 80001a2: d301 bcc.n 80001a8 <__udivsi3+0xa8> 80001a4: 01cb lsls r3, r1, #7 80001a6: 1ac0 subs r0, r0, r3 80001a8: 4152 adcs r2, r2 80001aa: 0983 lsrs r3, r0, #6 80001ac: 428b cmp r3, r1 80001ae: d301 bcc.n 80001b4 <__udivsi3+0xb4> 80001b0: 018b lsls r3, r1, #6 80001b2: 1ac0 subs r0, r0, r3 80001b4: 4152 adcs r2, r2 80001b6: 0943 lsrs r3, r0, #5 80001b8: 428b cmp r3, r1 80001ba: d301 bcc.n 80001c0 <__udivsi3+0xc0> 80001bc: 014b lsls r3, r1, #5 80001be: 1ac0 subs r0, r0, r3 80001c0: 4152 adcs r2, r2 80001c2: 0903 lsrs r3, r0, #4 80001c4: 428b cmp r3, r1 80001c6: d301 bcc.n 80001cc <__udivsi3+0xcc> 80001c8: 010b lsls r3, r1, #4 80001ca: 1ac0 subs r0, r0, r3 80001cc: 4152 adcs r2, r2 80001ce: 08c3 lsrs r3, r0, #3 80001d0: 428b cmp r3, r1 80001d2: d301 bcc.n 80001d8 <__udivsi3+0xd8> 80001d4: 00cb lsls r3, r1, #3 80001d6: 1ac0 subs r0, r0, r3 80001d8: 4152 adcs r2, r2 80001da: 0883 lsrs r3, r0, #2 80001dc: 428b cmp r3, r1 80001de: d301 bcc.n 80001e4 <__udivsi3+0xe4> 80001e0: 008b lsls r3, r1, #2 80001e2: 1ac0 subs r0, r0, r3 80001e4: 4152 adcs r2, r2 80001e6: 0843 lsrs r3, r0, #1 80001e8: 428b cmp r3, r1 80001ea: d301 bcc.n 80001f0 <__udivsi3+0xf0> 80001ec: 004b lsls r3, r1, #1 80001ee: 1ac0 subs r0, r0, r3 80001f0: 4152 adcs r2, r2 80001f2: 1a41 subs r1, r0, r1 80001f4: d200 bcs.n 80001f8 <__udivsi3+0xf8> 80001f6: 4601 mov r1, r0 80001f8: 4152 adcs r2, r2 80001fa: 4610 mov r0, r2 80001fc: 4770 bx lr 80001fe: e7ff b.n 8000200 <__udivsi3+0x100> 8000200: b501 push {r0, lr} 8000202: 2000 movs r0, #0 8000204: f000 f806 bl 8000214 <__aeabi_idiv0> 8000208: bd02 pop {r1, pc} 800020a: 46c0 nop @ (mov r8, r8) 0800020c <__aeabi_uidivmod>: 800020c: 2900 cmp r1, #0 800020e: d0f7 beq.n 8000200 <__udivsi3+0x100> 8000210: e776 b.n 8000100 <__udivsi3> 8000212: 4770 bx lr 08000214 <__aeabi_idiv0>: 8000214: 4770 bx lr 8000216: 46c0 nop @ (mov r8, r8) 08000218 : extern ADC_HandleTypeDef hadc1; #define ADC_REGULAR_BUF_LEN 1 uint32_t ADCRegular[ADC_REGULAR_BUF_LEN]; // ADC regular conventions void ADC_Init(void) { 8000218: b580 push {r7, lr} 800021a: af00 add r7, sp, #0 ADC_Enable(&hadc1); 800021c: 4b0a ldr r3, [pc, #40] @ (8000248 ) 800021e: 0018 movs r0, r3 8000220: f002 f994 bl 800254c // ADC Calibration if (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK) { 8000224: 4b08 ldr r3, [pc, #32] @ (8000248 ) 8000226: 0018 movs r0, r3 8000228: f002 fb9a bl 8002960 800022c: 1e03 subs r3, r0, #0 800022e: d001 beq.n 8000234 Error_Handler(); 8000230: f000 faf2 bl 8000818 } HAL_ADC_Start_DMA(&hadc1, ADCRegular, ADC_REGULAR_BUF_LEN); 8000234: 4905 ldr r1, [pc, #20] @ (800024c ) 8000236: 4b04 ldr r3, [pc, #16] @ (8000248 ) 8000238: 2201 movs r2, #1 800023a: 0018 movs r0, r3 800023c: f001 fe54 bl 8001ee8 } 8000240: 46c0 nop @ (mov r8, r8) 8000242: 46bd mov sp, r7 8000244: bd80 pop {r7, pc} 8000246: 46c0 nop @ (mov r8, r8) 8000248: 200001b4 .word 0x200001b4 800024c: 200001b0 .word 0x200001b0 08000250 : void ADC_Start_Convertion(void) { 8000250: b580 push {r7, lr} 8000252: af00 add r7, sp, #0 HAL_ADC_Stop_DMA(&hadc1); 8000254: 4b06 ldr r3, [pc, #24] @ (8000270 ) 8000256: 0018 movs r0, r3 8000258: f001 fed4 bl 8002004 HAL_ADC_Start_DMA(&hadc1, ADCRegular, ADC_REGULAR_BUF_LEN); 800025c: 4905 ldr r1, [pc, #20] @ (8000274 ) 800025e: 4b04 ldr r3, [pc, #16] @ (8000270 ) 8000260: 2201 movs r2, #1 8000262: 0018 movs r0, r3 8000264: f001 fe40 bl 8001ee8 } 8000268: 46c0 nop @ (mov r8, r8) 800026a: 46bd mov sp, r7 800026c: bd80 pop {r7, pc} 800026e: 46c0 nop @ (mov r8, r8) 8000270: 200001b4 .word 0x200001b4 8000274: 200001b0 .word 0x200001b0 08000278 : uint16_t ADC_GetVoltage(void) { 8000278: b580 push {r7, lr} 800027a: b082 sub sp, #8 800027c: af00 add r7, sp, #0 uint32_t adc_value; adc_value = ADC_REF_Voltage_mV * ADCRegular[0] / 4095; 800027e: 4b10 ldr r3, [pc, #64] @ (80002c0 ) 8000280: 681b ldr r3, [r3, #0] 8000282: 4a10 ldr r2, [pc, #64] @ (80002c4 ) 8000284: 4353 muls r3, r2 8000286: 4910 ldr r1, [pc, #64] @ (80002c8 ) 8000288: 0018 movs r0, r3 800028a: f7ff ff39 bl 8000100 <__udivsi3> 800028e: 0003 movs r3, r0 8000290: 607b str r3, [r7, #4] adc_value = (adc_value* (ADC_Voltage_R1 + ADC_Voltage_R2)) / ADC_Voltage_R2; // Milivolts 8000292: 687b ldr r3, [r7, #4] 8000294: 4a0d ldr r2, [pc, #52] @ (80002cc ) 8000296: 4353 muls r3, r2 8000298: 490d ldr r1, [pc, #52] @ (80002d0 ) 800029a: 0018 movs r0, r3 800029c: f7ff ff30 bl 8000100 <__udivsi3> 80002a0: 0003 movs r3, r0 80002a2: 607b str r3, [r7, #4] adc_value = adc_value / 100; // Volts * 10 It is need for telemetry 80002a4: 687b ldr r3, [r7, #4] 80002a6: 2164 movs r1, #100 @ 0x64 80002a8: 0018 movs r0, r3 80002aa: f7ff ff29 bl 8000100 <__udivsi3> 80002ae: 0003 movs r3, r0 80002b0: 607b str r3, [r7, #4] return adc_value; 80002b2: 687b ldr r3, [r7, #4] 80002b4: b29b uxth r3, r3 } 80002b6: 0018 movs r0, r3 80002b8: 46bd mov sp, r7 80002ba: b002 add sp, #8 80002bc: bd80 pop {r7, pc} 80002be: 46c0 nop @ (mov r8, r8) 80002c0: 200001b0 .word 0x200001b0 80002c4: 00000ce4 .word 0x00000ce4 80002c8: 00000fff .word 0x00000fff 80002cc: 00003afc .word 0x00003afc 80002d0: 000013ec .word 0x000013ec 080002d4
: /** * @brief The application entry point. * @retval int */ int main(void) { 80002d4: b580 push {r7, lr} 80002d6: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80002d8: f001 fa4a bl 8001770 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80002dc: f000 f811 bl 8000302 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80002e0: f000 fa5e bl 80007a0 MX_DMA_Init(); 80002e4: f000 fa36 bl 8000754 MX_TIM3_Init(); 80002e8: f000 f994 bl 8000614 MX_ADC1_Init(); 80002ec: f000 f864 bl 80003b8 MX_USART2_UART_Init(); 80002f0: f000 f9fc bl 80006ec MX_TIM1_Init(); 80002f4: f000 f8cc bl 8000490 /* USER CODE BEGIN 2 */ USER_Init(); 80002f8: f001 f876 bl 80013e8 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { USER_Main_Loop(); 80002fc: f001 f924 bl 8001548 8000300: e7fc b.n 80002fc 08000302 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000302: b590 push {r4, r7, lr} 8000304: b093 sub sp, #76 @ 0x4c 8000306: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000308: 2414 movs r4, #20 800030a: 193b adds r3, r7, r4 800030c: 0018 movs r0, r3 800030e: 2334 movs r3, #52 @ 0x34 8000310: 001a movs r2, r3 8000312: 2100 movs r1, #0 8000314: f005 fe64 bl 8005fe0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000318: 1d3b adds r3, r7, #4 800031a: 0018 movs r0, r3 800031c: 2310 movs r3, #16 800031e: 001a movs r2, r3 8000320: 2100 movs r1, #0 8000322: f005 fe5d bl 8005fe0 /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 8000326: 2380 movs r3, #128 @ 0x80 8000328: 009b lsls r3, r3, #2 800032a: 0018 movs r0, r3 800032c: f003 fad8 bl 80038e0 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8000330: 193b adds r3, r7, r4 8000332: 2202 movs r2, #2 8000334: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000336: 193b adds r3, r7, r4 8000338: 2280 movs r2, #128 @ 0x80 800033a: 0052 lsls r2, r2, #1 800033c: 60da str r2, [r3, #12] RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; 800033e: 0021 movs r1, r4 8000340: 187b adds r3, r7, r1 8000342: 2200 movs r2, #0 8000344: 611a str r2, [r3, #16] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8000346: 187b adds r3, r7, r1 8000348: 2240 movs r2, #64 @ 0x40 800034a: 615a str r2, [r3, #20] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800034c: 187b adds r3, r7, r1 800034e: 2202 movs r2, #2 8000350: 61da str r2, [r3, #28] RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 8000352: 187b adds r3, r7, r1 8000354: 2202 movs r2, #2 8000356: 621a str r2, [r3, #32] RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; 8000358: 187b adds r3, r7, r1 800035a: 2200 movs r2, #0 800035c: 625a str r2, [r3, #36] @ 0x24 RCC_OscInitStruct.PLL.PLLN = 8; 800035e: 187b adds r3, r7, r1 8000360: 2208 movs r2, #8 8000362: 629a str r2, [r3, #40] @ 0x28 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000364: 187b adds r3, r7, r1 8000366: 2280 movs r2, #128 @ 0x80 8000368: 0292 lsls r2, r2, #10 800036a: 62da str r2, [r3, #44] @ 0x2c RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 800036c: 187b adds r3, r7, r1 800036e: 2280 movs r2, #128 @ 0x80 8000370: 0592 lsls r2, r2, #22 8000372: 631a str r2, [r3, #48] @ 0x30 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000374: 187b adds r3, r7, r1 8000376: 0018 movs r0, r3 8000378: f003 fafe bl 8003978 800037c: 1e03 subs r3, r0, #0 800037e: d001 beq.n 8000384 { Error_Handler(); 8000380: f000 fa4a bl 8000818 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000384: 1d3b adds r3, r7, #4 8000386: 2207 movs r2, #7 8000388: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800038a: 1d3b adds r3, r7, #4 800038c: 2202 movs r2, #2 800038e: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000390: 1d3b adds r3, r7, #4 8000392: 2200 movs r2, #0 8000394: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8000396: 1d3b adds r3, r7, #4 8000398: 2200 movs r2, #0 800039a: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800039c: 1d3b adds r3, r7, #4 800039e: 2102 movs r1, #2 80003a0: 0018 movs r0, r3 80003a2: f003 fdf9 bl 8003f98 80003a6: 1e03 subs r3, r0, #0 80003a8: d001 beq.n 80003ae { Error_Handler(); 80003aa: f000 fa35 bl 8000818 } } 80003ae: 46c0 nop @ (mov r8, r8) 80003b0: 46bd mov sp, r7 80003b2: b013 add sp, #76 @ 0x4c 80003b4: bd90 pop {r4, r7, pc} ... 080003b8 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 80003b8: b580 push {r7, lr} 80003ba: b084 sub sp, #16 80003bc: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80003be: 1d3b adds r3, r7, #4 80003c0: 0018 movs r0, r3 80003c2: 230c movs r3, #12 80003c4: 001a movs r2, r3 80003c6: 2100 movs r1, #0 80003c8: f005 fe0a bl 8005fe0 /* USER CODE END ADC1_Init 1 */ /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc1.Instance = ADC1; 80003cc: 4b2d ldr r3, [pc, #180] @ (8000484 ) 80003ce: 4a2e ldr r2, [pc, #184] @ (8000488 ) 80003d0: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; 80003d2: 4b2c ldr r3, [pc, #176] @ (8000484 ) 80003d4: 2280 movs r2, #128 @ 0x80 80003d6: 05d2 lsls r2, r2, #23 80003d8: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_12B; 80003da: 4b2a ldr r3, [pc, #168] @ (8000484 ) 80003dc: 2200 movs r2, #0 80003de: 609a str r2, [r3, #8] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80003e0: 4b28 ldr r3, [pc, #160] @ (8000484 ) 80003e2: 2200 movs r2, #0 80003e4: 60da str r2, [r3, #12] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 80003e6: 4b27 ldr r3, [pc, #156] @ (8000484 ) 80003e8: 2200 movs r2, #0 80003ea: 611a str r2, [r3, #16] hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 80003ec: 4b25 ldr r3, [pc, #148] @ (8000484 ) 80003ee: 2204 movs r2, #4 80003f0: 615a str r2, [r3, #20] hadc1.Init.LowPowerAutoWait = DISABLE; 80003f2: 4b24 ldr r3, [pc, #144] @ (8000484 ) 80003f4: 2200 movs r2, #0 80003f6: 761a strb r2, [r3, #24] hadc1.Init.LowPowerAutoPowerOff = DISABLE; 80003f8: 4b22 ldr r3, [pc, #136] @ (8000484 ) 80003fa: 2200 movs r2, #0 80003fc: 765a strb r2, [r3, #25] hadc1.Init.ContinuousConvMode = DISABLE; 80003fe: 4b21 ldr r3, [pc, #132] @ (8000484 ) 8000400: 2200 movs r2, #0 8000402: 769a strb r2, [r3, #26] hadc1.Init.NbrOfConversion = 1; 8000404: 4b1f ldr r3, [pc, #124] @ (8000484 ) 8000406: 2201 movs r2, #1 8000408: 61da str r2, [r3, #28] hadc1.Init.DiscontinuousConvMode = ENABLE; 800040a: 4b1e ldr r3, [pc, #120] @ (8000484 ) 800040c: 2220 movs r2, #32 800040e: 2101 movs r1, #1 8000410: 5499 strb r1, [r3, r2] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000412: 4b1c ldr r3, [pc, #112] @ (8000484 ) 8000414: 2200 movs r2, #0 8000416: 625a str r2, [r3, #36] @ 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 8000418: 4b1a ldr r3, [pc, #104] @ (8000484 ) 800041a: 2200 movs r2, #0 800041c: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.DMAContinuousRequests = DISABLE; 800041e: 4b19 ldr r3, [pc, #100] @ (8000484 ) 8000420: 222c movs r2, #44 @ 0x2c 8000422: 2100 movs r1, #0 8000424: 5499 strb r1, [r3, r2] hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000426: 4b17 ldr r3, [pc, #92] @ (8000484 ) 8000428: 2200 movs r2, #0 800042a: 631a str r2, [r3, #48] @ 0x30 hadc1.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_7CYCLES_5; 800042c: 4b15 ldr r3, [pc, #84] @ (8000484 ) 800042e: 2202 movs r2, #2 8000430: 635a str r2, [r3, #52] @ 0x34 hadc1.Init.SamplingTimeCommon2 = ADC_SAMPLETIME_7CYCLES_5; 8000432: 4b14 ldr r3, [pc, #80] @ (8000484 ) 8000434: 2202 movs r2, #2 8000436: 639a str r2, [r3, #56] @ 0x38 hadc1.Init.OversamplingMode = DISABLE; 8000438: 4b12 ldr r3, [pc, #72] @ (8000484 ) 800043a: 223c movs r2, #60 @ 0x3c 800043c: 2100 movs r1, #0 800043e: 5499 strb r1, [r3, r2] hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH; 8000440: 4b10 ldr r3, [pc, #64] @ (8000484 ) 8000442: 2200 movs r2, #0 8000444: 64da str r2, [r3, #76] @ 0x4c if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000446: 4b0f ldr r3, [pc, #60] @ (8000484 ) 8000448: 0018 movs r0, r3 800044a: f001 fba5 bl 8001b98 800044e: 1e03 subs r3, r0, #0 8000450: d001 beq.n 8000456 { Error_Handler(); 8000452: f000 f9e1 bl 8000818 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000456: 1d3b adds r3, r7, #4 8000458: 4a0c ldr r2, [pc, #48] @ (800048c ) 800045a: 601a str r2, [r3, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 800045c: 1d3b adds r3, r7, #4 800045e: 2200 movs r2, #0 8000460: 605a str r2, [r3, #4] sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_1; 8000462: 1d3b adds r3, r7, #4 8000464: 2200 movs r2, #0 8000466: 609a str r2, [r3, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000468: 1d3a adds r2, r7, #4 800046a: 4b06 ldr r3, [pc, #24] @ (8000484 ) 800046c: 0011 movs r1, r2 800046e: 0018 movs r0, r3 8000470: f001 fe52 bl 8002118 8000474: 1e03 subs r3, r0, #0 8000476: d001 beq.n 800047c { Error_Handler(); 8000478: f000 f9ce bl 8000818 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 800047c: 46c0 nop @ (mov r8, r8) 800047e: 46bd mov sp, r7 8000480: b004 add sp, #16 8000482: bd80 pop {r7, pc} 8000484: 200001b4 .word 0x200001b4 8000488: 40012400 .word 0x40012400 800048c: 10000010 .word 0x10000010 08000490 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8000490: b580 push {r7, lr} 8000492: b098 sub sp, #96 @ 0x60 8000494: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000496: 2354 movs r3, #84 @ 0x54 8000498: 18fb adds r3, r7, r3 800049a: 0018 movs r0, r3 800049c: 230c movs r3, #12 800049e: 001a movs r2, r3 80004a0: 2100 movs r1, #0 80004a2: f005 fd9d bl 8005fe0 TIM_OC_InitTypeDef sConfigOC = {0}; 80004a6: 2338 movs r3, #56 @ 0x38 80004a8: 18fb adds r3, r7, r3 80004aa: 0018 movs r0, r3 80004ac: 231c movs r3, #28 80004ae: 001a movs r2, r3 80004b0: 2100 movs r1, #0 80004b2: f005 fd95 bl 8005fe0 TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 80004b6: 1d3b adds r3, r7, #4 80004b8: 0018 movs r0, r3 80004ba: 2334 movs r3, #52 @ 0x34 80004bc: 001a movs r2, r3 80004be: 2100 movs r1, #0 80004c0: f005 fd8e bl 8005fe0 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 80004c4: 4b50 ldr r3, [pc, #320] @ (8000608 ) 80004c6: 4a51 ldr r2, [pc, #324] @ (800060c ) 80004c8: 601a str r2, [r3, #0] htim1.Init.Prescaler = 63; 80004ca: 4b4f ldr r3, [pc, #316] @ (8000608 ) 80004cc: 223f movs r2, #63 @ 0x3f 80004ce: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 80004d0: 4b4d ldr r3, [pc, #308] @ (8000608 ) 80004d2: 2200 movs r2, #0 80004d4: 609a str r2, [r3, #8] htim1.Init.Period = 20000; 80004d6: 4b4c ldr r3, [pc, #304] @ (8000608 ) 80004d8: 4a4d ldr r2, [pc, #308] @ (8000610 ) 80004da: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80004dc: 4b4a ldr r3, [pc, #296] @ (8000608 ) 80004de: 2200 movs r2, #0 80004e0: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 80004e2: 4b49 ldr r3, [pc, #292] @ (8000608 ) 80004e4: 2200 movs r2, #0 80004e6: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80004e8: 4b47 ldr r3, [pc, #284] @ (8000608 ) 80004ea: 2280 movs r2, #128 @ 0x80 80004ec: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 80004ee: 4b46 ldr r3, [pc, #280] @ (8000608 ) 80004f0: 0018 movs r0, r3 80004f2: f004 f821 bl 8004538 80004f6: 1e03 subs r3, r0, #0 80004f8: d001 beq.n 80004fe { Error_Handler(); 80004fa: f000 f98d bl 8000818 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80004fe: 2154 movs r1, #84 @ 0x54 8000500: 187b adds r3, r7, r1 8000502: 2200 movs r2, #0 8000504: 601a str r2, [r3, #0] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8000506: 187b adds r3, r7, r1 8000508: 2200 movs r2, #0 800050a: 605a str r2, [r3, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800050c: 187b adds r3, r7, r1 800050e: 2200 movs r2, #0 8000510: 609a str r2, [r3, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000512: 187a adds r2, r7, r1 8000514: 4b3c ldr r3, [pc, #240] @ (8000608 ) 8000516: 0011 movs r1, r2 8000518: 0018 movs r0, r3 800051a: f004 fc7b bl 8004e14 800051e: 1e03 subs r3, r0, #0 8000520: d001 beq.n 8000526 { Error_Handler(); 8000522: f000 f979 bl 8000818 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8000526: 2138 movs r1, #56 @ 0x38 8000528: 187b adds r3, r7, r1 800052a: 2260 movs r2, #96 @ 0x60 800052c: 601a str r2, [r3, #0] sConfigOC.Pulse = 0; 800052e: 187b adds r3, r7, r1 8000530: 2200 movs r2, #0 8000532: 605a str r2, [r3, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8000534: 187b adds r3, r7, r1 8000536: 2200 movs r2, #0 8000538: 609a str r2, [r3, #8] sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 800053a: 187b adds r3, r7, r1 800053c: 2200 movs r2, #0 800053e: 60da str r2, [r3, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8000540: 187b adds r3, r7, r1 8000542: 2200 movs r2, #0 8000544: 611a str r2, [r3, #16] sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 8000546: 187b adds r3, r7, r1 8000548: 2200 movs r2, #0 800054a: 615a str r2, [r3, #20] sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 800054c: 187b adds r3, r7, r1 800054e: 2200 movs r2, #0 8000550: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8000552: 1879 adds r1, r7, r1 8000554: 4b2c ldr r3, [pc, #176] @ (8000608 ) 8000556: 2200 movs r2, #0 8000558: 0018 movs r0, r3 800055a: f004 f845 bl 80045e8 800055e: 1e03 subs r3, r0, #0 8000560: d001 beq.n 8000566 { Error_Handler(); 8000562: f000 f959 bl 8000818 } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8000566: 2338 movs r3, #56 @ 0x38 8000568: 18f9 adds r1, r7, r3 800056a: 4b27 ldr r3, [pc, #156] @ (8000608 ) 800056c: 2204 movs r2, #4 800056e: 0018 movs r0, r3 8000570: f004 f83a bl 80045e8 8000574: 1e03 subs r3, r0, #0 8000576: d001 beq.n 800057c { Error_Handler(); 8000578: f000 f94e bl 8000818 } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800057c: 2338 movs r3, #56 @ 0x38 800057e: 18f9 adds r1, r7, r3 8000580: 4b21 ldr r3, [pc, #132] @ (8000608 ) 8000582: 220c movs r2, #12 8000584: 0018 movs r0, r3 8000586: f004 f82f bl 80045e8 800058a: 1e03 subs r3, r0, #0 800058c: d001 beq.n 8000592 { Error_Handler(); 800058e: f000 f943 bl 8000818 } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 8000592: 1d3b adds r3, r7, #4 8000594: 2200 movs r2, #0 8000596: 601a str r2, [r3, #0] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8000598: 1d3b adds r3, r7, #4 800059a: 2200 movs r2, #0 800059c: 605a str r2, [r3, #4] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 800059e: 1d3b adds r3, r7, #4 80005a0: 2200 movs r2, #0 80005a2: 609a str r2, [r3, #8] sBreakDeadTimeConfig.DeadTime = 0; 80005a4: 1d3b adds r3, r7, #4 80005a6: 2200 movs r2, #0 80005a8: 60da str r2, [r3, #12] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 80005aa: 1d3b adds r3, r7, #4 80005ac: 2200 movs r2, #0 80005ae: 611a str r2, [r3, #16] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 80005b0: 1d3b adds r3, r7, #4 80005b2: 2280 movs r2, #128 @ 0x80 80005b4: 0192 lsls r2, r2, #6 80005b6: 615a str r2, [r3, #20] sBreakDeadTimeConfig.BreakFilter = 0; 80005b8: 1d3b adds r3, r7, #4 80005ba: 2200 movs r2, #0 80005bc: 619a str r2, [r3, #24] sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT; 80005be: 1d3b adds r3, r7, #4 80005c0: 2200 movs r2, #0 80005c2: 61da str r2, [r3, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 80005c4: 1d3b adds r3, r7, #4 80005c6: 2200 movs r2, #0 80005c8: 621a str r2, [r3, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 80005ca: 1d3b adds r3, r7, #4 80005cc: 2280 movs r2, #128 @ 0x80 80005ce: 0492 lsls r2, r2, #18 80005d0: 625a str r2, [r3, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 80005d2: 1d3b adds r3, r7, #4 80005d4: 2200 movs r2, #0 80005d6: 629a str r2, [r3, #40] @ 0x28 sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT; 80005d8: 1d3b adds r3, r7, #4 80005da: 2200 movs r2, #0 80005dc: 62da str r2, [r3, #44] @ 0x2c sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 80005de: 1d3b adds r3, r7, #4 80005e0: 2200 movs r2, #0 80005e2: 631a str r2, [r3, #48] @ 0x30 if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 80005e4: 1d3a adds r2, r7, #4 80005e6: 4b08 ldr r3, [pc, #32] @ (8000608 ) 80005e8: 0011 movs r1, r2 80005ea: 0018 movs r0, r3 80005ec: f004 fc74 bl 8004ed8 80005f0: 1e03 subs r3, r0, #0 80005f2: d001 beq.n 80005f8 { Error_Handler(); 80005f4: f000 f910 bl 8000818 } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 80005f8: 4b03 ldr r3, [pc, #12] @ (8000608 ) 80005fa: 0018 movs r0, r3 80005fc: f000 fa9c bl 8000b38 } 8000600: 46c0 nop @ (mov r8, r8) 8000602: 46bd mov sp, r7 8000604: b018 add sp, #96 @ 0x60 8000606: bd80 pop {r7, pc} 8000608: 20000274 .word 0x20000274 800060c: 40012c00 .word 0x40012c00 8000610: 00004e20 .word 0x00004e20 08000614 : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 8000614: b580 push {r7, lr} 8000616: b08a sub sp, #40 @ 0x28 8000618: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 800061a: 231c movs r3, #28 800061c: 18fb adds r3, r7, r3 800061e: 0018 movs r0, r3 8000620: 230c movs r3, #12 8000622: 001a movs r2, r3 8000624: 2100 movs r1, #0 8000626: f005 fcdb bl 8005fe0 TIM_OC_InitTypeDef sConfigOC = {0}; 800062a: 003b movs r3, r7 800062c: 0018 movs r0, r3 800062e: 231c movs r3, #28 8000630: 001a movs r2, r3 8000632: 2100 movs r1, #0 8000634: f005 fcd4 bl 8005fe0 /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8000638: 4b29 ldr r3, [pc, #164] @ (80006e0 ) 800063a: 4a2a ldr r2, [pc, #168] @ (80006e4 ) 800063c: 601a str r2, [r3, #0] htim3.Init.Prescaler = 63; 800063e: 4b28 ldr r3, [pc, #160] @ (80006e0 ) 8000640: 223f movs r2, #63 @ 0x3f 8000642: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8000644: 4b26 ldr r3, [pc, #152] @ (80006e0 ) 8000646: 2200 movs r2, #0 8000648: 609a str r2, [r3, #8] htim3.Init.Period = 20000; 800064a: 4b25 ldr r3, [pc, #148] @ (80006e0 ) 800064c: 4a26 ldr r2, [pc, #152] @ (80006e8 ) 800064e: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000650: 4b23 ldr r3, [pc, #140] @ (80006e0 ) 8000652: 2200 movs r2, #0 8000654: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8000656: 4b22 ldr r3, [pc, #136] @ (80006e0 ) 8000658: 2280 movs r2, #128 @ 0x80 800065a: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800065c: 4b20 ldr r3, [pc, #128] @ (80006e0 ) 800065e: 0018 movs r0, r3 8000660: f003 ff6a bl 8004538 8000664: 1e03 subs r3, r0, #0 8000666: d001 beq.n 800066c { Error_Handler(); 8000668: f000 f8d6 bl 8000818 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800066c: 211c movs r1, #28 800066e: 187b adds r3, r7, r1 8000670: 2200 movs r2, #0 8000672: 601a str r2, [r3, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000674: 187b adds r3, r7, r1 8000676: 2200 movs r2, #0 8000678: 609a str r2, [r3, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800067a: 187a adds r2, r7, r1 800067c: 4b18 ldr r3, [pc, #96] @ (80006e0 ) 800067e: 0011 movs r1, r2 8000680: 0018 movs r0, r3 8000682: f004 fbc7 bl 8004e14 8000686: 1e03 subs r3, r0, #0 8000688: d001 beq.n 800068e { Error_Handler(); 800068a: f000 f8c5 bl 8000818 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800068e: 003b movs r3, r7 8000690: 2260 movs r2, #96 @ 0x60 8000692: 601a str r2, [r3, #0] sConfigOC.Pulse = 0; 8000694: 003b movs r3, r7 8000696: 2200 movs r2, #0 8000698: 605a str r2, [r3, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800069a: 003b movs r3, r7 800069c: 2200 movs r2, #0 800069e: 609a str r2, [r3, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80006a0: 003b movs r3, r7 80006a2: 2200 movs r2, #0 80006a4: 611a str r2, [r3, #16] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80006a6: 0039 movs r1, r7 80006a8: 4b0d ldr r3, [pc, #52] @ (80006e0 ) 80006aa: 2200 movs r2, #0 80006ac: 0018 movs r0, r3 80006ae: f003 ff9b bl 80045e8 80006b2: 1e03 subs r3, r0, #0 80006b4: d001 beq.n 80006ba { Error_Handler(); 80006b6: f000 f8af bl 8000818 } if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 80006ba: 0039 movs r1, r7 80006bc: 4b08 ldr r3, [pc, #32] @ (80006e0 ) 80006be: 2204 movs r2, #4 80006c0: 0018 movs r0, r3 80006c2: f003 ff91 bl 80045e8 80006c6: 1e03 subs r3, r0, #0 80006c8: d001 beq.n 80006ce { Error_Handler(); 80006ca: f000 f8a5 bl 8000818 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 80006ce: 4b04 ldr r3, [pc, #16] @ (80006e0 ) 80006d0: 0018 movs r0, r3 80006d2: f000 fa31 bl 8000b38 } 80006d6: 46c0 nop @ (mov r8, r8) 80006d8: 46bd mov sp, r7 80006da: b00a add sp, #40 @ 0x28 80006dc: bd80 pop {r7, pc} 80006de: 46c0 nop @ (mov r8, r8) 80006e0: 200002c0 .word 0x200002c0 80006e4: 40000400 .word 0x40000400 80006e8: 00004e20 .word 0x00004e20 080006ec : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { 80006ec: b580 push {r7, lr} 80006ee: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 80006f0: 4b15 ldr r3, [pc, #84] @ (8000748 ) 80006f2: 4a16 ldr r2, [pc, #88] @ (800074c ) 80006f4: 601a str r2, [r3, #0] huart2.Init.BaudRate = 420000; 80006f6: 4b14 ldr r3, [pc, #80] @ (8000748 ) 80006f8: 4a15 ldr r2, [pc, #84] @ (8000750 ) 80006fa: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 80006fc: 4b12 ldr r3, [pc, #72] @ (8000748 ) 80006fe: 2200 movs r2, #0 8000700: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8000702: 4b11 ldr r3, [pc, #68] @ (8000748 ) 8000704: 2200 movs r2, #0 8000706: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 8000708: 4b0f ldr r3, [pc, #60] @ (8000748 ) 800070a: 2200 movs r2, #0 800070c: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800070e: 4b0e ldr r3, [pc, #56] @ (8000748 ) 8000710: 220c movs r2, #12 8000712: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000714: 4b0c ldr r3, [pc, #48] @ (8000748 ) 8000716: 2200 movs r2, #0 8000718: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800071a: 4b0b ldr r3, [pc, #44] @ (8000748 ) 800071c: 2200 movs r2, #0 800071e: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000720: 4b09 ldr r3, [pc, #36] @ (8000748 ) 8000722: 2200 movs r2, #0 8000724: 621a str r2, [r3, #32] huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000726: 4b08 ldr r3, [pc, #32] @ (8000748 ) 8000728: 2200 movs r2, #0 800072a: 625a str r2, [r3, #36] @ 0x24 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 800072c: 4b06 ldr r3, [pc, #24] @ (8000748 ) 800072e: 2200 movs r2, #0 8000730: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart2) != HAL_OK) 8000732: 4b05 ldr r3, [pc, #20] @ (8000748 ) 8000734: 0018 movs r0, r3 8000736: f004 fc6b bl 8005010 800073a: 1e03 subs r3, r0, #0 800073c: d001 beq.n 8000742 { Error_Handler(); 800073e: f000 f86b bl 8000818 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8000742: 46c0 nop @ (mov r8, r8) 8000744: 46bd mov sp, r7 8000746: bd80 pop {r7, pc} 8000748: 2000030c .word 0x2000030c 800074c: 40004400 .word 0x40004400 8000750: 000668a0 .word 0x000668a0 08000754 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8000754: b580 push {r7, lr} 8000756: b082 sub sp, #8 8000758: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800075a: 4b10 ldr r3, [pc, #64] @ (800079c ) 800075c: 6b9a ldr r2, [r3, #56] @ 0x38 800075e: 4b0f ldr r3, [pc, #60] @ (800079c ) 8000760: 2101 movs r1, #1 8000762: 430a orrs r2, r1 8000764: 639a str r2, [r3, #56] @ 0x38 8000766: 4b0d ldr r3, [pc, #52] @ (800079c ) 8000768: 6b9b ldr r3, [r3, #56] @ 0x38 800076a: 2201 movs r2, #1 800076c: 4013 ands r3, r2 800076e: 607b str r3, [r7, #4] 8000770: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel2_3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0); 8000772: 2200 movs r2, #0 8000774: 2100 movs r1, #0 8000776: 200a movs r0, #10 8000778: f002 fa9a bl 8002cb0 HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); 800077c: 200a movs r0, #10 800077e: f002 faac bl 8002cda /* DMA1_Ch4_5_DMAMUX1_OVR_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Ch4_5_DMAMUX1_OVR_IRQn, 0, 0); 8000782: 2200 movs r2, #0 8000784: 2100 movs r1, #0 8000786: 200b movs r0, #11 8000788: f002 fa92 bl 8002cb0 HAL_NVIC_EnableIRQ(DMA1_Ch4_5_DMAMUX1_OVR_IRQn); 800078c: 200b movs r0, #11 800078e: f002 faa4 bl 8002cda } 8000792: 46c0 nop @ (mov r8, r8) 8000794: 46bd mov sp, r7 8000796: b002 add sp, #8 8000798: bd80 pop {r7, pc} 800079a: 46c0 nop @ (mov r8, r8) 800079c: 40021000 .word 0x40021000 080007a0 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80007a0: b590 push {r4, r7, lr} 80007a2: b089 sub sp, #36 @ 0x24 80007a4: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007a6: 240c movs r4, #12 80007a8: 193b adds r3, r7, r4 80007aa: 0018 movs r0, r3 80007ac: 2314 movs r3, #20 80007ae: 001a movs r2, r3 80007b0: 2100 movs r1, #0 80007b2: f005 fc15 bl 8005fe0 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80007b6: 4b16 ldr r3, [pc, #88] @ (8000810 ) 80007b8: 6b5a ldr r2, [r3, #52] @ 0x34 80007ba: 4b15 ldr r3, [pc, #84] @ (8000810 ) 80007bc: 2102 movs r1, #2 80007be: 430a orrs r2, r1 80007c0: 635a str r2, [r3, #52] @ 0x34 80007c2: 4b13 ldr r3, [pc, #76] @ (8000810 ) 80007c4: 6b5b ldr r3, [r3, #52] @ 0x34 80007c6: 2202 movs r2, #2 80007c8: 4013 ands r3, r2 80007ca: 60bb str r3, [r7, #8] 80007cc: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 80007ce: 4b10 ldr r3, [pc, #64] @ (8000810 ) 80007d0: 6b5a ldr r2, [r3, #52] @ 0x34 80007d2: 4b0f ldr r3, [pc, #60] @ (8000810 ) 80007d4: 2101 movs r1, #1 80007d6: 430a orrs r2, r1 80007d8: 635a str r2, [r3, #52] @ 0x34 80007da: 4b0d ldr r3, [pc, #52] @ (8000810 ) 80007dc: 6b5b ldr r3, [r3, #52] @ 0x34 80007de: 2201 movs r2, #1 80007e0: 4013 ands r3, r2 80007e2: 607b str r3, [r7, #4] 80007e4: 687b ldr r3, [r7, #4] /*Configure GPIO pins : SET_DEFAULT_Pin SET_FAILSAFE_Pin */ GPIO_InitStruct.Pin = SET_DEFAULT_Pin|SET_FAILSAFE_Pin; 80007e6: 193b adds r3, r7, r4 80007e8: 22c0 movs r2, #192 @ 0xc0 80007ea: 0092 lsls r2, r2, #2 80007ec: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80007ee: 193b adds r3, r7, r4 80007f0: 2200 movs r2, #0 80007f2: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 80007f4: 193b adds r3, r7, r4 80007f6: 2201 movs r2, #1 80007f8: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80007fa: 193b adds r3, r7, r4 80007fc: 4a05 ldr r2, [pc, #20] @ (8000814 ) 80007fe: 0019 movs r1, r3 8000800: 0010 movs r0, r2 8000802: f002 feeb bl 80035dc } 8000806: 46c0 nop @ (mov r8, r8) 8000808: 46bd mov sp, r7 800080a: b009 add sp, #36 @ 0x24 800080c: bd90 pop {r4, r7, pc} 800080e: 46c0 nop @ (mov r8, r8) 8000810: 40021000 .word 0x40021000 8000814: 50000400 .word 0x50000400 08000818 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000818: b580 push {r7, lr} 800081a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800081c: b672 cpsid i } 800081e: 46c0 nop @ (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000820: 46c0 nop @ (mov r8, r8) 8000822: e7fd b.n 8000820 08000824 : #include "settings.h" #include "stm32g0xx_hal_flash.h" SettingsStruct Settings; void SettingsInit(void) { 8000824: b580 push {r7, lr} 8000826: af00 add r7, sp, #0 SettingsLoad(); 8000828: f000 f87c bl 8000924 if (Settings.start[0] == 0xFFFF) { // Flash memory is clear 800082c: 4b04 ldr r3, [pc, #16] @ (8000840 ) 800082e: 881b ldrh r3, [r3, #0] 8000830: 4a04 ldr r2, [pc, #16] @ (8000844 ) 8000832: 4293 cmp r3, r2 8000834: d101 bne.n 800083a SettinsDefault(); 8000836: f000 f807 bl 8000848 } } 800083a: 46c0 nop @ (mov r8, r8) 800083c: 46bd mov sp, r7 800083e: bd80 pop {r7, pc} 8000840: 20000458 .word 0x20000458 8000844: 0000ffff .word 0x0000ffff 08000848 : void SettinsDefault(void) { 8000848: b580 push {r7, lr} 800084a: b082 sub sp, #8 800084c: af00 add r7, sp, #0 // Default Value unsigned int ch; for(ch=0; ch<5; ch++) { 800084e: 2300 movs r3, #0 8000850: 607b str r3, [r7, #4] 8000852: e010 b.n 8000876 Settings.start[ch] = 1000; 8000854: 4b0c ldr r3, [pc, #48] @ (8000888 ) 8000856: 687a ldr r2, [r7, #4] 8000858: 0052 lsls r2, r2, #1 800085a: 21fa movs r1, #250 @ 0xfa 800085c: 0089 lsls r1, r1, #2 800085e: 52d1 strh r1, [r2, r3] Settings.fail[ch] = 0; 8000860: 4a09 ldr r2, [pc, #36] @ (8000888 ) 8000862: 687b ldr r3, [r7, #4] 8000864: 3304 adds r3, #4 8000866: 005b lsls r3, r3, #1 8000868: 18d3 adds r3, r2, r3 800086a: 3302 adds r3, #2 800086c: 2200 movs r2, #0 800086e: 801a strh r2, [r3, #0] for(ch=0; ch<5; ch++) { 8000870: 687b ldr r3, [r7, #4] 8000872: 3301 adds r3, #1 8000874: 607b str r3, [r7, #4] 8000876: 687b ldr r3, [r7, #4] 8000878: 2b04 cmp r3, #4 800087a: d9eb bls.n 8000854 } SettingsSave(); 800087c: f000 f806 bl 800088c } 8000880: 46c0 nop @ (mov r8, r8) 8000882: 46bd mov sp, r7 8000884: b002 add sp, #8 8000886: bd80 pop {r7, pc} 8000888: 20000458 .word 0x20000458 0800088c : void SettingsSave(void) { 800088c: b580 push {r7, lr} 800088e: b08a sub sp, #40 @ 0x28 8000890: af00 add r7, sp, #0 uint32_t PageError = 0; 8000892: 2300 movs r3, #0 8000894: 613b str r3, [r7, #16] FLASH_EraseInitTypeDef EraseInitStruct; HAL_FLASH_Unlock(); 8000896: f002 fd49 bl 800332c EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; 800089a: 003b movs r3, r7 800089c: 2202 movs r2, #2 800089e: 601a str r2, [r3, #0] EraseInitStruct.Page = 15; //FLASH_PAGE_NB - 1; 80008a0: 003b movs r3, r7 80008a2: 220f movs r2, #15 80008a4: 609a str r2, [r3, #8] EraseInitStruct.NbPages = 1; 80008a6: 003b movs r3, r7 80008a8: 2201 movs r2, #1 80008aa: 60da str r2, [r3, #12] if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) == HAL_OK) 80008ac: 2310 movs r3, #16 80008ae: 18fa adds r2, r7, r3 80008b0: 003b movs r3, r7 80008b2: 0011 movs r1, r2 80008b4: 0018 movs r0, r3 80008b6: f002 fded bl 8003494 80008ba: 1e03 subs r3, r0, #0 80008bc: d127 bne.n 800090e { // Write setting uint64_t *source_addr = (void *)&Settings; 80008be: 4b17 ldr r3, [pc, #92] @ (800091c ) 80008c0: 627b str r3, [r7, #36] @ 0x24 uint64_t dest_addr = (uint64_t) FLASH_SETTINGS_START_ADDR; 80008c2: 4a17 ldr r2, [pc, #92] @ (8000920 ) 80008c4: 2300 movs r3, #0 80008c6: 61ba str r2, [r7, #24] 80008c8: 61fb str r3, [r7, #28] for (uint16_t i=0; i HAL_FLASH_Program(FLASH_CR_PG, dest_addr, *source_addr); 80008d4: 69b9 ldr r1, [r7, #24] 80008d6: 6a7b ldr r3, [r7, #36] @ 0x24 80008d8: 681a ldr r2, [r3, #0] 80008da: 685b ldr r3, [r3, #4] 80008dc: 2001 movs r0, #1 80008de: f002 fcd7 bl 8003290 source_addr++; 80008e2: 6a7b ldr r3, [r7, #36] @ 0x24 80008e4: 3308 adds r3, #8 80008e6: 627b str r3, [r7, #36] @ 0x24 dest_addr = dest_addr + 8; 80008e8: 69ba ldr r2, [r7, #24] 80008ea: 69fb ldr r3, [r7, #28] 80008ec: 2008 movs r0, #8 80008ee: 2100 movs r1, #0 80008f0: 1812 adds r2, r2, r0 80008f2: 414b adcs r3, r1 80008f4: 61ba str r2, [r7, #24] 80008f6: 61fb str r3, [r7, #28] for (uint16_t i=0; i } } HAL_FLASH_Lock(); 800090e: f002 fd31 bl 8003374 } 8000912: 46c0 nop @ (mov r8, r8) 8000914: 46bd mov sp, r7 8000916: b00a add sp, #40 @ 0x28 8000918: bd80 pop {r7, pc} 800091a: 46c0 nop @ (mov r8, r8) 800091c: 20000458 .word 0x20000458 8000920: 08007800 .word 0x08007800 08000924 : void SettingsLoad(void) { 8000924: b580 push {r7, lr} 8000926: b084 sub sp, #16 8000928: af00 add r7, sp, #0 uint32_t *source_addr = (uint32_t *)FLASH_SETTINGS_START_ADDR; 800092a: 4b10 ldr r3, [pc, #64] @ (800096c ) 800092c: 60fb str r3, [r7, #12] uint32_t *dest_addr = (void *)&Settings; 800092e: 4b10 ldr r3, [pc, #64] @ (8000970 ) 8000930: 60bb str r3, [r7, #8] for (uint16_t i=0; i *dest_addr = *(__IO uint32_t*)source_addr; 800093a: 68fb ldr r3, [r7, #12] 800093c: 681a ldr r2, [r3, #0] 800093e: 68bb ldr r3, [r7, #8] 8000940: 601a str r2, [r3, #0] source_addr++; 8000942: 68fb ldr r3, [r7, #12] 8000944: 3304 adds r3, #4 8000946: 60fb str r3, [r7, #12] dest_addr++; 8000948: 68bb ldr r3, [r7, #8] 800094a: 3304 adds r3, #4 800094c: 60bb str r3, [r7, #8] for (uint16_t i=0; i } } 8000960: 46c0 nop @ (mov r8, r8) 8000962: 46c0 nop @ (mov r8, r8) 8000964: 46bd mov sp, r7 8000966: b004 add sp, #16 8000968: bd80 pop {r7, pc} 800096a: 46c0 nop @ (mov r8, r8) 800096c: 08007800 .word 0x08007800 8000970: 20000458 .word 0x20000458 08000974 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000974: b580 push {r7, lr} 8000976: b082 sub sp, #8 8000978: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800097a: 4b0f ldr r3, [pc, #60] @ (80009b8 ) 800097c: 6c1a ldr r2, [r3, #64] @ 0x40 800097e: 4b0e ldr r3, [pc, #56] @ (80009b8 ) 8000980: 2101 movs r1, #1 8000982: 430a orrs r2, r1 8000984: 641a str r2, [r3, #64] @ 0x40 8000986: 4b0c ldr r3, [pc, #48] @ (80009b8 ) 8000988: 6c1b ldr r3, [r3, #64] @ 0x40 800098a: 2201 movs r2, #1 800098c: 4013 ands r3, r2 800098e: 607b str r3, [r7, #4] 8000990: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000992: 4b09 ldr r3, [pc, #36] @ (80009b8 ) 8000994: 6bda ldr r2, [r3, #60] @ 0x3c 8000996: 4b08 ldr r3, [pc, #32] @ (80009b8 ) 8000998: 2180 movs r1, #128 @ 0x80 800099a: 0549 lsls r1, r1, #21 800099c: 430a orrs r2, r1 800099e: 63da str r2, [r3, #60] @ 0x3c 80009a0: 4b05 ldr r3, [pc, #20] @ (80009b8 ) 80009a2: 6bda ldr r2, [r3, #60] @ 0x3c 80009a4: 2380 movs r3, #128 @ 0x80 80009a6: 055b lsls r3, r3, #21 80009a8: 4013 ands r3, r2 80009aa: 603b str r3, [r7, #0] 80009ac: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80009ae: 46c0 nop @ (mov r8, r8) 80009b0: 46bd mov sp, r7 80009b2: b002 add sp, #8 80009b4: bd80 pop {r7, pc} 80009b6: 46c0 nop @ (mov r8, r8) 80009b8: 40021000 .word 0x40021000 080009bc : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 80009bc: b590 push {r4, r7, lr} 80009be: b091 sub sp, #68 @ 0x44 80009c0: af00 add r7, sp, #0 80009c2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80009c4: 232c movs r3, #44 @ 0x2c 80009c6: 18fb adds r3, r7, r3 80009c8: 0018 movs r0, r3 80009ca: 2314 movs r3, #20 80009cc: 001a movs r2, r3 80009ce: 2100 movs r1, #0 80009d0: f005 fb06 bl 8005fe0 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 80009d4: 2414 movs r4, #20 80009d6: 193b adds r3, r7, r4 80009d8: 0018 movs r0, r3 80009da: 2318 movs r3, #24 80009dc: 001a movs r2, r3 80009de: 2100 movs r1, #0 80009e0: f005 fafe bl 8005fe0 if(hadc->Instance==ADC1) 80009e4: 687b ldr r3, [r7, #4] 80009e6: 681b ldr r3, [r3, #0] 80009e8: 4a35 ldr r2, [pc, #212] @ (8000ac0 ) 80009ea: 4293 cmp r3, r2 80009ec: d164 bne.n 8000ab8 /* USER CODE END ADC1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 80009ee: 193b adds r3, r7, r4 80009f0: 2280 movs r2, #128 @ 0x80 80009f2: 01d2 lsls r2, r2, #7 80009f4: 601a str r2, [r3, #0] PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK; 80009f6: 193b adds r3, r7, r4 80009f8: 2200 movs r2, #0 80009fa: 611a str r2, [r3, #16] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80009fc: 193b adds r3, r7, r4 80009fe: 0018 movs r0, r3 8000a00: f003 fc74 bl 80042ec 8000a04: 1e03 subs r3, r0, #0 8000a06: d001 beq.n 8000a0c { Error_Handler(); 8000a08: f7ff ff06 bl 8000818 } /* Peripheral clock enable */ __HAL_RCC_ADC_CLK_ENABLE(); 8000a0c: 4b2d ldr r3, [pc, #180] @ (8000ac4 ) 8000a0e: 6c1a ldr r2, [r3, #64] @ 0x40 8000a10: 4b2c ldr r3, [pc, #176] @ (8000ac4 ) 8000a12: 2180 movs r1, #128 @ 0x80 8000a14: 0349 lsls r1, r1, #13 8000a16: 430a orrs r2, r1 8000a18: 641a str r2, [r3, #64] @ 0x40 8000a1a: 4b2a ldr r3, [pc, #168] @ (8000ac4 ) 8000a1c: 6c1a ldr r2, [r3, #64] @ 0x40 8000a1e: 2380 movs r3, #128 @ 0x80 8000a20: 035b lsls r3, r3, #13 8000a22: 4013 ands r3, r2 8000a24: 613b str r3, [r7, #16] 8000a26: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000a28: 4b26 ldr r3, [pc, #152] @ (8000ac4 ) 8000a2a: 6b5a ldr r2, [r3, #52] @ 0x34 8000a2c: 4b25 ldr r3, [pc, #148] @ (8000ac4 ) 8000a2e: 2101 movs r1, #1 8000a30: 430a orrs r2, r1 8000a32: 635a str r2, [r3, #52] @ 0x34 8000a34: 4b23 ldr r3, [pc, #140] @ (8000ac4 ) 8000a36: 6b5b ldr r3, [r3, #52] @ 0x34 8000a38: 2201 movs r2, #1 8000a3a: 4013 ands r3, r2 8000a3c: 60fb str r3, [r7, #12] 8000a3e: 68fb ldr r3, [r7, #12] /**ADC1 GPIO Configuration PA4 ------> ADC1_IN4 */ GPIO_InitStruct.Pin = ADC1_Pin; 8000a40: 212c movs r1, #44 @ 0x2c 8000a42: 187b adds r3, r7, r1 8000a44: 2210 movs r2, #16 8000a46: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000a48: 187b adds r3, r7, r1 8000a4a: 2203 movs r2, #3 8000a4c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000a4e: 187b adds r3, r7, r1 8000a50: 2200 movs r2, #0 8000a52: 609a str r2, [r3, #8] HAL_GPIO_Init(ADC1_GPIO_Port, &GPIO_InitStruct); 8000a54: 187a adds r2, r7, r1 8000a56: 23a0 movs r3, #160 @ 0xa0 8000a58: 05db lsls r3, r3, #23 8000a5a: 0011 movs r1, r2 8000a5c: 0018 movs r0, r3 8000a5e: f002 fdbd bl 80035dc /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel3; 8000a62: 4b19 ldr r3, [pc, #100] @ (8000ac8 ) 8000a64: 4a19 ldr r2, [pc, #100] @ (8000acc ) 8000a66: 601a str r2, [r3, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8000a68: 4b17 ldr r3, [pc, #92] @ (8000ac8 ) 8000a6a: 2205 movs r2, #5 8000a6c: 605a str r2, [r3, #4] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8000a6e: 4b16 ldr r3, [pc, #88] @ (8000ac8 ) 8000a70: 2200 movs r2, #0 8000a72: 609a str r2, [r3, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8000a74: 4b14 ldr r3, [pc, #80] @ (8000ac8 ) 8000a76: 2200 movs r2, #0 8000a78: 60da str r2, [r3, #12] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8000a7a: 4b13 ldr r3, [pc, #76] @ (8000ac8 ) 8000a7c: 2280 movs r2, #128 @ 0x80 8000a7e: 611a str r2, [r3, #16] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8000a80: 4b11 ldr r3, [pc, #68] @ (8000ac8 ) 8000a82: 2280 movs r2, #128 @ 0x80 8000a84: 0052 lsls r2, r2, #1 8000a86: 615a str r2, [r3, #20] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8000a88: 4b0f ldr r3, [pc, #60] @ (8000ac8 ) 8000a8a: 2280 movs r2, #128 @ 0x80 8000a8c: 00d2 lsls r2, r2, #3 8000a8e: 619a str r2, [r3, #24] hdma_adc1.Init.Mode = DMA_NORMAL; 8000a90: 4b0d ldr r3, [pc, #52] @ (8000ac8 ) 8000a92: 2200 movs r2, #0 8000a94: 61da str r2, [r3, #28] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8000a96: 4b0c ldr r3, [pc, #48] @ (8000ac8 ) 8000a98: 2200 movs r2, #0 8000a9a: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8000a9c: 4b0a ldr r3, [pc, #40] @ (8000ac8 ) 8000a9e: 0018 movs r0, r3 8000aa0: f002 f938 bl 8002d14 8000aa4: 1e03 subs r3, r0, #0 8000aa6: d001 beq.n 8000aac { Error_Handler(); 8000aa8: f7ff feb6 bl 8000818 } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8000aac: 687b ldr r3, [r7, #4] 8000aae: 4a06 ldr r2, [pc, #24] @ (8000ac8 ) 8000ab0: 651a str r2, [r3, #80] @ 0x50 8000ab2: 4b05 ldr r3, [pc, #20] @ (8000ac8 ) 8000ab4: 687a ldr r2, [r7, #4] 8000ab6: 629a str r2, [r3, #40] @ 0x28 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8000ab8: 46c0 nop @ (mov r8, r8) 8000aba: 46bd mov sp, r7 8000abc: b011 add sp, #68 @ 0x44 8000abe: bd90 pop {r4, r7, pc} 8000ac0: 40012400 .word 0x40012400 8000ac4: 40021000 .word 0x40021000 8000ac8: 20000218 .word 0x20000218 8000acc: 40020030 .word 0x40020030 08000ad0 : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 8000ad0: b580 push {r7, lr} 8000ad2: b084 sub sp, #16 8000ad4: af00 add r7, sp, #0 8000ad6: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM1) 8000ad8: 687b ldr r3, [r7, #4] 8000ada: 681b ldr r3, [r3, #0] 8000adc: 4a13 ldr r2, [pc, #76] @ (8000b2c ) 8000ade: 4293 cmp r3, r2 8000ae0: d10e bne.n 8000b00 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 8000ae2: 4b13 ldr r3, [pc, #76] @ (8000b30 ) 8000ae4: 6c1a ldr r2, [r3, #64] @ 0x40 8000ae6: 4b12 ldr r3, [pc, #72] @ (8000b30 ) 8000ae8: 2180 movs r1, #128 @ 0x80 8000aea: 0109 lsls r1, r1, #4 8000aec: 430a orrs r2, r1 8000aee: 641a str r2, [r3, #64] @ 0x40 8000af0: 4b0f ldr r3, [pc, #60] @ (8000b30 ) 8000af2: 6c1a ldr r2, [r3, #64] @ 0x40 8000af4: 2380 movs r3, #128 @ 0x80 8000af6: 011b lsls r3, r3, #4 8000af8: 4013 ands r3, r2 8000afa: 60fb str r3, [r7, #12] 8000afc: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8000afe: e010 b.n 8000b22 else if(htim_pwm->Instance==TIM3) 8000b00: 687b ldr r3, [r7, #4] 8000b02: 681b ldr r3, [r3, #0] 8000b04: 4a0b ldr r2, [pc, #44] @ (8000b34 ) 8000b06: 4293 cmp r3, r2 8000b08: d10b bne.n 8000b22 __HAL_RCC_TIM3_CLK_ENABLE(); 8000b0a: 4b09 ldr r3, [pc, #36] @ (8000b30 ) 8000b0c: 6bda ldr r2, [r3, #60] @ 0x3c 8000b0e: 4b08 ldr r3, [pc, #32] @ (8000b30 ) 8000b10: 2102 movs r1, #2 8000b12: 430a orrs r2, r1 8000b14: 63da str r2, [r3, #60] @ 0x3c 8000b16: 4b06 ldr r3, [pc, #24] @ (8000b30 ) 8000b18: 6bdb ldr r3, [r3, #60] @ 0x3c 8000b1a: 2202 movs r2, #2 8000b1c: 4013 ands r3, r2 8000b1e: 60bb str r3, [r7, #8] 8000b20: 68bb ldr r3, [r7, #8] } 8000b22: 46c0 nop @ (mov r8, r8) 8000b24: 46bd mov sp, r7 8000b26: b004 add sp, #16 8000b28: bd80 pop {r7, pc} 8000b2a: 46c0 nop @ (mov r8, r8) 8000b2c: 40012c00 .word 0x40012c00 8000b30: 40021000 .word 0x40021000 8000b34: 40000400 .word 0x40000400 08000b38 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 8000b38: b590 push {r4, r7, lr} 8000b3a: b08b sub sp, #44 @ 0x2c 8000b3c: af00 add r7, sp, #0 8000b3e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000b40: 2414 movs r4, #20 8000b42: 193b adds r3, r7, r4 8000b44: 0018 movs r0, r3 8000b46: 2314 movs r3, #20 8000b48: 001a movs r2, r3 8000b4a: 2100 movs r1, #0 8000b4c: f005 fa48 bl 8005fe0 if(htim->Instance==TIM1) 8000b50: 687b ldr r3, [r7, #4] 8000b52: 681b ldr r3, [r3, #0] 8000b54: 4a3a ldr r2, [pc, #232] @ (8000c40 ) 8000b56: 4293 cmp r3, r2 8000b58: d145 bne.n 8000be6 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8000b5a: 4b3a ldr r3, [pc, #232] @ (8000c44 ) 8000b5c: 6b5a ldr r2, [r3, #52] @ 0x34 8000b5e: 4b39 ldr r3, [pc, #228] @ (8000c44 ) 8000b60: 2101 movs r1, #1 8000b62: 430a orrs r2, r1 8000b64: 635a str r2, [r3, #52] @ 0x34 8000b66: 4b37 ldr r3, [pc, #220] @ (8000c44 ) 8000b68: 6b5b ldr r3, [r3, #52] @ 0x34 8000b6a: 2201 movs r2, #1 8000b6c: 4013 ands r3, r2 8000b6e: 613b str r3, [r7, #16] 8000b70: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000b72: 4b34 ldr r3, [pc, #208] @ (8000c44 ) 8000b74: 6b5a ldr r2, [r3, #52] @ 0x34 8000b76: 4b33 ldr r3, [pc, #204] @ (8000c44 ) 8000b78: 2102 movs r1, #2 8000b7a: 430a orrs r2, r1 8000b7c: 635a str r2, [r3, #52] @ 0x34 8000b7e: 4b31 ldr r3, [pc, #196] @ (8000c44 ) 8000b80: 6b5b ldr r3, [r3, #52] @ 0x34 8000b82: 2202 movs r2, #2 8000b84: 4013 ands r3, r2 8000b86: 60fb str r3, [r7, #12] 8000b88: 68fb ldr r3, [r7, #12] /**TIM1 GPIO Configuration PA8 ------> TIM1_CH1 PA11 [PA9] ------> TIM1_CH4 PB3 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = PWM3_Pin|PWM4_Pin; 8000b8a: 193b adds r3, r7, r4 8000b8c: 2290 movs r2, #144 @ 0x90 8000b8e: 0112 lsls r2, r2, #4 8000b90: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000b92: 193b adds r3, r7, r4 8000b94: 2202 movs r2, #2 8000b96: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b98: 193b adds r3, r7, r4 8000b9a: 2200 movs r2, #0 8000b9c: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000b9e: 193b adds r3, r7, r4 8000ba0: 2200 movs r2, #0 8000ba2: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF2_TIM1; 8000ba4: 193b adds r3, r7, r4 8000ba6: 2202 movs r2, #2 8000ba8: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000baa: 193a adds r2, r7, r4 8000bac: 23a0 movs r3, #160 @ 0xa0 8000bae: 05db lsls r3, r3, #23 8000bb0: 0011 movs r1, r2 8000bb2: 0018 movs r0, r3 8000bb4: f002 fd12 bl 80035dc GPIO_InitStruct.Pin = PWM5_Pin; 8000bb8: 0021 movs r1, r4 8000bba: 187b adds r3, r7, r1 8000bbc: 2208 movs r2, #8 8000bbe: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000bc0: 187b adds r3, r7, r1 8000bc2: 2202 movs r2, #2 8000bc4: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000bc6: 187b adds r3, r7, r1 8000bc8: 2200 movs r2, #0 8000bca: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000bcc: 187b adds r3, r7, r1 8000bce: 2200 movs r2, #0 8000bd0: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 8000bd2: 187b adds r3, r7, r1 8000bd4: 2201 movs r2, #1 8000bd6: 611a str r2, [r3, #16] HAL_GPIO_Init(PWM5_GPIO_Port, &GPIO_InitStruct); 8000bd8: 187b adds r3, r7, r1 8000bda: 4a1b ldr r2, [pc, #108] @ (8000c48 ) 8000bdc: 0019 movs r1, r3 8000bde: 0010 movs r0, r2 8000be0: f002 fcfc bl 80035dc /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 8000be4: e027 b.n 8000c36 else if(htim->Instance==TIM3) 8000be6: 687b ldr r3, [r7, #4] 8000be8: 681b ldr r3, [r3, #0] 8000bea: 4a18 ldr r2, [pc, #96] @ (8000c4c ) 8000bec: 4293 cmp r3, r2 8000bee: d122 bne.n 8000c36 __HAL_RCC_GPIOA_CLK_ENABLE(); 8000bf0: 4b14 ldr r3, [pc, #80] @ (8000c44 ) 8000bf2: 6b5a ldr r2, [r3, #52] @ 0x34 8000bf4: 4b13 ldr r3, [pc, #76] @ (8000c44 ) 8000bf6: 2101 movs r1, #1 8000bf8: 430a orrs r2, r1 8000bfa: 635a str r2, [r3, #52] @ 0x34 8000bfc: 4b11 ldr r3, [pc, #68] @ (8000c44 ) 8000bfe: 6b5b ldr r3, [r3, #52] @ 0x34 8000c00: 2201 movs r2, #1 8000c02: 4013 ands r3, r2 8000c04: 60bb str r3, [r7, #8] 8000c06: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = PWM1_Pin|PWM2_Pin; 8000c08: 2114 movs r1, #20 8000c0a: 187b adds r3, r7, r1 8000c0c: 22c0 movs r2, #192 @ 0xc0 8000c0e: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000c10: 187b adds r3, r7, r1 8000c12: 2202 movs r2, #2 8000c14: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c16: 187b adds r3, r7, r1 8000c18: 2200 movs r2, #0 8000c1a: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c1c: 187b adds r3, r7, r1 8000c1e: 2200 movs r2, #0 8000c20: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_TIM3; 8000c22: 187b adds r3, r7, r1 8000c24: 2201 movs r2, #1 8000c26: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000c28: 187a adds r2, r7, r1 8000c2a: 23a0 movs r3, #160 @ 0xa0 8000c2c: 05db lsls r3, r3, #23 8000c2e: 0011 movs r1, r2 8000c30: 0018 movs r0, r3 8000c32: f002 fcd3 bl 80035dc } 8000c36: 46c0 nop @ (mov r8, r8) 8000c38: 46bd mov sp, r7 8000c3a: b00b add sp, #44 @ 0x2c 8000c3c: bd90 pop {r4, r7, pc} 8000c3e: 46c0 nop @ (mov r8, r8) 8000c40: 40012c00 .word 0x40012c00 8000c44: 40021000 .word 0x40021000 8000c48: 50000400 .word 0x50000400 8000c4c: 40000400 .word 0x40000400 08000c50 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8000c50: b590 push {r4, r7, lr} 8000c52: b08b sub sp, #44 @ 0x2c 8000c54: af00 add r7, sp, #0 8000c56: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000c58: 2414 movs r4, #20 8000c5a: 193b adds r3, r7, r4 8000c5c: 0018 movs r0, r3 8000c5e: 2314 movs r3, #20 8000c60: 001a movs r2, r3 8000c62: 2100 movs r1, #0 8000c64: f005 f9bc bl 8005fe0 if(huart->Instance==USART2) 8000c68: 687b ldr r3, [r7, #4] 8000c6a: 681b ldr r3, [r3, #0] 8000c6c: 4a45 ldr r2, [pc, #276] @ (8000d84 ) 8000c6e: 4293 cmp r3, r2 8000c70: d000 beq.n 8000c74 8000c72: e083 b.n 8000d7c { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8000c74: 4b44 ldr r3, [pc, #272] @ (8000d88 ) 8000c76: 6bda ldr r2, [r3, #60] @ 0x3c 8000c78: 4b43 ldr r3, [pc, #268] @ (8000d88 ) 8000c7a: 2180 movs r1, #128 @ 0x80 8000c7c: 0289 lsls r1, r1, #10 8000c7e: 430a orrs r2, r1 8000c80: 63da str r2, [r3, #60] @ 0x3c 8000c82: 4b41 ldr r3, [pc, #260] @ (8000d88 ) 8000c84: 6bda ldr r2, [r3, #60] @ 0x3c 8000c86: 2380 movs r3, #128 @ 0x80 8000c88: 029b lsls r3, r3, #10 8000c8a: 4013 ands r3, r2 8000c8c: 613b str r3, [r7, #16] 8000c8e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000c90: 4b3d ldr r3, [pc, #244] @ (8000d88 ) 8000c92: 6b5a ldr r2, [r3, #52] @ 0x34 8000c94: 4b3c ldr r3, [pc, #240] @ (8000d88 ) 8000c96: 2101 movs r1, #1 8000c98: 430a orrs r2, r1 8000c9a: 635a str r2, [r3, #52] @ 0x34 8000c9c: 4b3a ldr r3, [pc, #232] @ (8000d88 ) 8000c9e: 6b5b ldr r3, [r3, #52] @ 0x34 8000ca0: 2201 movs r2, #1 8000ca2: 4013 ands r3, r2 8000ca4: 60fb str r3, [r7, #12] 8000ca6: 68fb ldr r3, [r7, #12] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = TX_Pin|RX_Pin; 8000ca8: 0021 movs r1, r4 8000caa: 187b adds r3, r7, r1 8000cac: 220c movs r2, #12 8000cae: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000cb0: 187b adds r3, r7, r1 8000cb2: 2202 movs r2, #2 8000cb4: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cb6: 187b adds r3, r7, r1 8000cb8: 2200 movs r2, #0 8000cba: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000cbc: 187b adds r3, r7, r1 8000cbe: 2200 movs r2, #0 8000cc0: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_USART2; 8000cc2: 187b adds r3, r7, r1 8000cc4: 2201 movs r2, #1 8000cc6: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000cc8: 187a adds r2, r7, r1 8000cca: 23a0 movs r3, #160 @ 0xa0 8000ccc: 05db lsls r3, r3, #23 8000cce: 0011 movs r1, r2 8000cd0: 0018 movs r0, r3 8000cd2: f002 fc83 bl 80035dc /* USART2 DMA Init */ /* USART2_RX Init */ hdma_usart2_rx.Instance = DMA1_Channel4; 8000cd6: 4b2d ldr r3, [pc, #180] @ (8000d8c ) 8000cd8: 4a2d ldr r2, [pc, #180] @ (8000d90 ) 8000cda: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX; 8000cdc: 4b2b ldr r3, [pc, #172] @ (8000d8c ) 8000cde: 2234 movs r2, #52 @ 0x34 8000ce0: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8000ce2: 4b2a ldr r3, [pc, #168] @ (8000d8c ) 8000ce4: 2200 movs r2, #0 8000ce6: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8000ce8: 4b28 ldr r3, [pc, #160] @ (8000d8c ) 8000cea: 2200 movs r2, #0 8000cec: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 8000cee: 4b27 ldr r3, [pc, #156] @ (8000d8c ) 8000cf0: 2280 movs r2, #128 @ 0x80 8000cf2: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8000cf4: 4b25 ldr r3, [pc, #148] @ (8000d8c ) 8000cf6: 2200 movs r2, #0 8000cf8: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8000cfa: 4b24 ldr r3, [pc, #144] @ (8000d8c ) 8000cfc: 2200 movs r2, #0 8000cfe: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_CIRCULAR; 8000d00: 4b22 ldr r3, [pc, #136] @ (8000d8c ) 8000d02: 2220 movs r2, #32 8000d04: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 8000d06: 4b21 ldr r3, [pc, #132] @ (8000d8c ) 8000d08: 2200 movs r2, #0 8000d0a: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 8000d0c: 4b1f ldr r3, [pc, #124] @ (8000d8c ) 8000d0e: 0018 movs r0, r3 8000d10: f002 f800 bl 8002d14 8000d14: 1e03 subs r3, r0, #0 8000d16: d001 beq.n 8000d1c { Error_Handler(); 8000d18: f7ff fd7e bl 8000818 } __HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx); 8000d1c: 687b ldr r3, [r7, #4] 8000d1e: 2180 movs r1, #128 @ 0x80 8000d20: 4a1a ldr r2, [pc, #104] @ (8000d8c ) 8000d22: 505a str r2, [r3, r1] 8000d24: 4b19 ldr r3, [pc, #100] @ (8000d8c ) 8000d26: 687a ldr r2, [r7, #4] 8000d28: 629a str r2, [r3, #40] @ 0x28 /* USART2_TX Init */ hdma_usart2_tx.Instance = DMA1_Channel5; 8000d2a: 4b1a ldr r3, [pc, #104] @ (8000d94 ) 8000d2c: 4a1a ldr r2, [pc, #104] @ (8000d98 ) 8000d2e: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; 8000d30: 4b18 ldr r3, [pc, #96] @ (8000d94 ) 8000d32: 2235 movs r2, #53 @ 0x35 8000d34: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8000d36: 4b17 ldr r3, [pc, #92] @ (8000d94 ) 8000d38: 2210 movs r2, #16 8000d3a: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8000d3c: 4b15 ldr r3, [pc, #84] @ (8000d94 ) 8000d3e: 2200 movs r2, #0 8000d40: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 8000d42: 4b14 ldr r3, [pc, #80] @ (8000d94 ) 8000d44: 2280 movs r2, #128 @ 0x80 8000d46: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8000d48: 4b12 ldr r3, [pc, #72] @ (8000d94 ) 8000d4a: 2200 movs r2, #0 8000d4c: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8000d4e: 4b11 ldr r3, [pc, #68] @ (8000d94 ) 8000d50: 2200 movs r2, #0 8000d52: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 8000d54: 4b0f ldr r3, [pc, #60] @ (8000d94 ) 8000d56: 2200 movs r2, #0 8000d58: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 8000d5a: 4b0e ldr r3, [pc, #56] @ (8000d94 ) 8000d5c: 2200 movs r2, #0 8000d5e: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 8000d60: 4b0c ldr r3, [pc, #48] @ (8000d94 ) 8000d62: 0018 movs r0, r3 8000d64: f001 ffd6 bl 8002d14 8000d68: 1e03 subs r3, r0, #0 8000d6a: d001 beq.n 8000d70 { Error_Handler(); 8000d6c: f7ff fd54 bl 8000818 } __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx); 8000d70: 687b ldr r3, [r7, #4] 8000d72: 4a08 ldr r2, [pc, #32] @ (8000d94 ) 8000d74: 67da str r2, [r3, #124] @ 0x7c 8000d76: 4b07 ldr r3, [pc, #28] @ (8000d94 ) 8000d78: 687a ldr r2, [r7, #4] 8000d7a: 629a str r2, [r3, #40] @ 0x28 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8000d7c: 46c0 nop @ (mov r8, r8) 8000d7e: 46bd mov sp, r7 8000d80: b00b add sp, #44 @ 0x2c 8000d82: bd90 pop {r4, r7, pc} 8000d84: 40004400 .word 0x40004400 8000d88: 40021000 .word 0x40021000 8000d8c: 200003a0 .word 0x200003a0 8000d90: 40020044 .word 0x40020044 8000d94: 200003fc .word 0x200003fc 8000d98: 40020058 .word 0x40020058 08000d9c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000d9c: b580 push {r7, lr} 8000d9e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000da0: 46c0 nop @ (mov r8, r8) 8000da2: e7fd b.n 8000da0 08000da4 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000da4: b580 push {r7, lr} 8000da6: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000da8: 46c0 nop @ (mov r8, r8) 8000daa: e7fd b.n 8000da8 08000dac : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000dac: b580 push {r7, lr} 8000dae: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 8000db0: 46c0 nop @ (mov r8, r8) 8000db2: 46bd mov sp, r7 8000db4: bd80 pop {r7, pc} 08000db6 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000db6: b580 push {r7, lr} 8000db8: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000dba: 46c0 nop @ (mov r8, r8) 8000dbc: 46bd mov sp, r7 8000dbe: bd80 pop {r7, pc} 08000dc0 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000dc0: b580 push {r7, lr} 8000dc2: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000dc4: f000 fd3e bl 8001844 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000dc8: 46c0 nop @ (mov r8, r8) 8000dca: 46bd mov sp, r7 8000dcc: bd80 pop {r7, pc} ... 08000dd0 : /** * @brief This function handles DMA1 channel 2 and channel 3 interrupts. */ void DMA1_Channel2_3_IRQHandler(void) { 8000dd0: b580 push {r7, lr} 8000dd2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */ /* USER CODE END DMA1_Channel2_3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8000dd4: 4b03 ldr r3, [pc, #12] @ (8000de4 ) 8000dd6: 0018 movs r0, r3 8000dd8: f002 f90e bl 8002ff8 /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */ /* USER CODE END DMA1_Channel2_3_IRQn 1 */ } 8000ddc: 46c0 nop @ (mov r8, r8) 8000dde: 46bd mov sp, r7 8000de0: bd80 pop {r7, pc} 8000de2: 46c0 nop @ (mov r8, r8) 8000de4: 20000218 .word 0x20000218 08000de8 : /** * @brief This function handles DMA1 channel 4, channel 5 and DMAMUX1 interrupts. */ void DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler(void) { 8000de8: b580 push {r7, lr} 8000dea: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Ch4_5_DMAMUX1_OVR_IRQn 0 */ /* USER CODE END DMA1_Ch4_5_DMAMUX1_OVR_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8000dec: 4b05 ldr r3, [pc, #20] @ (8000e04 ) 8000dee: 0018 movs r0, r3 8000df0: f002 f902 bl 8002ff8 HAL_DMA_IRQHandler(&hdma_usart2_tx); 8000df4: 4b04 ldr r3, [pc, #16] @ (8000e08 ) 8000df6: 0018 movs r0, r3 8000df8: f002 f8fe bl 8002ff8 /* USER CODE BEGIN DMA1_Ch4_5_DMAMUX1_OVR_IRQn 1 */ /* USER CODE END DMA1_Ch4_5_DMAMUX1_OVR_IRQn 1 */ } 8000dfc: 46c0 nop @ (mov r8, r8) 8000dfe: 46bd mov sp, r7 8000e00: bd80 pop {r7, pc} 8000e02: 46c0 nop @ (mov r8, r8) 8000e04: 200003a0 .word 0x200003a0 8000e08: 200003fc .word 0x200003fc 08000e0c : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { 8000e0c: b580 push {r7, lr} 8000e0e: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000e10: 46c0 nop @ (mov r8, r8) 8000e12: 46bd mov sp, r7 8000e14: bd80 pop {r7, pc} ... 08000e18 : RC_RC_BatterySensorsFrame Frame; RC_LinkStatistics LinkStatistics; unsigned int Channals[16]; int TICKS_TO_US (int x) { 8000e18: b580 push {r7, lr} 8000e1a: b082 sub sp, #8 8000e1c: af00 add r7, sp, #0 8000e1e: 6078 str r0, [r7, #4] return ((x - 992) * 5 / 8 + 1500); 8000e20: 687b ldr r3, [r7, #4] 8000e22: 4a08 ldr r2, [pc, #32] @ (8000e44 ) 8000e24: 189a adds r2, r3, r2 8000e26: 0013 movs r3, r2 8000e28: 009b lsls r3, r3, #2 8000e2a: 189b adds r3, r3, r2 8000e2c: 2b00 cmp r3, #0 8000e2e: da00 bge.n 8000e32 8000e30: 3307 adds r3, #7 8000e32: 10db asrs r3, r3, #3 8000e34: 4a04 ldr r2, [pc, #16] @ (8000e48 ) 8000e36: 4694 mov ip, r2 8000e38: 4463 add r3, ip } 8000e3a: 0018 movs r0, r3 8000e3c: 46bd mov sp, r7 8000e3e: b002 add sp, #8 8000e40: bd80 pop {r7, pc} 8000e42: 46c0 nop @ (mov r8, r8) 8000e44: fffffc20 .word 0xfffffc20 8000e48: 000005dc .word 0x000005dc 08000e4c : 0xD6, 0x03, 0xA9, 0x7C, 0x28, 0xFD, 0x57, 0x82, 0xFF, 0x2A, 0x80, 0x55, 0x01, 0xD4, 0x7E, 0xAB, 0x84, 0x51, 0xFB, 0x2E, 0x7A, 0xAF, 0x05, 0xD0, 0xAD, 0x78, 0xD2, 0x07, 0x53, 0x86, 0x2C, 0xF9}; uint8_t crc8(uint8_t * ptr, uint8_t len) { 8000e4c: b590 push {r4, r7, lr} 8000e4e: b085 sub sp, #20 8000e50: af00 add r7, sp, #0 8000e52: 6078 str r0, [r7, #4] 8000e54: 000a movs r2, r1 8000e56: 1cfb adds r3, r7, #3 8000e58: 701a strb r2, [r3, #0] uint8_t crc = 0; 8000e5a: 230f movs r3, #15 8000e5c: 18fb adds r3, r7, r3 8000e5e: 2200 movs r2, #0 8000e60: 701a strb r2, [r3, #0] for (uint8_t i=2; i<=len; i++) 8000e62: 230e movs r3, #14 8000e64: 18fb adds r3, r7, r3 8000e66: 2202 movs r2, #2 8000e68: 701a strb r2, [r3, #0] 8000e6a: e014 b.n 8000e96 crc = crc8tab[crc ^ ptr[i]]; 8000e6c: 200e movs r0, #14 8000e6e: 183b adds r3, r7, r0 8000e70: 781b ldrb r3, [r3, #0] 8000e72: 687a ldr r2, [r7, #4] 8000e74: 18d3 adds r3, r2, r3 8000e76: 781a ldrb r2, [r3, #0] 8000e78: 240f movs r4, #15 8000e7a: 193b adds r3, r7, r4 8000e7c: 781b ldrb r3, [r3, #0] 8000e7e: 4053 eors r3, r2 8000e80: b2db uxtb r3, r3 8000e82: 0019 movs r1, r3 8000e84: 193b adds r3, r7, r4 8000e86: 4a0b ldr r2, [pc, #44] @ (8000eb4 ) 8000e88: 5c52 ldrb r2, [r2, r1] 8000e8a: 701a strb r2, [r3, #0] for (uint8_t i=2; i<=len; i++) 8000e8c: 183b adds r3, r7, r0 8000e8e: 781a ldrb r2, [r3, #0] 8000e90: 183b adds r3, r7, r0 8000e92: 3201 adds r2, #1 8000e94: 701a strb r2, [r3, #0] 8000e96: 230e movs r3, #14 8000e98: 18fa adds r2, r7, r3 8000e9a: 1cfb adds r3, r7, #3 8000e9c: 7812 ldrb r2, [r2, #0] 8000e9e: 781b ldrb r3, [r3, #0] 8000ea0: 429a cmp r2, r3 8000ea2: d9e3 bls.n 8000e6c return crc; 8000ea4: 230f movs r3, #15 8000ea6: 18fb adds r3, r7, r3 8000ea8: 781b ldrb r3, [r3, #0] } 8000eaa: 0018 movs r0, r3 8000eac: 46bd mov sp, r7 8000eae: b005 add sp, #20 8000eb0: bd90 pop {r4, r7, pc} 8000eb2: 46c0 nop @ (mov r8, r8) 8000eb4: 20000004 .word 0x20000004 08000eb8 : void processLink_Statistics() { 8000eb8: b580 push {r7, lr} 8000eba: b082 sub sp, #8 8000ebc: af00 add r7, sp, #0 RC_LinkStatistics *ls = (RC_LinkStatistics *)&RxBuf[3]; 8000ebe: 4b18 ldr r3, [pc, #96] @ (8000f20 ) 8000ec0: 607b str r3, [r7, #4] LinkStatistics.up_rssi_ant1 = ls->up_rssi_ant1; 8000ec2: 687b ldr r3, [r7, #4] 8000ec4: 781a ldrb r2, [r3, #0] 8000ec6: 4b17 ldr r3, [pc, #92] @ (8000f24 ) 8000ec8: 701a strb r2, [r3, #0] LinkStatistics.up_rssi_ant2 = ls->up_rssi_ant2; 8000eca: 687b ldr r3, [r7, #4] 8000ecc: 785a ldrb r2, [r3, #1] 8000ece: 4b15 ldr r3, [pc, #84] @ (8000f24 ) 8000ed0: 705a strb r2, [r3, #1] LinkStatistics.up_link_quality = ls->up_link_quality; 8000ed2: 687b ldr r3, [r7, #4] 8000ed4: 789a ldrb r2, [r3, #2] 8000ed6: 4b13 ldr r3, [pc, #76] @ (8000f24 ) 8000ed8: 709a strb r2, [r3, #2] LinkStatistics.up_snr = ls->up_snr; 8000eda: 687b ldr r3, [r7, #4] 8000edc: 2203 movs r2, #3 8000ede: 569a ldrsb r2, [r3, r2] 8000ee0: 4b10 ldr r3, [pc, #64] @ (8000f24 ) 8000ee2: 70da strb r2, [r3, #3] LinkStatistics.active_antenna = ls->active_antenna; 8000ee4: 687b ldr r3, [r7, #4] 8000ee6: 791a ldrb r2, [r3, #4] 8000ee8: 4b0e ldr r3, [pc, #56] @ (8000f24 ) 8000eea: 711a strb r2, [r3, #4] LinkStatistics.rf_profile = ls->rf_profile; 8000eec: 687b ldr r3, [r7, #4] 8000eee: 795a ldrb r2, [r3, #5] 8000ef0: 4b0c ldr r3, [pc, #48] @ (8000f24 ) 8000ef2: 715a strb r2, [r3, #5] LinkStatistics.up_rf_power = ls->up_rf_power; 8000ef4: 687b ldr r3, [r7, #4] 8000ef6: 799a ldrb r2, [r3, #6] 8000ef8: 4b0a ldr r3, [pc, #40] @ (8000f24 ) 8000efa: 719a strb r2, [r3, #6] LinkStatistics.down_rssi = ls->down_rssi; 8000efc: 687b ldr r3, [r7, #4] 8000efe: 79da ldrb r2, [r3, #7] 8000f00: 4b08 ldr r3, [pc, #32] @ (8000f24 ) 8000f02: 71da strb r2, [r3, #7] LinkStatistics.down_link_quality = ls->down_link_quality; 8000f04: 687b ldr r3, [r7, #4] 8000f06: 7a1a ldrb r2, [r3, #8] 8000f08: 4b06 ldr r3, [pc, #24] @ (8000f24 ) 8000f0a: 721a strb r2, [r3, #8] LinkStatistics.down_snr = ls->down_snr; 8000f0c: 687b ldr r3, [r7, #4] 8000f0e: 2209 movs r2, #9 8000f10: 569a ldrsb r2, [r3, r2] 8000f12: 4b04 ldr r3, [pc, #16] @ (8000f24 ) 8000f14: 725a strb r2, [r3, #9] } 8000f16: 46c0 nop @ (mov r8, r8) 8000f18: 46bd mov sp, r7 8000f1a: b002 add sp, #8 8000f1c: bd80 pop {r7, pc} 8000f1e: 46c0 nop @ (mov r8, r8) 8000f20: 20000473 .word 0x20000473 8000f24: 200004c0 .word 0x200004c0 08000f28 : void processLink_RC_Channels() { 8000f28: b580 push {r7, lr} 8000f2a: b082 sub sp, #8 8000f2c: af00 add r7, sp, #0 RC_Channels *ch = (RC_Channels *)&RxBuf[3]; 8000f2e: 4b8d ldr r3, [pc, #564] @ (8001164 ) 8000f30: 607b str r3, [r7, #4] Channals[0] = TICKS_TO_US(ch->channel_01); 8000f32: 687b ldr r3, [r7, #4] 8000f34: 781a ldrb r2, [r3, #0] 8000f36: 785b ldrb r3, [r3, #1] 8000f38: 2107 movs r1, #7 8000f3a: 400b ands r3, r1 8000f3c: 021b lsls r3, r3, #8 8000f3e: 4313 orrs r3, r2 8000f40: b29b uxth r3, r3 8000f42: 0018 movs r0, r3 8000f44: f7ff ff68 bl 8000e18 8000f48: 0003 movs r3, r0 8000f4a: 001a movs r2, r3 8000f4c: 4b86 ldr r3, [pc, #536] @ (8001168 ) 8000f4e: 601a str r2, [r3, #0] Channals[1] = TICKS_TO_US(ch->channel_02); 8000f50: 687b ldr r3, [r7, #4] 8000f52: 785a ldrb r2, [r3, #1] 8000f54: 08d2 lsrs r2, r2, #3 8000f56: b2d2 uxtb r2, r2 8000f58: 789b ldrb r3, [r3, #2] 8000f5a: 213f movs r1, #63 @ 0x3f 8000f5c: 400b ands r3, r1 8000f5e: 015b lsls r3, r3, #5 8000f60: 4313 orrs r3, r2 8000f62: b29b uxth r3, r3 8000f64: 0018 movs r0, r3 8000f66: f7ff ff57 bl 8000e18 8000f6a: 0003 movs r3, r0 8000f6c: 001a movs r2, r3 8000f6e: 4b7e ldr r3, [pc, #504] @ (8001168 ) 8000f70: 605a str r2, [r3, #4] Channals[2] = TICKS_TO_US(ch->channel_03); 8000f72: 687b ldr r3, [r7, #4] 8000f74: 789a ldrb r2, [r3, #2] 8000f76: 0992 lsrs r2, r2, #6 8000f78: b2d2 uxtb r2, r2 8000f7a: 78d9 ldrb r1, [r3, #3] 8000f7c: 0089 lsls r1, r1, #2 8000f7e: 430a orrs r2, r1 8000f80: 791b ldrb r3, [r3, #4] 8000f82: 2101 movs r1, #1 8000f84: 400b ands r3, r1 8000f86: 029b lsls r3, r3, #10 8000f88: 4313 orrs r3, r2 8000f8a: b29b uxth r3, r3 8000f8c: 0018 movs r0, r3 8000f8e: f7ff ff43 bl 8000e18 8000f92: 0003 movs r3, r0 8000f94: 001a movs r2, r3 8000f96: 4b74 ldr r3, [pc, #464] @ (8001168 ) 8000f98: 609a str r2, [r3, #8] Channals[3] = TICKS_TO_US(ch->channel_04); 8000f9a: 687b ldr r3, [r7, #4] 8000f9c: 791a ldrb r2, [r3, #4] 8000f9e: 0852 lsrs r2, r2, #1 8000fa0: b2d2 uxtb r2, r2 8000fa2: 795b ldrb r3, [r3, #5] 8000fa4: 210f movs r1, #15 8000fa6: 400b ands r3, r1 8000fa8: 01db lsls r3, r3, #7 8000faa: 4313 orrs r3, r2 8000fac: b29b uxth r3, r3 8000fae: 0018 movs r0, r3 8000fb0: f7ff ff32 bl 8000e18 8000fb4: 0003 movs r3, r0 8000fb6: 001a movs r2, r3 8000fb8: 4b6b ldr r3, [pc, #428] @ (8001168 ) 8000fba: 60da str r2, [r3, #12] Channals[4] = TICKS_TO_US(ch->channel_05); 8000fbc: 687b ldr r3, [r7, #4] 8000fbe: 795a ldrb r2, [r3, #5] 8000fc0: 0912 lsrs r2, r2, #4 8000fc2: b2d2 uxtb r2, r2 8000fc4: 799b ldrb r3, [r3, #6] 8000fc6: 217f movs r1, #127 @ 0x7f 8000fc8: 400b ands r3, r1 8000fca: 011b lsls r3, r3, #4 8000fcc: 4313 orrs r3, r2 8000fce: b29b uxth r3, r3 8000fd0: 0018 movs r0, r3 8000fd2: f7ff ff21 bl 8000e18 8000fd6: 0003 movs r3, r0 8000fd8: 001a movs r2, r3 8000fda: 4b63 ldr r3, [pc, #396] @ (8001168 ) 8000fdc: 611a str r2, [r3, #16] Channals[5] = TICKS_TO_US(ch->channel_06); 8000fde: 687b ldr r3, [r7, #4] 8000fe0: 799a ldrb r2, [r3, #6] 8000fe2: 09d2 lsrs r2, r2, #7 8000fe4: b2d2 uxtb r2, r2 8000fe6: 79d9 ldrb r1, [r3, #7] 8000fe8: 0049 lsls r1, r1, #1 8000fea: 430a orrs r2, r1 8000fec: 7a1b ldrb r3, [r3, #8] 8000fee: 2103 movs r1, #3 8000ff0: 400b ands r3, r1 8000ff2: 025b lsls r3, r3, #9 8000ff4: 4313 orrs r3, r2 8000ff6: b29b uxth r3, r3 8000ff8: 0018 movs r0, r3 8000ffa: f7ff ff0d bl 8000e18 8000ffe: 0003 movs r3, r0 8001000: 001a movs r2, r3 8001002: 4b59 ldr r3, [pc, #356] @ (8001168 ) 8001004: 615a str r2, [r3, #20] Channals[6] = TICKS_TO_US(ch->channel_07); 8001006: 687b ldr r3, [r7, #4] 8001008: 7a1a ldrb r2, [r3, #8] 800100a: 0892 lsrs r2, r2, #2 800100c: b2d2 uxtb r2, r2 800100e: 7a5b ldrb r3, [r3, #9] 8001010: 211f movs r1, #31 8001012: 400b ands r3, r1 8001014: 019b lsls r3, r3, #6 8001016: 4313 orrs r3, r2 8001018: b29b uxth r3, r3 800101a: 0018 movs r0, r3 800101c: f7ff fefc bl 8000e18 8001020: 0003 movs r3, r0 8001022: 001a movs r2, r3 8001024: 4b50 ldr r3, [pc, #320] @ (8001168 ) 8001026: 619a str r2, [r3, #24] Channals[7] = TICKS_TO_US(ch->channel_08); 8001028: 687b ldr r3, [r7, #4] 800102a: 7a5a ldrb r2, [r3, #9] 800102c: 0952 lsrs r2, r2, #5 800102e: b2d2 uxtb r2, r2 8001030: 7a9b ldrb r3, [r3, #10] 8001032: 00db lsls r3, r3, #3 8001034: 4313 orrs r3, r2 8001036: b29b uxth r3, r3 8001038: 0018 movs r0, r3 800103a: f7ff feed bl 8000e18 800103e: 0003 movs r3, r0 8001040: 001a movs r2, r3 8001042: 4b49 ldr r3, [pc, #292] @ (8001168 ) 8001044: 61da str r2, [r3, #28] Channals[8] = TICKS_TO_US(ch->channel_09); 8001046: 687b ldr r3, [r7, #4] 8001048: 7ada ldrb r2, [r3, #11] 800104a: 7b1b ldrb r3, [r3, #12] 800104c: 2107 movs r1, #7 800104e: 400b ands r3, r1 8001050: 021b lsls r3, r3, #8 8001052: 4313 orrs r3, r2 8001054: b29b uxth r3, r3 8001056: 0018 movs r0, r3 8001058: f7ff fede bl 8000e18 800105c: 0003 movs r3, r0 800105e: 001a movs r2, r3 8001060: 4b41 ldr r3, [pc, #260] @ (8001168 ) 8001062: 621a str r2, [r3, #32] Channals[9] = TICKS_TO_US(ch->channel_10); 8001064: 687b ldr r3, [r7, #4] 8001066: 7b1a ldrb r2, [r3, #12] 8001068: 08d2 lsrs r2, r2, #3 800106a: b2d2 uxtb r2, r2 800106c: 7b5b ldrb r3, [r3, #13] 800106e: 213f movs r1, #63 @ 0x3f 8001070: 400b ands r3, r1 8001072: 015b lsls r3, r3, #5 8001074: 4313 orrs r3, r2 8001076: b29b uxth r3, r3 8001078: 0018 movs r0, r3 800107a: f7ff fecd bl 8000e18 800107e: 0003 movs r3, r0 8001080: 001a movs r2, r3 8001082: 4b39 ldr r3, [pc, #228] @ (8001168 ) 8001084: 625a str r2, [r3, #36] @ 0x24 Channals[10] = TICKS_TO_US(ch->channel_11); 8001086: 687b ldr r3, [r7, #4] 8001088: 7b5a ldrb r2, [r3, #13] 800108a: 0992 lsrs r2, r2, #6 800108c: b2d2 uxtb r2, r2 800108e: 7b99 ldrb r1, [r3, #14] 8001090: 0089 lsls r1, r1, #2 8001092: 430a orrs r2, r1 8001094: 7bdb ldrb r3, [r3, #15] 8001096: 2101 movs r1, #1 8001098: 400b ands r3, r1 800109a: 029b lsls r3, r3, #10 800109c: 4313 orrs r3, r2 800109e: b29b uxth r3, r3 80010a0: 0018 movs r0, r3 80010a2: f7ff feb9 bl 8000e18 80010a6: 0003 movs r3, r0 80010a8: 001a movs r2, r3 80010aa: 4b2f ldr r3, [pc, #188] @ (8001168 ) 80010ac: 629a str r2, [r3, #40] @ 0x28 Channals[11] = TICKS_TO_US(ch->channel_12); 80010ae: 687b ldr r3, [r7, #4] 80010b0: 7bda ldrb r2, [r3, #15] 80010b2: 0852 lsrs r2, r2, #1 80010b4: b2d2 uxtb r2, r2 80010b6: 7c1b ldrb r3, [r3, #16] 80010b8: 210f movs r1, #15 80010ba: 400b ands r3, r1 80010bc: 01db lsls r3, r3, #7 80010be: 4313 orrs r3, r2 80010c0: b29b uxth r3, r3 80010c2: 0018 movs r0, r3 80010c4: f7ff fea8 bl 8000e18 80010c8: 0003 movs r3, r0 80010ca: 001a movs r2, r3 80010cc: 4b26 ldr r3, [pc, #152] @ (8001168 ) 80010ce: 62da str r2, [r3, #44] @ 0x2c Channals[12] = TICKS_TO_US(ch->channel_13); 80010d0: 687b ldr r3, [r7, #4] 80010d2: 7c1a ldrb r2, [r3, #16] 80010d4: 0912 lsrs r2, r2, #4 80010d6: b2d2 uxtb r2, r2 80010d8: 7c5b ldrb r3, [r3, #17] 80010da: 217f movs r1, #127 @ 0x7f 80010dc: 400b ands r3, r1 80010de: 011b lsls r3, r3, #4 80010e0: 4313 orrs r3, r2 80010e2: b29b uxth r3, r3 80010e4: 0018 movs r0, r3 80010e6: f7ff fe97 bl 8000e18 80010ea: 0003 movs r3, r0 80010ec: 001a movs r2, r3 80010ee: 4b1e ldr r3, [pc, #120] @ (8001168 ) 80010f0: 631a str r2, [r3, #48] @ 0x30 Channals[13] = TICKS_TO_US(ch->channel_14); 80010f2: 687b ldr r3, [r7, #4] 80010f4: 7c5a ldrb r2, [r3, #17] 80010f6: 09d2 lsrs r2, r2, #7 80010f8: b2d2 uxtb r2, r2 80010fa: 7c99 ldrb r1, [r3, #18] 80010fc: 0049 lsls r1, r1, #1 80010fe: 430a orrs r2, r1 8001100: 7cdb ldrb r3, [r3, #19] 8001102: 2103 movs r1, #3 8001104: 400b ands r3, r1 8001106: 025b lsls r3, r3, #9 8001108: 4313 orrs r3, r2 800110a: b29b uxth r3, r3 800110c: 0018 movs r0, r3 800110e: f7ff fe83 bl 8000e18 8001112: 0003 movs r3, r0 8001114: 001a movs r2, r3 8001116: 4b14 ldr r3, [pc, #80] @ (8001168 ) 8001118: 635a str r2, [r3, #52] @ 0x34 Channals[14] = TICKS_TO_US(ch->channel_15); 800111a: 687b ldr r3, [r7, #4] 800111c: 7cda ldrb r2, [r3, #19] 800111e: 0892 lsrs r2, r2, #2 8001120: b2d2 uxtb r2, r2 8001122: 7d1b ldrb r3, [r3, #20] 8001124: 211f movs r1, #31 8001126: 400b ands r3, r1 8001128: 019b lsls r3, r3, #6 800112a: 4313 orrs r3, r2 800112c: b29b uxth r3, r3 800112e: 0018 movs r0, r3 8001130: f7ff fe72 bl 8000e18 8001134: 0003 movs r3, r0 8001136: 001a movs r2, r3 8001138: 4b0b ldr r3, [pc, #44] @ (8001168 ) 800113a: 639a str r2, [r3, #56] @ 0x38 Channals[15] = TICKS_TO_US(ch->channel_16); 800113c: 687b ldr r3, [r7, #4] 800113e: 7d1a ldrb r2, [r3, #20] 8001140: 0952 lsrs r2, r2, #5 8001142: b2d2 uxtb r2, r2 8001144: 7d5b ldrb r3, [r3, #21] 8001146: 00db lsls r3, r3, #3 8001148: 4313 orrs r3, r2 800114a: b29b uxth r3, r3 800114c: 0018 movs r0, r3 800114e: f7ff fe63 bl 8000e18 8001152: 0003 movs r3, r0 8001154: 001a movs r2, r3 8001156: 4b04 ldr r3, [pc, #16] @ (8001168 ) 8001158: 63da str r2, [r3, #60] @ 0x3c } 800115a: 46c0 nop @ (mov r8, r8) 800115c: 46bd mov sp, r7 800115e: b002 add sp, #8 8001160: bd80 pop {r7, pc} 8001162: 46c0 nop @ (mov r8, r8) 8001164: 20000473 .word 0x20000473 8001168: 200004cc .word 0x200004cc 0800116c : void checkValidPakage() { 800116c: b590 push {r4, r7, lr} 800116e: b083 sub sp, #12 8001170: af00 add r7, sp, #0 uint8_t crc; uint8_t crc_frame; if (RxBufPos > 5) { 8001172: 4b1c ldr r3, [pc, #112] @ (80011e4 ) 8001174: 781b ldrb r3, [r3, #0] 8001176: 2b05 cmp r3, #5 8001178: d930 bls.n 80011dc if (RxBuf[0] == SYNC_BYTE) { 800117a: 4b1b ldr r3, [pc, #108] @ (80011e8 ) 800117c: 781b ldrb r3, [r3, #0] 800117e: 2bc8 cmp r3, #200 @ 0xc8 8001180: d12c bne.n 80011dc if (RxBuf[FRAME_LENGTH_BYTE]+2 == RxBufPos) { 8001182: 4b19 ldr r3, [pc, #100] @ (80011e8 ) 8001184: 785b ldrb r3, [r3, #1] 8001186: 3302 adds r3, #2 8001188: 4a16 ldr r2, [pc, #88] @ (80011e4 ) 800118a: 7812 ldrb r2, [r2, #0] 800118c: 4293 cmp r3, r2 800118e: d125 bne.n 80011dc crc = crc8((uint8_t * )&RxBuf, RxBuf[FRAME_LENGTH_BYTE]); 8001190: 4b15 ldr r3, [pc, #84] @ (80011e8 ) 8001192: 785a ldrb r2, [r3, #1] 8001194: 1dfc adds r4, r7, #7 8001196: 4b14 ldr r3, [pc, #80] @ (80011e8 ) 8001198: 0011 movs r1, r2 800119a: 0018 movs r0, r3 800119c: f7ff fe56 bl 8000e4c 80011a0: 0003 movs r3, r0 80011a2: 7023 strb r3, [r4, #0] crc_frame = RxBuf[RxBufPos-1]; 80011a4: 4b0f ldr r3, [pc, #60] @ (80011e4 ) 80011a6: 781b ldrb r3, [r3, #0] 80011a8: 1e5a subs r2, r3, #1 80011aa: 1dbb adds r3, r7, #6 80011ac: 490e ldr r1, [pc, #56] @ (80011e8 ) 80011ae: 5c8a ldrb r2, [r1, r2] 80011b0: 701a strb r2, [r3, #0] if (crc == crc_frame) { 80011b2: 1dfa adds r2, r7, #7 80011b4: 1dbb adds r3, r7, #6 80011b6: 7812 ldrb r2, [r2, #0] 80011b8: 781b ldrb r3, [r3, #0] 80011ba: 429a cmp r2, r3 80011bc: d10e bne.n 80011dc // Process Pakage if (RxBuf[FRAME_TYPE_BYTE] == FRAME_TYPE_Link_Statistics) { 80011be: 4b0a ldr r3, [pc, #40] @ (80011e8 ) 80011c0: 789b ldrb r3, [r3, #2] 80011c2: 2b14 cmp r3, #20 80011c4: d101 bne.n 80011ca processLink_Statistics(); 80011c6: f7ff fe77 bl 8000eb8 } if (RxBuf[FRAME_TYPE_BYTE] == FRAME_TYPE_RC_Channels) { 80011ca: 4b07 ldr r3, [pc, #28] @ (80011e8 ) 80011cc: 789b ldrb r3, [r3, #2] 80011ce: 2b16 cmp r3, #22 80011d0: d101 bne.n 80011d6 processLink_RC_Channels(); 80011d2: f7ff fea9 bl 8000f28 } // Reset Buffer RxBufPos = 0; 80011d6: 4b03 ldr r3, [pc, #12] @ (80011e4 ) 80011d8: 2200 movs r2, #0 80011da: 701a strb r2, [r3, #0] } } } else { //ErrorPakageCounter++; } } 80011dc: 46c0 nop @ (mov r8, r8) 80011de: 46bd mov sp, r7 80011e0: b003 add sp, #12 80011e2: bd90 pop {r4, r7, pc} 80011e4: 200004b0 .word 0x200004b0 80011e8: 20000470 .word 0x20000470 080011ec : uint8_t UART_Counter = 0; void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 80011ec: b580 push {r7, lr} 80011ee: b082 sub sp, #8 80011f0: af00 add r7, sp, #0 80011f2: 6078 str r0, [r7, #4] 80011f4: 000a movs r2, r1 80011f6: 1cbb adds r3, r7, #2 80011f8: 801a strh r2, [r3, #0] if (huart->Instance == USART2) 80011fa: 687b ldr r3, [r7, #4] 80011fc: 681b ldr r3, [r3, #0] 80011fe: 4a14 ldr r2, [pc, #80] @ (8001250 ) 8001200: 4293 cmp r3, r2 8001202: d122 bne.n 800124a { if ((RxBufPos == 0) && (RxChar[0] != SYNC_BYTE )) { 8001204: 4b13 ldr r3, [pc, #76] @ (8001254 ) 8001206: 781b ldrb r3, [r3, #0] 8001208: 2b00 cmp r3, #0 800120a: d103 bne.n 8001214 800120c: 4b12 ldr r3, [pc, #72] @ (8001258 ) 800120e: 781b ldrb r3, [r3, #0] 8001210: 2bc8 cmp r3, #200 @ 0xc8 8001212: d119 bne.n 8001248 return; } RxBuf[RxBufPos] = RxChar[0]; 8001214: 4b0f ldr r3, [pc, #60] @ (8001254 ) 8001216: 781b ldrb r3, [r3, #0] 8001218: 001a movs r2, r3 800121a: 4b0f ldr r3, [pc, #60] @ (8001258 ) 800121c: 7819 ldrb r1, [r3, #0] 800121e: 4b0f ldr r3, [pc, #60] @ (800125c ) 8001220: 5499 strb r1, [r3, r2] RxBufPos++; 8001222: 4b0c ldr r3, [pc, #48] @ (8001254 ) 8001224: 781b ldrb r3, [r3, #0] 8001226: 3301 adds r3, #1 8001228: b2da uxtb r2, r3 800122a: 4b0a ldr r3, [pc, #40] @ (8001254 ) 800122c: 701a strb r2, [r3, #0] if (RxBufPos > BUFFER_LENGTH-1) { 800122e: 4b09 ldr r3, [pc, #36] @ (8001254 ) 8001230: 781b ldrb r3, [r3, #0] 8001232: 2b3f cmp r3, #63 @ 0x3f 8001234: d902 bls.n 800123c RxBufPos = 0; 8001236: 4b07 ldr r3, [pc, #28] @ (8001254 ) 8001238: 2200 movs r2, #0 800123a: 701a strb r2, [r3, #0] } checkValidPakage(); 800123c: f7ff ff96 bl 800116c UART_Counter = 0; 8001240: 4b07 ldr r3, [pc, #28] @ (8001260 ) 8001242: 2200 movs r2, #0 8001244: 701a strb r2, [r3, #0] 8001246: e000 b.n 800124a return; 8001248: 46c0 nop @ (mov r8, r8) } } 800124a: 46bd mov sp, r7 800124c: b002 add sp, #8 800124e: bd80 pop {r7, pc} 8001250: 40004400 .word 0x40004400 8001254: 200004b0 .word 0x200004b0 8001258: 2000046c .word 0x2000046c 800125c: 20000470 .word 0x20000470 8001260: 2000050c .word 0x2000050c 08001264 : void Uart_StartReceive() { 8001264: b580 push {r7, lr} 8001266: af00 add r7, sp, #0 RxBufPos = 0; 8001268: 4b0b ldr r3, [pc, #44] @ (8001298 ) 800126a: 2200 movs r2, #0 800126c: 701a strb r2, [r3, #0] HAL_UART_DMAStop(&huart2); 800126e: 4b0b ldr r3, [pc, #44] @ (800129c ) 8001270: 0018 movs r0, r3 8001272: f003 ffb5 bl 80051e0 HAL_UARTEx_ReceiveToIdle_DMA(&huart2, RxChar, 1); 8001276: 490a ldr r1, [pc, #40] @ (80012a0 ) 8001278: 4b08 ldr r3, [pc, #32] @ (800129c ) 800127a: 2201 movs r2, #1 800127c: 0018 movs r0, r3 800127e: f004 fe47 bl 8005f10 __HAL_DMA_DISABLE_IT(&hdma_usart2_rx, DMA_IT_HT); 8001282: 4b08 ldr r3, [pc, #32] @ (80012a4 ) 8001284: 681b ldr r3, [r3, #0] 8001286: 681a ldr r2, [r3, #0] 8001288: 4b06 ldr r3, [pc, #24] @ (80012a4 ) 800128a: 681b ldr r3, [r3, #0] 800128c: 2104 movs r1, #4 800128e: 438a bics r2, r1 8001290: 601a str r2, [r3, #0] } 8001292: 46c0 nop @ (mov r8, r8) 8001294: 46bd mov sp, r7 8001296: bd80 pop {r7, pc} 8001298: 200004b0 .word 0x200004b0 800129c: 2000030c .word 0x2000030c 80012a0: 2000046c .word 0x2000046c 80012a4: 200003a0 .word 0x200003a0 080012a8 : void Uart_StartSendFrame() { 80012a8: b580 push {r7, lr} 80012aa: af00 add r7, sp, #0 //HAL_UART_AbortTransmit(&huart2); huart2.gState = HAL_UART_STATE_READY; 80012ac: 4b06 ldr r3, [pc, #24] @ (80012c8 ) 80012ae: 2288 movs r2, #136 @ 0x88 80012b0: 2120 movs r1, #32 80012b2: 5099 str r1, [r3, r2] HAL_UART_Transmit_DMA(&huart2, (uint8_t *) &Frame, 12); 80012b4: 4905 ldr r1, [pc, #20] @ (80012cc ) 80012b6: 4b04 ldr r3, [pc, #16] @ (80012c8 ) 80012b8: 220c movs r2, #12 80012ba: 0018 movs r0, r3 80012bc: f003 fefe bl 80050bc } 80012c0: 46c0 nop @ (mov r8, r8) 80012c2: 46bd mov sp, r7 80012c4: bd80 pop {r7, pc} 80012c6: 46c0 nop @ (mov r8, r8) 80012c8: 2000030c .word 0x2000030c 80012cc: 200004b4 .word 0x200004b4 080012d0 : void Make_Frame() { 80012d0: b590 push {r4, r7, lr} 80012d2: b083 sub sp, #12 80012d4: af00 add r7, sp, #0 uint8_t crc; uint16_t voltage; voltage = ADC_GetVoltage(); 80012d6: 1dbc adds r4, r7, #6 80012d8: f7fe ffce bl 8000278 80012dc: 0003 movs r3, r0 80012de: 8023 strh r3, [r4, #0] voltage = (voltage << 8) | (voltage >> 8); 80012e0: 1dbb adds r3, r7, #6 80012e2: 881b ldrh r3, [r3, #0] 80012e4: 021b lsls r3, r3, #8 80012e6: b21a sxth r2, r3 80012e8: 1dbb adds r3, r7, #6 80012ea: 881b ldrh r3, [r3, #0] 80012ec: 0a1b lsrs r3, r3, #8 80012ee: b29b uxth r3, r3 80012f0: b21b sxth r3, r3 80012f2: 4313 orrs r3, r2 80012f4: b21a sxth r2, r3 80012f6: 1dbb adds r3, r7, #6 80012f8: 801a strh r2, [r3, #0] Frame.sync_byte = SYNC_BYTE; 80012fa: 4b23 ldr r3, [pc, #140] @ (8001388 ) 80012fc: 22c8 movs r2, #200 @ 0xc8 80012fe: 701a strb r2, [r3, #0] Frame.length = 10; 8001300: 4b21 ldr r3, [pc, #132] @ (8001388 ) 8001302: 220a movs r2, #10 8001304: 705a strb r2, [r3, #1] Frame.type = FRAME_TYPE_Battery_Sensor; 8001306: 4b20 ldr r3, [pc, #128] @ (8001388 ) 8001308: 2208 movs r2, #8 800130a: 709a strb r2, [r3, #2] Frame.voltage = voltage; 800130c: 4b1e ldr r3, [pc, #120] @ (8001388 ) 800130e: 1dba adds r2, r7, #6 8001310: 3303 adds r3, #3 8001312: 7814 ldrb r4, [r2, #0] 8001314: 7819 ldrb r1, [r3, #0] 8001316: 2000 movs r0, #0 8001318: 4001 ands r1, r0 800131a: 1c08 adds r0, r1, #0 800131c: 1c21 adds r1, r4, #0 800131e: 4301 orrs r1, r0 8001320: 7019 strb r1, [r3, #0] 8001322: 7850 ldrb r0, [r2, #1] 8001324: 785a ldrb r2, [r3, #1] 8001326: 2100 movs r1, #0 8001328: 400a ands r2, r1 800132a: 1c11 adds r1, r2, #0 800132c: 1c02 adds r2, r0, #0 800132e: 430a orrs r2, r1 8001330: 705a strb r2, [r3, #1] Frame.current = 0; 8001332: 4b15 ldr r3, [pc, #84] @ (8001388 ) 8001334: 3303 adds r3, #3 8001336: 789a ldrb r2, [r3, #2] 8001338: 2100 movs r1, #0 800133a: 400a ands r2, r1 800133c: 709a strb r2, [r3, #2] 800133e: 78da ldrb r2, [r3, #3] 8001340: 2100 movs r1, #0 8001342: 400a ands r2, r1 8001344: 70da strb r2, [r3, #3] Frame.capacity = 0; 8001346: 4b10 ldr r3, [pc, #64] @ (8001388 ) 8001348: 3303 adds r3, #3 800134a: 791a ldrb r2, [r3, #4] 800134c: 2100 movs r1, #0 800134e: 400a ands r2, r1 8001350: 711a strb r2, [r3, #4] 8001352: 795a ldrb r2, [r3, #5] 8001354: 2100 movs r1, #0 8001356: 400a ands r2, r1 8001358: 715a strb r2, [r3, #5] 800135a: 799a ldrb r2, [r3, #6] 800135c: 2100 movs r1, #0 800135e: 400a ands r2, r1 8001360: 719a strb r2, [r3, #6] Frame.remaining = 0; 8001362: 4b09 ldr r3, [pc, #36] @ (8001388 ) 8001364: 2200 movs r2, #0 8001366: 729a strb r2, [r3, #10] crc = crc8((uint8_t * )&Frame, 10); 8001368: 1d7c adds r4, r7, #5 800136a: 4b07 ldr r3, [pc, #28] @ (8001388 ) 800136c: 210a movs r1, #10 800136e: 0018 movs r0, r3 8001370: f7ff fd6c bl 8000e4c 8001374: 0003 movs r3, r0 8001376: 7023 strb r3, [r4, #0] Frame.crc = crc; 8001378: 4b03 ldr r3, [pc, #12] @ (8001388 ) 800137a: 1d7a adds r2, r7, #5 800137c: 7812 ldrb r2, [r2, #0] 800137e: 72da strb r2, [r3, #11] } 8001380: 46c0 nop @ (mov r8, r8) 8001382: 46bd mov sp, r7 8001384: b003 add sp, #12 8001386: bd90 pop {r4, r7, pc} 8001388: 200004b4 .word 0x200004b4 0800138c : unsigned int Uart_GetChannel(uint8_t ch) { 800138c: b580 push {r7, lr} 800138e: b082 sub sp, #8 8001390: af00 add r7, sp, #0 8001392: 0002 movs r2, r0 8001394: 1dfb adds r3, r7, #7 8001396: 701a strb r2, [r3, #0] return Channals[ch]; 8001398: 1dfb adds r3, r7, #7 800139a: 781a ldrb r2, [r3, #0] 800139c: 4b03 ldr r3, [pc, #12] @ (80013ac ) 800139e: 0092 lsls r2, r2, #2 80013a0: 58d3 ldr r3, [r2, r3] } 80013a2: 0018 movs r0, r3 80013a4: 46bd mov sp, r7 80013a6: b002 add sp, #8 80013a8: bd80 pop {r7, pc} 80013aa: 46c0 nop @ (mov r8, r8) 80013ac: 200004cc .word 0x200004cc 080013b0 : void Uart_IncCounter(void) { 80013b0: b580 push {r7, lr} 80013b2: af00 add r7, sp, #0 if (UART_Counter < 100) { 80013b4: 4b06 ldr r3, [pc, #24] @ (80013d0 ) 80013b6: 781b ldrb r3, [r3, #0] 80013b8: 2b63 cmp r3, #99 @ 0x63 80013ba: d805 bhi.n 80013c8 UART_Counter++; 80013bc: 4b04 ldr r3, [pc, #16] @ (80013d0 ) 80013be: 781b ldrb r3, [r3, #0] 80013c0: 3301 adds r3, #1 80013c2: b2da uxtb r2, r3 80013c4: 4b02 ldr r3, [pc, #8] @ (80013d0 ) 80013c6: 701a strb r2, [r3, #0] } } 80013c8: 46c0 nop @ (mov r8, r8) 80013ca: 46bd mov sp, r7 80013cc: bd80 pop {r7, pc} 80013ce: 46c0 nop @ (mov r8, r8) 80013d0: 2000050c .word 0x2000050c 080013d4 : uint8_t Uart_GetCounter(void) { 80013d4: b580 push {r7, lr} 80013d6: af00 add r7, sp, #0 return UART_Counter; 80013d8: 4b02 ldr r3, [pc, #8] @ (80013e4 ) 80013da: 781b ldrb r3, [r3, #0] } 80013dc: 0018 movs r0, r3 80013de: 46bd mov sp, r7 80013e0: bd80 pop {r7, pc} 80013e2: 46c0 nop @ (mov r8, r8) 80013e4: 2000050c .word 0x2000050c 080013e8 : extern SettingsStruct Settings; extern RC_LinkStatistics LinkStatistics; uint8_t RC_LinkUpAtLeastOnce = 0; void USER_Init(void) { 80013e8: b580 push {r7, lr} 80013ea: b082 sub sp, #8 80013ec: af00 add r7, sp, #0 unsigned int ChannelValue; unsigned int ch; SettingsInit(); 80013ee: f7ff fa19 bl 8000824 for(ch=0; ch<5; ch++) { 80013f2: 2300 movs r3, #0 80013f4: 607b str r3, [r7, #4] 80013f6: e01b b.n 8001430 ChannelValue = Settings.start[ch]; 80013f8: 4b33 ldr r3, [pc, #204] @ (80014c8 ) 80013fa: 687a ldr r2, [r7, #4] 80013fc: 0052 lsls r2, r2, #1 80013fe: 5ad3 ldrh r3, [r2, r3] 8001400: 603b str r3, [r7, #0] if (ChannelValue > 0) { 8001402: 683b ldr r3, [r7, #0] 8001404: 2b00 cmp r3, #0 8001406: d008 beq.n 800141a USER_SetPWM(ch, ChannelValue); 8001408: 687b ldr r3, [r7, #4] 800140a: b2db uxtb r3, r3 800140c: 683a ldr r2, [r7, #0] 800140e: b292 uxth r2, r2 8001410: 0011 movs r1, r2 8001412: 0018 movs r0, r3 8001414: f000 f862 bl 80014dc 8001418: e007 b.n 800142a } else { USER_SetPWM(ch, 1000); 800141a: 687b ldr r3, [r7, #4] 800141c: b2db uxtb r3, r3 800141e: 22fa movs r2, #250 @ 0xfa 8001420: 0092 lsls r2, r2, #2 8001422: 0011 movs r1, r2 8001424: 0018 movs r0, r3 8001426: f000 f859 bl 80014dc for(ch=0; ch<5; ch++) { 800142a: 687b ldr r3, [r7, #4] 800142c: 3301 adds r3, #1 800142e: 607b str r3, [r7, #4] 8001430: 687b ldr r3, [r7, #4] 8001432: 2b04 cmp r3, #4 8001434: d9e0 bls.n 80013f8 } } TIM3->CCER |= (uint32_t)(TIM_CCx_ENABLE << (TIM_CHANNEL_1 & 0x1FU)); // PWM1 8001436: 4b25 ldr r3, [pc, #148] @ (80014cc ) 8001438: 6a1a ldr r2, [r3, #32] 800143a: 4b24 ldr r3, [pc, #144] @ (80014cc ) 800143c: 2101 movs r1, #1 800143e: 430a orrs r2, r1 8001440: 621a str r2, [r3, #32] TIM3->CCER |= (uint32_t)(TIM_CCx_ENABLE << (TIM_CHANNEL_2 & 0x1FU)); // PWM2 8001442: 4b22 ldr r3, [pc, #136] @ (80014cc ) 8001444: 6a1a ldr r2, [r3, #32] 8001446: 4b21 ldr r3, [pc, #132] @ (80014cc ) 8001448: 2110 movs r1, #16 800144a: 430a orrs r2, r1 800144c: 621a str r2, [r3, #32] TIM1->CCER |= (uint32_t)(TIM_CCx_ENABLE << (TIM_CHANNEL_1 & 0x1FU)); // PWM3 800144e: 4b20 ldr r3, [pc, #128] @ (80014d0 ) 8001450: 6a1a ldr r2, [r3, #32] 8001452: 4b1f ldr r3, [pc, #124] @ (80014d0 ) 8001454: 2101 movs r1, #1 8001456: 430a orrs r2, r1 8001458: 621a str r2, [r3, #32] TIM1->CCER |= (uint32_t)(TIM_CCx_ENABLE << (TIM_CHANNEL_4 & 0x1FU)); // PWM4 800145a: 4b1d ldr r3, [pc, #116] @ (80014d0 ) 800145c: 6a1a ldr r2, [r3, #32] 800145e: 4b1c ldr r3, [pc, #112] @ (80014d0 ) 8001460: 2180 movs r1, #128 @ 0x80 8001462: 0149 lsls r1, r1, #5 8001464: 430a orrs r2, r1 8001466: 621a str r2, [r3, #32] TIM1->CCER |= (uint32_t)(TIM_CCx_ENABLE << (TIM_CHANNEL_2 & 0x1FU)); // PWM5 8001468: 4b19 ldr r3, [pc, #100] @ (80014d0 ) 800146a: 6a1a ldr r2, [r3, #32] 800146c: 4b18 ldr r3, [pc, #96] @ (80014d0 ) 800146e: 2110 movs r1, #16 8001470: 430a orrs r2, r1 8001472: 621a str r2, [r3, #32] __HAL_TIM_MOE_ENABLE(&htim1); 8001474: 4b17 ldr r3, [pc, #92] @ (80014d4 ) 8001476: 681b ldr r3, [r3, #0] 8001478: 6c5a ldr r2, [r3, #68] @ 0x44 800147a: 4b16 ldr r3, [pc, #88] @ (80014d4 ) 800147c: 681b ldr r3, [r3, #0] 800147e: 2180 movs r1, #128 @ 0x80 8001480: 0209 lsls r1, r1, #8 8001482: 430a orrs r2, r1 8001484: 645a str r2, [r3, #68] @ 0x44 __HAL_TIM_ENABLE(&htim1); 8001486: 4b13 ldr r3, [pc, #76] @ (80014d4 ) 8001488: 681b ldr r3, [r3, #0] 800148a: 681a ldr r2, [r3, #0] 800148c: 4b11 ldr r3, [pc, #68] @ (80014d4 ) 800148e: 681b ldr r3, [r3, #0] 8001490: 2101 movs r1, #1 8001492: 430a orrs r2, r1 8001494: 601a str r2, [r3, #0] __HAL_TIM_MOE_ENABLE(&htim3); 8001496: 4b10 ldr r3, [pc, #64] @ (80014d8 ) 8001498: 681b ldr r3, [r3, #0] 800149a: 6c5a ldr r2, [r3, #68] @ 0x44 800149c: 4b0e ldr r3, [pc, #56] @ (80014d8 ) 800149e: 681b ldr r3, [r3, #0] 80014a0: 2180 movs r1, #128 @ 0x80 80014a2: 0209 lsls r1, r1, #8 80014a4: 430a orrs r2, r1 80014a6: 645a str r2, [r3, #68] @ 0x44 __HAL_TIM_ENABLE(&htim3); 80014a8: 4b0b ldr r3, [pc, #44] @ (80014d8 ) 80014aa: 681b ldr r3, [r3, #0] 80014ac: 681a ldr r2, [r3, #0] 80014ae: 4b0a ldr r3, [pc, #40] @ (80014d8 ) 80014b0: 681b ldr r3, [r3, #0] 80014b2: 2101 movs r1, #1 80014b4: 430a orrs r2, r1 80014b6: 601a str r2, [r3, #0] Uart_StartReceive(); 80014b8: f7ff fed4 bl 8001264 ADC_Init(); 80014bc: f7fe feac bl 8000218 } 80014c0: 46c0 nop @ (mov r8, r8) 80014c2: 46bd mov sp, r7 80014c4: b002 add sp, #8 80014c6: bd80 pop {r7, pc} 80014c8: 20000458 .word 0x20000458 80014cc: 40000400 .word 0x40000400 80014d0: 40012c00 .word 0x40012c00 80014d4: 20000274 .word 0x20000274 80014d8: 200002c0 .word 0x200002c0 080014dc : void USER_SetPWM(uint8_t chanel, uint16_t value) { 80014dc: b580 push {r7, lr} 80014de: b082 sub sp, #8 80014e0: af00 add r7, sp, #0 80014e2: 0002 movs r2, r0 80014e4: 1dfb adds r3, r7, #7 80014e6: 701a strb r2, [r3, #0] 80014e8: 1d3b adds r3, r7, #4 80014ea: 1c0a adds r2, r1, #0 80014ec: 801a strh r2, [r3, #0] switch ( chanel ) 80014ee: 1dfb adds r3, r7, #7 80014f0: 781b ldrb r3, [r3, #0] 80014f2: 2b04 cmp r3, #4 80014f4: d81d bhi.n 8001532 80014f6: 009a lsls r2, r3, #2 80014f8: 4b10 ldr r3, [pc, #64] @ (800153c ) 80014fa: 18d3 adds r3, r2, r3 80014fc: 681b ldr r3, [r3, #0] 80014fe: 469f mov pc, r3 { case 0: TIM3->CCR1 = value; 8001500: 4b0f ldr r3, [pc, #60] @ (8001540 ) 8001502: 1d3a adds r2, r7, #4 8001504: 8812 ldrh r2, [r2, #0] 8001506: 635a str r2, [r3, #52] @ 0x34 break; 8001508: e014 b.n 8001534 case 1: TIM3->CCR2 = value; 800150a: 4b0d ldr r3, [pc, #52] @ (8001540 ) 800150c: 1d3a adds r2, r7, #4 800150e: 8812 ldrh r2, [r2, #0] 8001510: 639a str r2, [r3, #56] @ 0x38 break; 8001512: e00f b.n 8001534 case 2: TIM1->CCR1 = value; 8001514: 4b0b ldr r3, [pc, #44] @ (8001544 ) 8001516: 1d3a adds r2, r7, #4 8001518: 8812 ldrh r2, [r2, #0] 800151a: 635a str r2, [r3, #52] @ 0x34 break; 800151c: e00a b.n 8001534 case 3: TIM1->CCR4 = value; 800151e: 4b09 ldr r3, [pc, #36] @ (8001544 ) 8001520: 1d3a adds r2, r7, #4 8001522: 8812 ldrh r2, [r2, #0] 8001524: 641a str r2, [r3, #64] @ 0x40 break; 8001526: e005 b.n 8001534 case 4: TIM1->CCR2 = value; 8001528: 4b06 ldr r3, [pc, #24] @ (8001544 ) 800152a: 1d3a adds r2, r7, #4 800152c: 8812 ldrh r2, [r2, #0] 800152e: 639a str r2, [r3, #56] @ 0x38 break; 8001530: e000 b.n 8001534 default: break; 8001532: 46c0 nop @ (mov r8, r8) } } 8001534: 46c0 nop @ (mov r8, r8) 8001536: 46bd mov sp, r7 8001538: b002 add sp, #8 800153a: bd80 pop {r7, pc} 800153c: 080060c0 .word 0x080060c0 8001540: 40000400 .word 0x40000400 8001544: 40012c00 .word 0x40012c00 08001548 : void USER_Main_Loop(void) { 8001548: b590 push {r4, r7, lr} 800154a: b085 sub sp, #20 800154c: af00 add r7, sp, #0 unsigned int ChannelValue; unsigned int tmp; unsigned int ch; if ((LinkStatistics.up_link_quality > 0) & (Uart_GetCounter() < 10)) { // ELRS connection checking 800154e: 4b6f ldr r3, [pc, #444] @ (800170c ) 8001550: 789b ldrb r3, [r3, #2] 8001552: 1e5a subs r2, r3, #1 8001554: 4193 sbcs r3, r2 8001556: b2dc uxtb r4, r3 8001558: f7ff ff3c bl 80013d4 800155c: 0003 movs r3, r0 800155e: 0019 movs r1, r3 8001560: 2209 movs r2, #9 8001562: 2300 movs r3, #0 8001564: 428a cmp r2, r1 8001566: 415b adcs r3, r3 8001568: b2db uxtb r3, r3 800156a: 4023 ands r3, r4 800156c: b2db uxtb r3, r3 800156e: 2b00 cmp r3, #0 8001570: d100 bne.n 8001574 8001572: e080 b.n 8001676 RC_LinkUpAtLeastOnce = 1; 8001574: 4b66 ldr r3, [pc, #408] @ (8001710 ) 8001576: 2201 movs r2, #1 8001578: 701a strb r2, [r3, #0] for(ch=0; ch<5; ch++) { 800157a: 2300 movs r3, #0 800157c: 60bb str r3, [r7, #8] 800157e: e014 b.n 80015aa ChannelValue = Uart_GetChannel(ch); 8001580: 68bb ldr r3, [r7, #8] 8001582: b2db uxtb r3, r3 8001584: 0018 movs r0, r3 8001586: f7ff ff01 bl 800138c 800158a: 0003 movs r3, r0 800158c: 607b str r3, [r7, #4] if (ChannelValue > 0) { 800158e: 687b ldr r3, [r7, #4] 8001590: 2b00 cmp r3, #0 8001592: d007 beq.n 80015a4 USER_SetPWM(ch, ChannelValue); 8001594: 68bb ldr r3, [r7, #8] 8001596: b2db uxtb r3, r3 8001598: 687a ldr r2, [r7, #4] 800159a: b292 uxth r2, r2 800159c: 0011 movs r1, r2 800159e: 0018 movs r0, r3 80015a0: f7ff ff9c bl 80014dc for(ch=0; ch<5; ch++) { 80015a4: 68bb ldr r3, [r7, #8] 80015a6: 3301 adds r3, #1 80015a8: 60bb str r3, [r7, #8] 80015aa: 68bb ldr r3, [r7, #8] 80015ac: 2b04 cmp r3, #4 80015ae: d9e7 bls.n 8001580 } } if (HAL_GPIO_ReadPin(SET_DEFAULT_GPIO_Port, SET_DEFAULT_Pin) == GPIO_PIN_RESET) { // Set Default Values 80015b0: 2380 movs r3, #128 @ 0x80 80015b2: 005b lsls r3, r3, #1 80015b4: 4a57 ldr r2, [pc, #348] @ (8001714 ) 80015b6: 0019 movs r1, r3 80015b8: 0010 movs r0, r2 80015ba: f002 f973 bl 80038a4 80015be: 1e03 subs r3, r0, #0 80015c0: d125 bne.n 800160e for(ch=0; ch<5; ch++) { 80015c2: 2300 movs r3, #0 80015c4: 60bb str r3, [r7, #8] 80015c6: e00d b.n 80015e4 Settings.start[ch] = Uart_GetChannel(ch); 80015c8: 68bb ldr r3, [r7, #8] 80015ca: b2db uxtb r3, r3 80015cc: 0018 movs r0, r3 80015ce: f7ff fedd bl 800138c 80015d2: 0003 movs r3, r0 80015d4: b299 uxth r1, r3 80015d6: 4b50 ldr r3, [pc, #320] @ (8001718 ) 80015d8: 68ba ldr r2, [r7, #8] 80015da: 0052 lsls r2, r2, #1 80015dc: 52d1 strh r1, [r2, r3] for(ch=0; ch<5; ch++) { 80015de: 68bb ldr r3, [r7, #8] 80015e0: 3301 adds r3, #1 80015e2: 60bb str r3, [r7, #8] 80015e4: 68bb ldr r3, [r7, #8] 80015e6: 2b04 cmp r3, #4 80015e8: d9ee bls.n 80015c8 } SettingsSave(); 80015ea: f7ff f94f bl 800088c while (HAL_GPIO_ReadPin(SET_DEFAULT_GPIO_Port, SET_DEFAULT_Pin) == GPIO_PIN_RESET) { 80015ee: e002 b.n 80015f6 HAL_Delay(10); 80015f0: 200a movs r0, #10 80015f2: f000 f943 bl 800187c while (HAL_GPIO_ReadPin(SET_DEFAULT_GPIO_Port, SET_DEFAULT_Pin) == GPIO_PIN_RESET) { 80015f6: 2380 movs r3, #128 @ 0x80 80015f8: 005b lsls r3, r3, #1 80015fa: 4a46 ldr r2, [pc, #280] @ (8001714 ) 80015fc: 0019 movs r1, r3 80015fe: 0010 movs r0, r2 8001600: f002 f950 bl 80038a4 8001604: 1e03 subs r3, r0, #0 8001606: d0f3 beq.n 80015f0 } HAL_Delay(100); 8001608: 2064 movs r0, #100 @ 0x64 800160a: f000 f937 bl 800187c } if (HAL_GPIO_ReadPin(SET_FAILSAFE_GPIO_Port, SET_FAILSAFE_Pin) == GPIO_PIN_RESET) { // Set Fail safe Values 800160e: 2380 movs r3, #128 @ 0x80 8001610: 009b lsls r3, r3, #2 8001612: 4a40 ldr r2, [pc, #256] @ (8001714 ) 8001614: 0019 movs r1, r3 8001616: 0010 movs r0, r2 8001618: f002 f944 bl 80038a4 800161c: 1e03 subs r3, r0, #0 800161e: d165 bne.n 80016ec for(ch=0; ch<5; ch++) { 8001620: 2300 movs r3, #0 8001622: 60bb str r3, [r7, #8] 8001624: e011 b.n 800164a Settings.fail[ch] = Uart_GetChannel(ch); 8001626: 68bb ldr r3, [r7, #8] 8001628: b2db uxtb r3, r3 800162a: 0018 movs r0, r3 800162c: f7ff feae bl 800138c 8001630: 0003 movs r3, r0 8001632: b299 uxth r1, r3 8001634: 4a38 ldr r2, [pc, #224] @ (8001718 ) 8001636: 68bb ldr r3, [r7, #8] 8001638: 3304 adds r3, #4 800163a: 005b lsls r3, r3, #1 800163c: 18d3 adds r3, r2, r3 800163e: 3302 adds r3, #2 8001640: 1c0a adds r2, r1, #0 8001642: 801a strh r2, [r3, #0] for(ch=0; ch<5; ch++) { 8001644: 68bb ldr r3, [r7, #8] 8001646: 3301 adds r3, #1 8001648: 60bb str r3, [r7, #8] 800164a: 68bb ldr r3, [r7, #8] 800164c: 2b04 cmp r3, #4 800164e: d9ea bls.n 8001626 } SettingsSave(); 8001650: f7ff f91c bl 800088c while (HAL_GPIO_ReadPin(SET_FAILSAFE_GPIO_Port, SET_FAILSAFE_Pin) == GPIO_PIN_RESET) { 8001654: e002 b.n 800165c HAL_Delay(10); 8001656: 200a movs r0, #10 8001658: f000 f910 bl 800187c while (HAL_GPIO_ReadPin(SET_FAILSAFE_GPIO_Port, SET_FAILSAFE_Pin) == GPIO_PIN_RESET) { 800165c: 2380 movs r3, #128 @ 0x80 800165e: 009b lsls r3, r3, #2 8001660: 4a2c ldr r2, [pc, #176] @ (8001714 ) 8001662: 0019 movs r1, r3 8001664: 0010 movs r0, r2 8001666: f002 f91d bl 80038a4 800166a: 1e03 subs r3, r0, #0 800166c: d0f3 beq.n 8001656 } HAL_Delay(100); 800166e: 2064 movs r0, #100 @ 0x64 8001670: f000 f904 bl 800187c 8001674: e03a b.n 80016ec } } else { if (RC_LinkUpAtLeastOnce == 1) { 8001676: 4b26 ldr r3, [pc, #152] @ (8001710 ) 8001678: 781b ldrb r3, [r3, #0] 800167a: 2b01 cmp r3, #1 800167c: d136 bne.n 80016ec // Check if the values ​​are set tmp = 0; 800167e: 2300 movs r3, #0 8001680: 60fb str r3, [r7, #12] for(ch=0; ch<5; ch++) { 8001682: 2300 movs r3, #0 8001684: 60bb str r3, [r7, #8] 8001686: e00d b.n 80016a4 tmp = tmp + Settings.fail[ch]; 8001688: 4a23 ldr r2, [pc, #140] @ (8001718 ) 800168a: 68bb ldr r3, [r7, #8] 800168c: 3304 adds r3, #4 800168e: 005b lsls r3, r3, #1 8001690: 18d3 adds r3, r2, r3 8001692: 3302 adds r3, #2 8001694: 881b ldrh r3, [r3, #0] 8001696: 001a movs r2, r3 8001698: 68fb ldr r3, [r7, #12] 800169a: 189b adds r3, r3, r2 800169c: 60fb str r3, [r7, #12] for(ch=0; ch<5; ch++) { 800169e: 68bb ldr r3, [r7, #8] 80016a0: 3301 adds r3, #1 80016a2: 60bb str r3, [r7, #8] 80016a4: 68bb ldr r3, [r7, #8] 80016a6: 2b04 cmp r3, #4 80016a8: d9ee bls.n 8001688 } if (tmp > 1000) { 80016aa: 68fa ldr r2, [r7, #12] 80016ac: 23fa movs r3, #250 @ 0xfa 80016ae: 009b lsls r3, r3, #2 80016b0: 429a cmp r2, r3 80016b2: d91b bls.n 80016ec // Set Fail safe values for(ch=0; ch<5; ch++) { 80016b4: 2300 movs r3, #0 80016b6: 60bb str r3, [r7, #8] 80016b8: e015 b.n 80016e6 ChannelValue = Settings.fail[ch]; 80016ba: 4a17 ldr r2, [pc, #92] @ (8001718 ) 80016bc: 68bb ldr r3, [r7, #8] 80016be: 3304 adds r3, #4 80016c0: 005b lsls r3, r3, #1 80016c2: 18d3 adds r3, r2, r3 80016c4: 3302 adds r3, #2 80016c6: 881b ldrh r3, [r3, #0] 80016c8: 607b str r3, [r7, #4] if (ChannelValue > 0) { 80016ca: 687b ldr r3, [r7, #4] 80016cc: 2b00 cmp r3, #0 80016ce: d007 beq.n 80016e0 USER_SetPWM(ch, ChannelValue); 80016d0: 68bb ldr r3, [r7, #8] 80016d2: b2db uxtb r3, r3 80016d4: 687a ldr r2, [r7, #4] 80016d6: b292 uxth r2, r2 80016d8: 0011 movs r1, r2 80016da: 0018 movs r0, r3 80016dc: f7ff fefe bl 80014dc for(ch=0; ch<5; ch++) { 80016e0: 68bb ldr r3, [r7, #8] 80016e2: 3301 adds r3, #1 80016e4: 60bb str r3, [r7, #8] 80016e6: 68bb ldr r3, [r7, #8] 80016e8: 2b04 cmp r3, #4 80016ea: d9e6 bls.n 80016ba } } } } ADC_Start_Convertion(); 80016ec: f7fe fdb0 bl 8000250 Make_Frame(); 80016f0: f7ff fdee bl 80012d0 Uart_StartSendFrame(); 80016f4: f7ff fdd8 bl 80012a8 Uart_IncCounter(); 80016f8: f7ff fe5a bl 80013b0 HAL_Delay(1); 80016fc: 2001 movs r0, #1 80016fe: f000 f8bd bl 800187c } 8001702: 46c0 nop @ (mov r8, r8) 8001704: 46bd mov sp, r7 8001706: b005 add sp, #20 8001708: bd90 pop {r4, r7, pc} 800170a: 46c0 nop @ (mov r8, r8) 800170c: 200004c0 .word 0x200004c0 8001710: 2000050d .word 0x2000050d 8001714: 50000400 .word 0x50000400 8001718: 20000458 .word 0x20000458 0800171c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 800171c: 480d ldr r0, [pc, #52] @ (8001754 ) mov sp, r0 /* set stack pointer */ 800171e: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 8001720: f7ff fb74 bl 8000e0c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001724: 480c ldr r0, [pc, #48] @ (8001758 ) ldr r1, =_edata 8001726: 490d ldr r1, [pc, #52] @ (800175c ) ldr r2, =_sidata 8001728: 4a0d ldr r2, [pc, #52] @ (8001760 ) movs r3, #0 800172a: 2300 movs r3, #0 b LoopCopyDataInit 800172c: e002 b.n 8001734 0800172e : CopyDataInit: ldr r4, [r2, r3] 800172e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001730: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001732: 3304 adds r3, #4 08001734 : LoopCopyDataInit: adds r4, r0, r3 8001734: 18c4 adds r4, r0, r3 cmp r4, r1 8001736: 428c cmp r4, r1 bcc CopyDataInit 8001738: d3f9 bcc.n 800172e /* Zero fill the bss segment. */ ldr r2, =_sbss 800173a: 4a0a ldr r2, [pc, #40] @ (8001764 ) ldr r4, =_ebss 800173c: 4c0a ldr r4, [pc, #40] @ (8001768 ) movs r3, #0 800173e: 2300 movs r3, #0 b LoopFillZerobss 8001740: e001 b.n 8001746 08001742 : FillZerobss: str r3, [r2] 8001742: 6013 str r3, [r2, #0] adds r2, r2, #4 8001744: 3204 adds r2, #4 08001746 : LoopFillZerobss: cmp r2, r4 8001746: 42a2 cmp r2, r4 bcc FillZerobss 8001748: d3fb bcc.n 8001742 /* Call static constructors */ bl __libc_init_array 800174a: f004 fc51 bl 8005ff0 <__libc_init_array> /* Call the application s entry point.*/ bl main 800174e: f7fe fdc1 bl 80002d4
08001752 : LoopForever: b LoopForever 8001752: e7fe b.n 8001752 ldr r0, =_estack 8001754: 20002000 .word 0x20002000 ldr r0, =_sdata 8001758: 20000000 .word 0x20000000 ldr r1, =_edata 800175c: 20000194 .word 0x20000194 ldr r2, =_sidata 8001760: 08006148 .word 0x08006148 ldr r2, =_sbss 8001764: 20000194 .word 0x20000194 ldr r4, =_ebss 8001768: 20000530 .word 0x20000530 0800176c : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800176c: e7fe b.n 800176c ... 08001770 : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001770: b580 push {r7, lr} 8001772: b082 sub sp, #8 8001774: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 8001776: 1dfb adds r3, r7, #7 8001778: 2200 movs r2, #0 800177a: 701a strb r2, [r3, #0] #if (INSTRUCTION_CACHE_ENABLE == 0U) __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800177c: 4b0b ldr r3, [pc, #44] @ (80017ac ) 800177e: 681a ldr r2, [r3, #0] 8001780: 4b0a ldr r3, [pc, #40] @ (80017ac ) 8001782: 2180 movs r1, #128 @ 0x80 8001784: 0049 lsls r1, r1, #1 8001786: 430a orrs r2, r1 8001788: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 800178a: 2003 movs r0, #3 800178c: f000 f810 bl 80017b0 8001790: 1e03 subs r3, r0, #0 8001792: d003 beq.n 800179c { status = HAL_ERROR; 8001794: 1dfb adds r3, r7, #7 8001796: 2201 movs r2, #1 8001798: 701a strb r2, [r3, #0] 800179a: e001 b.n 80017a0 } else { /* Init the low level hardware */ HAL_MspInit(); 800179c: f7ff f8ea bl 8000974 } /* Return function status */ return status; 80017a0: 1dfb adds r3, r7, #7 80017a2: 781b ldrb r3, [r3, #0] } 80017a4: 0018 movs r0, r3 80017a6: 46bd mov sp, r7 80017a8: b002 add sp, #8 80017aa: bd80 pop {r7, pc} 80017ac: 40022000 .word 0x40022000 080017b0 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80017b0: b590 push {r4, r7, lr} 80017b2: b085 sub sp, #20 80017b4: af00 add r7, sp, #0 80017b6: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80017b8: 230f movs r3, #15 80017ba: 18fb adds r3, r7, r3 80017bc: 2200 movs r2, #0 80017be: 701a strb r2, [r3, #0] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ if ((uint32_t)uwTickFreq != 0U) 80017c0: 4b1d ldr r3, [pc, #116] @ (8001838 ) 80017c2: 781b ldrb r3, [r3, #0] 80017c4: 2b00 cmp r3, #0 80017c6: d02b beq.n 8001820 { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U) 80017c8: 4b1c ldr r3, [pc, #112] @ (800183c ) 80017ca: 681c ldr r4, [r3, #0] 80017cc: 4b1a ldr r3, [pc, #104] @ (8001838 ) 80017ce: 781b ldrb r3, [r3, #0] 80017d0: 0019 movs r1, r3 80017d2: 23fa movs r3, #250 @ 0xfa 80017d4: 0098 lsls r0, r3, #2 80017d6: f7fe fc93 bl 8000100 <__udivsi3> 80017da: 0003 movs r3, r0 80017dc: 0019 movs r1, r3 80017de: 0020 movs r0, r4 80017e0: f7fe fc8e bl 8000100 <__udivsi3> 80017e4: 0003 movs r3, r0 80017e6: 0018 movs r0, r3 80017e8: f001 fa87 bl 8002cfa 80017ec: 1e03 subs r3, r0, #0 80017ee: d112 bne.n 8001816 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80017f0: 687b ldr r3, [r7, #4] 80017f2: 2b03 cmp r3, #3 80017f4: d80a bhi.n 800180c { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80017f6: 6879 ldr r1, [r7, #4] 80017f8: 2301 movs r3, #1 80017fa: 425b negs r3, r3 80017fc: 2200 movs r2, #0 80017fe: 0018 movs r0, r3 8001800: f001 fa56 bl 8002cb0 uwTickPrio = TickPriority; 8001804: 4b0e ldr r3, [pc, #56] @ (8001840 ) 8001806: 687a ldr r2, [r7, #4] 8001808: 601a str r2, [r3, #0] 800180a: e00d b.n 8001828 } else { status = HAL_ERROR; 800180c: 230f movs r3, #15 800180e: 18fb adds r3, r7, r3 8001810: 2201 movs r2, #1 8001812: 701a strb r2, [r3, #0] 8001814: e008 b.n 8001828 } } else { status = HAL_ERROR; 8001816: 230f movs r3, #15 8001818: 18fb adds r3, r7, r3 800181a: 2201 movs r2, #1 800181c: 701a strb r2, [r3, #0] 800181e: e003 b.n 8001828 } } else { status = HAL_ERROR; 8001820: 230f movs r3, #15 8001822: 18fb adds r3, r7, r3 8001824: 2201 movs r2, #1 8001826: 701a strb r2, [r3, #0] } /* Return function status */ return status; 8001828: 230f movs r3, #15 800182a: 18fb adds r3, r7, r3 800182c: 781b ldrb r3, [r3, #0] } 800182e: 0018 movs r0, r3 8001830: 46bd mov sp, r7 8001832: b005 add sp, #20 8001834: bd90 pop {r4, r7, pc} 8001836: 46c0 nop @ (mov r8, r8) 8001838: 20000108 .word 0x20000108 800183c: 20000000 .word 0x20000000 8001840: 20000104 .word 0x20000104 08001844 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001844: b580 push {r7, lr} 8001846: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8001848: 4b05 ldr r3, [pc, #20] @ (8001860 ) 800184a: 781b ldrb r3, [r3, #0] 800184c: 001a movs r2, r3 800184e: 4b05 ldr r3, [pc, #20] @ (8001864 ) 8001850: 681b ldr r3, [r3, #0] 8001852: 18d2 adds r2, r2, r3 8001854: 4b03 ldr r3, [pc, #12] @ (8001864 ) 8001856: 601a str r2, [r3, #0] } 8001858: 46c0 nop @ (mov r8, r8) 800185a: 46bd mov sp, r7 800185c: bd80 pop {r7, pc} 800185e: 46c0 nop @ (mov r8, r8) 8001860: 20000108 .word 0x20000108 8001864: 20000510 .word 0x20000510 08001868 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001868: b580 push {r7, lr} 800186a: af00 add r7, sp, #0 return uwTick; 800186c: 4b02 ldr r3, [pc, #8] @ (8001878 ) 800186e: 681b ldr r3, [r3, #0] } 8001870: 0018 movs r0, r3 8001872: 46bd mov sp, r7 8001874: bd80 pop {r7, pc} 8001876: 46c0 nop @ (mov r8, r8) 8001878: 20000510 .word 0x20000510 0800187c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800187c: b580 push {r7, lr} 800187e: b084 sub sp, #16 8001880: af00 add r7, sp, #0 8001882: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001884: f7ff fff0 bl 8001868 8001888: 0003 movs r3, r0 800188a: 60bb str r3, [r7, #8] uint32_t wait = Delay; 800188c: 687b ldr r3, [r7, #4] 800188e: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001890: 68fb ldr r3, [r7, #12] 8001892: 3301 adds r3, #1 8001894: d005 beq.n 80018a2 { wait += (uint32_t)(uwTickFreq); 8001896: 4b0a ldr r3, [pc, #40] @ (80018c0 ) 8001898: 781b ldrb r3, [r3, #0] 800189a: 001a movs r2, r3 800189c: 68fb ldr r3, [r7, #12] 800189e: 189b adds r3, r3, r2 80018a0: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80018a2: 46c0 nop @ (mov r8, r8) 80018a4: f7ff ffe0 bl 8001868 80018a8: 0002 movs r2, r0 80018aa: 68bb ldr r3, [r7, #8] 80018ac: 1ad3 subs r3, r2, r3 80018ae: 68fa ldr r2, [r7, #12] 80018b0: 429a cmp r2, r3 80018b2: d8f7 bhi.n 80018a4 { } } 80018b4: 46c0 nop @ (mov r8, r8) 80018b6: 46c0 nop @ (mov r8, r8) 80018b8: 46bd mov sp, r7 80018ba: b004 add sp, #16 80018bc: bd80 pop {r7, pc} 80018be: 46c0 nop @ (mov r8, r8) 80018c0: 20000108 .word 0x20000108 080018c4 : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 80018c4: b580 push {r7, lr} 80018c6: b082 sub sp, #8 80018c8: af00 add r7, sp, #0 80018ca: 6078 str r0, [r7, #4] 80018cc: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 80018ce: 687b ldr r3, [r7, #4] 80018d0: 681b ldr r3, [r3, #0] 80018d2: 4a05 ldr r2, [pc, #20] @ (80018e8 ) 80018d4: 401a ands r2, r3 80018d6: 683b ldr r3, [r7, #0] 80018d8: 431a orrs r2, r3 80018da: 687b ldr r3, [r7, #4] 80018dc: 601a str r2, [r3, #0] } 80018de: 46c0 nop @ (mov r8, r8) 80018e0: 46bd mov sp, r7 80018e2: b002 add sp, #8 80018e4: bd80 pop {r7, pc} 80018e6: 46c0 nop @ (mov r8, r8) 80018e8: fe3fffff .word 0xfe3fffff 080018ec : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { 80018ec: b580 push {r7, lr} 80018ee: b082 sub sp, #8 80018f0: af00 add r7, sp, #0 80018f2: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 80018f4: 687b ldr r3, [r7, #4] 80018f6: 681a ldr r2, [r3, #0] 80018f8: 23e0 movs r3, #224 @ 0xe0 80018fa: 045b lsls r3, r3, #17 80018fc: 4013 ands r3, r2 } 80018fe: 0018 movs r0, r3 8001900: 46bd mov sp, r7 8001902: b002 add sp, #8 8001904: bd80 pop {r7, pc} 08001906 : * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, uint32_t SamplingTime) { 8001906: b580 push {r7, lr} 8001908: b084 sub sp, #16 800190a: af00 add r7, sp, #0 800190c: 60f8 str r0, [r7, #12] 800190e: 60b9 str r1, [r7, #8] 8001910: 607a str r2, [r7, #4] MODIFY_REG(ADCx->SMPR, 8001912: 68fb ldr r3, [r7, #12] 8001914: 695b ldr r3, [r3, #20] 8001916: 68ba ldr r2, [r7, #8] 8001918: 2104 movs r1, #4 800191a: 400a ands r2, r1 800191c: 2107 movs r1, #7 800191e: 4091 lsls r1, r2 8001920: 000a movs r2, r1 8001922: 43d2 mvns r2, r2 8001924: 401a ands r2, r3 8001926: 68bb ldr r3, [r7, #8] 8001928: 2104 movs r1, #4 800192a: 400b ands r3, r1 800192c: 6879 ldr r1, [r7, #4] 800192e: 4099 lsls r1, r3 8001930: 000b movs r3, r1 8001932: 431a orrs r2, r3 8001934: 68fb ldr r3, [r7, #12] 8001936: 615a str r2, [r3, #20] ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK), SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); } 8001938: 46c0 nop @ (mov r8, r8) 800193a: 46bd mov sp, r7 800193c: b004 add sp, #16 800193e: bd80 pop {r7, pc} 08001940 : * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 */ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY) { 8001940: b580 push {r7, lr} 8001942: b082 sub sp, #8 8001944: af00 add r7, sp, #0 8001946: 6078 str r0, [r7, #4] 8001948: 6039 str r1, [r7, #0] return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) 800194a: 687b ldr r3, [r7, #4] 800194c: 695b ldr r3, [r3, #20] 800194e: 683a ldr r2, [r7, #0] 8001950: 2104 movs r1, #4 8001952: 400a ands r2, r1 8001954: 2107 movs r1, #7 8001956: 4091 lsls r1, r2 8001958: 000a movs r2, r1 800195a: 401a ands r2, r3 >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); 800195c: 683b ldr r3, [r7, #0] 800195e: 2104 movs r1, #4 8001960: 400b ands r3, r1 return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) 8001962: 40da lsrs r2, r3 8001964: 0013 movs r3, r2 } 8001966: 0018 movs r0, r3 8001968: 46bd mov sp, r7 800196a: b002 add sp, #8 800196c: bd80 pop {r7, pc} 0800196e : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { 800196e: b580 push {r7, lr} 8001970: b082 sub sp, #8 8001972: af00 add r7, sp, #0 8001974: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL); 8001976: 687b ldr r3, [r7, #4] 8001978: 68da ldr r2, [r3, #12] 800197a: 23c0 movs r3, #192 @ 0xc0 800197c: 011b lsls r3, r3, #4 800197e: 4013 ands r3, r2 8001980: d101 bne.n 8001986 8001982: 2301 movs r3, #1 8001984: e000 b.n 8001988 8001986: 2300 movs r3, #0 } 8001988: 0018 movs r0, r3 800198a: 46bd mov sp, r7 800198c: b002 add sp, #8 800198e: bd80 pop {r7, pc} 08001990 : * only if sequencer is set in mode "not fully configurable", * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 8001990: b580 push {r7, lr} 8001992: b084 sub sp, #16 8001994: af00 add r7, sp, #0 8001996: 60f8 str r0, [r7, #12] 8001998: 60b9 str r1, [r7, #8] 800199a: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ MODIFY_REG(ADCx->CHSELR, 800199c: 68fb ldr r3, [r7, #12] 800199e: 6a9b ldr r3, [r3, #40] @ 0x28 80019a0: 68ba ldr r2, [r7, #8] 80019a2: 211f movs r1, #31 80019a4: 400a ands r2, r1 80019a6: 210f movs r1, #15 80019a8: 4091 lsls r1, r2 80019aa: 000a movs r2, r1 80019ac: 43d2 mvns r2, r2 80019ae: 401a ands r2, r3 80019b0: 687b ldr r3, [r7, #4] 80019b2: 0e9b lsrs r3, r3, #26 80019b4: 210f movs r1, #15 80019b6: 4019 ands r1, r3 80019b8: 68bb ldr r3, [r7, #8] 80019ba: 201f movs r0, #31 80019bc: 4003 ands r3, r0 80019be: 4099 lsls r1, r3 80019c0: 000b movs r3, r1 80019c2: 431a orrs r2, r3 80019c4: 68fb ldr r3, [r7, #12] 80019c6: 629a str r2, [r3, #40] @ 0x28 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 80019c8: 46c0 nop @ (mov r8, r8) 80019ca: 46bd mov sp, r7 80019cc: b004 add sp, #16 80019ce: bd80 pop {r7, pc} 080019d0 : * only if sequencer is set in mode "not fully configurable", * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel) { 80019d0: b580 push {r7, lr} 80019d2: b082 sub sp, #8 80019d4: af00 add r7, sp, #0 80019d6: 6078 str r0, [r7, #4] 80019d8: 6039 str r1, [r7, #0] /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); 80019da: 687b ldr r3, [r7, #4] 80019dc: 6a9a ldr r2, [r3, #40] @ 0x28 80019de: 683b ldr r3, [r7, #0] 80019e0: 035b lsls r3, r3, #13 80019e2: 0b5b lsrs r3, r3, #13 80019e4: 431a orrs r2, r3 80019e6: 687b ldr r3, [r7, #4] 80019e8: 629a str r2, [r3, #40] @ 0x28 } 80019ea: 46c0 nop @ (mov r8, r8) 80019ec: 46bd mov sp, r7 80019ee: b002 add sp, #8 80019f0: bd80 pop {r7, pc} 080019f2 : * only if sequencer is set in mode "not fully configurable", * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel) { 80019f2: b580 push {r7, lr} 80019f4: b082 sub sp, #8 80019f6: af00 add r7, sp, #0 80019f8: 6078 str r0, [r7, #4] 80019fa: 6039 str r1, [r7, #0] /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); 80019fc: 687b ldr r3, [r7, #4] 80019fe: 6a9b ldr r3, [r3, #40] @ 0x28 8001a00: 683a ldr r2, [r7, #0] 8001a02: 0352 lsls r2, r2, #13 8001a04: 0b52 lsrs r2, r2, #13 8001a06: 43d2 mvns r2, r2 8001a08: 401a ands r2, r3 8001a0a: 687b ldr r3, [r7, #4] 8001a0c: 629a str r2, [r3, #40] @ 0x28 } 8001a0e: 46c0 nop @ (mov r8, r8) 8001a10: 46bd mov sp, r7 8001a12: b002 add sp, #8 8001a14: bd80 pop {r7, pc} ... 08001a18 : * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY) { 8001a18: b580 push {r7, lr} 8001a1a: b084 sub sp, #16 8001a1c: af00 add r7, sp, #0 8001a1e: 60f8 str r0, [r7, #12] 8001a20: 60b9 str r1, [r7, #8] 8001a22: 607a str r2, [r7, #4] /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ MODIFY_REG(ADCx->SMPR, 8001a24: 68fb ldr r3, [r7, #12] 8001a26: 695b ldr r3, [r3, #20] 8001a28: 68ba ldr r2, [r7, #8] 8001a2a: 0212 lsls r2, r2, #8 8001a2c: 43d2 mvns r2, r2 8001a2e: 401a ands r2, r3 8001a30: 68bb ldr r3, [r7, #8] 8001a32: 021b lsls r3, r3, #8 8001a34: 6879 ldr r1, [r7, #4] 8001a36: 400b ands r3, r1 8001a38: 4904 ldr r1, [pc, #16] @ (8001a4c ) 8001a3a: 400b ands r3, r1 8001a3c: 431a orrs r2, r3 8001a3e: 68fb ldr r3, [r7, #12] 8001a40: 615a str r2, [r3, #20] (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS), (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK) ); } 8001a42: 46c0 nop @ (mov r8, r8) 8001a44: 46bd mov sp, r7 8001a46: b004 add sp, #16 8001a48: bd80 pop {r7, pc} 8001a4a: 46c0 nop @ (mov r8, r8) 8001a4c: 07ffff00 .word 0x07ffff00 08001a50 : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 8001a50: b580 push {r7, lr} 8001a52: b082 sub sp, #8 8001a54: af00 add r7, sp, #0 8001a56: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001a58: 687b ldr r3, [r7, #4] 8001a5a: 689b ldr r3, [r3, #8] 8001a5c: 4a05 ldr r2, [pc, #20] @ (8001a74 ) 8001a5e: 4013 ands r3, r2 8001a60: 2280 movs r2, #128 @ 0x80 8001a62: 0552 lsls r2, r2, #21 8001a64: 431a orrs r2, r3 8001a66: 687b ldr r3, [r7, #4] 8001a68: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 8001a6a: 46c0 nop @ (mov r8, r8) 8001a6c: 46bd mov sp, r7 8001a6e: b002 add sp, #8 8001a70: bd80 pop {r7, pc} 8001a72: 46c0 nop @ (mov r8, r8) 8001a74: 6fffffe8 .word 0x6fffffe8 08001a78 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { 8001a78: b580 push {r7, lr} 8001a7a: b082 sub sp, #8 8001a7c: af00 add r7, sp, #0 8001a7e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8001a80: 687b ldr r3, [r7, #4] 8001a82: 689a ldr r2, [r3, #8] 8001a84: 2380 movs r3, #128 @ 0x80 8001a86: 055b lsls r3, r3, #21 8001a88: 401a ands r2, r3 8001a8a: 2380 movs r3, #128 @ 0x80 8001a8c: 055b lsls r3, r3, #21 8001a8e: 429a cmp r2, r3 8001a90: d101 bne.n 8001a96 8001a92: 2301 movs r3, #1 8001a94: e000 b.n 8001a98 8001a96: 2300 movs r3, #0 } 8001a98: 0018 movs r0, r3 8001a9a: 46bd mov sp, r7 8001a9c: b002 add sp, #8 8001a9e: bd80 pop {r7, pc} 08001aa0 : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { 8001aa0: b580 push {r7, lr} 8001aa2: b082 sub sp, #8 8001aa4: af00 add r7, sp, #0 8001aa6: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001aa8: 687b ldr r3, [r7, #4] 8001aaa: 689b ldr r3, [r3, #8] 8001aac: 4a04 ldr r2, [pc, #16] @ (8001ac0 ) 8001aae: 4013 ands r3, r2 8001ab0: 2201 movs r2, #1 8001ab2: 431a orrs r2, r3 8001ab4: 687b ldr r3, [r7, #4] 8001ab6: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } 8001ab8: 46c0 nop @ (mov r8, r8) 8001aba: 46bd mov sp, r7 8001abc: b002 add sp, #8 8001abe: bd80 pop {r7, pc} 8001ac0: 7fffffe8 .word 0x7fffffe8 08001ac4 : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 8001ac4: b580 push {r7, lr} 8001ac6: b082 sub sp, #8 8001ac8: af00 add r7, sp, #0 8001aca: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001acc: 687b ldr r3, [r7, #4] 8001ace: 689b ldr r3, [r3, #8] 8001ad0: 4a04 ldr r2, [pc, #16] @ (8001ae4 ) 8001ad2: 4013 ands r3, r2 8001ad4: 2202 movs r2, #2 8001ad6: 431a orrs r2, r3 8001ad8: 687b ldr r3, [r7, #4] 8001ada: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 8001adc: 46c0 nop @ (mov r8, r8) 8001ade: 46bd mov sp, r7 8001ae0: b002 add sp, #8 8001ae2: bd80 pop {r7, pc} 8001ae4: 7fffffe8 .word 0x7fffffe8 08001ae8 : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { 8001ae8: b580 push {r7, lr} 8001aea: b082 sub sp, #8 8001aec: af00 add r7, sp, #0 8001aee: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8001af0: 687b ldr r3, [r7, #4] 8001af2: 689b ldr r3, [r3, #8] 8001af4: 2201 movs r2, #1 8001af6: 4013 ands r3, r2 8001af8: 2b01 cmp r3, #1 8001afa: d101 bne.n 8001b00 8001afc: 2301 movs r3, #1 8001afe: e000 b.n 8001b02 8001b00: 2300 movs r3, #0 } 8001b02: 0018 movs r0, r3 8001b04: 46bd mov sp, r7 8001b06: b002 add sp, #8 8001b08: bd80 pop {r7, pc} 08001b0a : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { 8001b0a: b580 push {r7, lr} 8001b0c: b082 sub sp, #8 8001b0e: af00 add r7, sp, #0 8001b10: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 8001b12: 687b ldr r3, [r7, #4] 8001b14: 689b ldr r3, [r3, #8] 8001b16: 2202 movs r2, #2 8001b18: 4013 ands r3, r2 8001b1a: 2b02 cmp r3, #2 8001b1c: d101 bne.n 8001b22 8001b1e: 2301 movs r3, #1 8001b20: e000 b.n 8001b24 8001b22: 2300 movs r3, #0 } 8001b24: 0018 movs r0, r3 8001b26: 46bd mov sp, r7 8001b28: b002 add sp, #8 8001b2a: bd80 pop {r7, pc} 08001b2c : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { 8001b2c: b580 push {r7, lr} 8001b2e: b082 sub sp, #8 8001b30: af00 add r7, sp, #0 8001b32: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001b34: 687b ldr r3, [r7, #4] 8001b36: 689b ldr r3, [r3, #8] 8001b38: 4a04 ldr r2, [pc, #16] @ (8001b4c ) 8001b3a: 4013 ands r3, r2 8001b3c: 2204 movs r2, #4 8001b3e: 431a orrs r2, r3 8001b40: 687b ldr r3, [r7, #4] 8001b42: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } 8001b44: 46c0 nop @ (mov r8, r8) 8001b46: 46bd mov sp, r7 8001b48: b002 add sp, #8 8001b4a: bd80 pop {r7, pc} 8001b4c: 7fffffe8 .word 0x7fffffe8 08001b50 : * @rmtoll CR ADSTP LL_ADC_REG_StopConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) { 8001b50: b580 push {r7, lr} 8001b52: b082 sub sp, #8 8001b54: af00 add r7, sp, #0 8001b56: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001b58: 687b ldr r3, [r7, #4] 8001b5a: 689b ldr r3, [r3, #8] 8001b5c: 4a04 ldr r2, [pc, #16] @ (8001b70 ) 8001b5e: 4013 ands r3, r2 8001b60: 2210 movs r2, #16 8001b62: 431a orrs r2, r3 8001b64: 687b ldr r3, [r7, #4] 8001b66: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTP); } 8001b68: 46c0 nop @ (mov r8, r8) 8001b6a: 46bd mov sp, r7 8001b6c: b002 add sp, #8 8001b6e: bd80 pop {r7, pc} 8001b70: 7fffffe8 .word 0x7fffffe8 08001b74 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { 8001b74: b580 push {r7, lr} 8001b76: b082 sub sp, #8 8001b78: af00 add r7, sp, #0 8001b7a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8001b7c: 687b ldr r3, [r7, #4] 8001b7e: 689b ldr r3, [r3, #8] 8001b80: 2204 movs r2, #4 8001b82: 4013 ands r3, r2 8001b84: 2b04 cmp r3, #4 8001b86: d101 bne.n 8001b8c 8001b88: 2301 movs r3, #1 8001b8a: e000 b.n 8001b8e 8001b8c: 2300 movs r3, #0 } 8001b8e: 0018 movs r0, r3 8001b90: 46bd mov sp, r7 8001b92: b002 add sp, #8 8001b94: bd80 pop {r7, pc} ... 08001b98 : * of structure "ADC_InitTypeDef". * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 8001b98: b580 push {r7, lr} 8001b9a: b088 sub sp, #32 8001b9c: af00 add r7, sp, #0 8001b9e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001ba0: 231f movs r3, #31 8001ba2: 18fb adds r3, r7, r3 8001ba4: 2200 movs r2, #0 8001ba6: 701a strb r2, [r3, #0] uint32_t tmp_cfgr1 = 0UL; 8001ba8: 2300 movs r3, #0 8001baa: 61bb str r3, [r7, #24] uint32_t tmp_cfgr2 = 0UL; 8001bac: 2300 movs r3, #0 8001bae: 617b str r3, [r7, #20] uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 8001bb0: 2300 movs r3, #0 8001bb2: 60fb str r3, [r7, #12] /* Check ADC handle */ if (hadc == NULL) 8001bb4: 687b ldr r3, [r7, #4] 8001bb6: 2b00 cmp r3, #0 8001bb8: d101 bne.n 8001bbe { return HAL_ERROR; 8001bba: 2301 movs r3, #1 8001bbc: e17f b.n 8001ebe /* continuous mode is disabled. */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8001bbe: 687b ldr r3, [r7, #4] 8001bc0: 6d9b ldr r3, [r3, #88] @ 0x58 8001bc2: 2b00 cmp r3, #0 8001bc4: d10a bne.n 8001bdc /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8001bc6: 687b ldr r3, [r7, #4] 8001bc8: 0018 movs r0, r3 8001bca: f7fe fef7 bl 80009bc #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8001bce: 687b ldr r3, [r7, #4] 8001bd0: 2200 movs r2, #0 8001bd2: 65da str r2, [r3, #92] @ 0x5c /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 8001bd4: 687b ldr r3, [r7, #4] 8001bd6: 2254 movs r2, #84 @ 0x54 8001bd8: 2100 movs r1, #0 8001bda: 5499 strb r1, [r3, r2] } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8001bdc: 687b ldr r3, [r7, #4] 8001bde: 681b ldr r3, [r3, #0] 8001be0: 0018 movs r0, r3 8001be2: f7ff ff49 bl 8001a78 8001be6: 1e03 subs r3, r0, #0 8001be8: d115 bne.n 8001c16 { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 8001bea: 687b ldr r3, [r7, #4] 8001bec: 681b ldr r3, [r3, #0] 8001bee: 0018 movs r0, r3 8001bf0: f7ff ff2e bl 8001a50 /* Delay for ADC stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8001bf4: 4bb4 ldr r3, [pc, #720] @ (8001ec8 ) 8001bf6: 681b ldr r3, [r3, #0] 8001bf8: 49b4 ldr r1, [pc, #720] @ (8001ecc ) 8001bfa: 0018 movs r0, r3 8001bfc: f7fe fa80 bl 8000100 <__udivsi3> 8001c00: 0003 movs r3, r0 8001c02: 3301 adds r3, #1 8001c04: 005b lsls r3, r3, #1 8001c06: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 8001c08: e002 b.n 8001c10 { wait_loop_index--; 8001c0a: 68fb ldr r3, [r7, #12] 8001c0c: 3b01 subs r3, #1 8001c0e: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 8001c10: 68fb ldr r3, [r7, #12] 8001c12: 2b00 cmp r3, #0 8001c14: d1f9 bne.n 8001c0a } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8001c16: 687b ldr r3, [r7, #4] 8001c18: 681b ldr r3, [r3, #0] 8001c1a: 0018 movs r0, r3 8001c1c: f7ff ff2c bl 8001a78 8001c20: 1e03 subs r3, r0, #0 8001c22: d10f bne.n 8001c44 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001c24: 687b ldr r3, [r7, #4] 8001c26: 6d9b ldr r3, [r3, #88] @ 0x58 8001c28: 2210 movs r2, #16 8001c2a: 431a orrs r2, r3 8001c2c: 687b ldr r3, [r7, #4] 8001c2e: 659a str r2, [r3, #88] @ 0x58 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001c30: 687b ldr r3, [r7, #4] 8001c32: 6ddb ldr r3, [r3, #92] @ 0x5c 8001c34: 2201 movs r2, #1 8001c36: 431a orrs r2, r3 8001c38: 687b ldr r3, [r7, #4] 8001c3a: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; 8001c3c: 231f movs r3, #31 8001c3e: 18fb adds r3, r7, r3 8001c40: 2201 movs r2, #1 8001c42: 701a strb r2, [r3, #0] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8001c44: 687b ldr r3, [r7, #4] 8001c46: 681b ldr r3, [r3, #0] 8001c48: 0018 movs r0, r3 8001c4a: f7ff ff93 bl 8001b74 8001c4e: 0003 movs r3, r0 8001c50: 613b str r3, [r7, #16] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8001c52: 687b ldr r3, [r7, #4] 8001c54: 6d9b ldr r3, [r3, #88] @ 0x58 8001c56: 2210 movs r2, #16 8001c58: 4013 ands r3, r2 8001c5a: d000 beq.n 8001c5e 8001c5c: e122 b.n 8001ea4 && (tmp_adc_reg_is_conversion_on_going == 0UL) 8001c5e: 693b ldr r3, [r7, #16] 8001c60: 2b00 cmp r3, #0 8001c62: d000 beq.n 8001c66 8001c64: e11e b.n 8001ea4 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001c66: 687b ldr r3, [r7, #4] 8001c68: 6d9b ldr r3, [r3, #88] @ 0x58 8001c6a: 4a99 ldr r2, [pc, #612] @ (8001ed0 ) 8001c6c: 4013 ands r3, r2 8001c6e: 2202 movs r2, #2 8001c70: 431a orrs r2, r3 8001c72: 687b ldr r3, [r7, #4] 8001c74: 659a str r2, [r3, #88] @ 0x58 /* - DMA continuous request */ /* - Trigger frequency mode */ /* Note: If low power mode AutoPowerOff is enabled, ADC enable */ /* and disable phases are performed automatically by hardware */ /* (in this case, flag ADC_FLAG_RDY is not set). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8001c76: 687b ldr r3, [r7, #4] 8001c78: 681b ldr r3, [r3, #0] 8001c7a: 0018 movs r0, r3 8001c7c: f7ff ff34 bl 8001ae8 8001c80: 1e03 subs r3, r0, #0 8001c82: d000 beq.n 8001c86 8001c84: e0ad b.n 8001de2 /* without needing to reconfigure all other ADC groups/channels */ /* parameters): */ /* - internal measurement paths (VrefInt, ...) */ /* (set into HAL_ADC_ConfigChannel() ) */ tmp_cfgr1 |= (hadc->Init.Resolution | 8001c86: 687b ldr r3, [r7, #4] 8001c88: 689a ldr r2, [r3, #8] ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8001c8a: 687b ldr r3, [r7, #4] 8001c8c: 7e1b ldrb r3, [r3, #24] 8001c8e: 039b lsls r3, r3, #14 tmp_cfgr1 |= (hadc->Init.Resolution | 8001c90: 431a orrs r2, r3 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8001c92: 687b ldr r3, [r7, #4] 8001c94: 7e5b ldrb r3, [r3, #25] 8001c96: 03db lsls r3, r3, #15 ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8001c98: 431a orrs r2, r3 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001c9a: 687b ldr r3, [r7, #4] 8001c9c: 7e9b ldrb r3, [r3, #26] 8001c9e: 035b lsls r3, r3, #13 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8001ca0: 431a orrs r2, r3 ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8001ca2: 687b ldr r3, [r7, #4] 8001ca4: 6b1b ldr r3, [r3, #48] @ 0x30 8001ca6: 2b00 cmp r3, #0 8001ca8: d002 beq.n 8001cb0 8001caa: 2380 movs r3, #128 @ 0x80 8001cac: 015b lsls r3, r3, #5 8001cae: e000 b.n 8001cb2 8001cb0: 2300 movs r3, #0 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001cb2: 431a orrs r2, r3 hadc->Init.DataAlign | 8001cb4: 687b ldr r3, [r7, #4] 8001cb6: 68db ldr r3, [r3, #12] ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8001cb8: 431a orrs r2, r3 ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | 8001cba: 687b ldr r3, [r7, #4] 8001cbc: 691b ldr r3, [r3, #16] 8001cbe: 2b00 cmp r3, #0 8001cc0: da04 bge.n 8001ccc 8001cc2: 687b ldr r3, [r7, #4] 8001cc4: 691b ldr r3, [r3, #16] 8001cc6: 005b lsls r3, r3, #1 8001cc8: 085b lsrs r3, r3, #1 8001cca: e001 b.n 8001cd0 8001ccc: 2380 movs r3, #128 @ 0x80 8001cce: 039b lsls r3, r3, #14 hadc->Init.DataAlign | 8001cd0: 431a orrs r2, r3 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); 8001cd2: 687b ldr r3, [r7, #4] 8001cd4: 212c movs r1, #44 @ 0x2c 8001cd6: 5c5b ldrb r3, [r3, r1] 8001cd8: 005b lsls r3, r3, #1 ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | 8001cda: 4313 orrs r3, r2 tmp_cfgr1 |= (hadc->Init.Resolution | 8001cdc: 69ba ldr r2, [r7, #24] 8001cde: 4313 orrs r3, r2 8001ce0: 61bb str r3, [r7, #24] /* Update setting of discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8001ce2: 687b ldr r3, [r7, #4] 8001ce4: 2220 movs r2, #32 8001ce6: 5c9b ldrb r3, [r3, r2] 8001ce8: 2b01 cmp r3, #1 8001cea: d115 bne.n 8001d18 { if (hadc->Init.ContinuousConvMode == DISABLE) 8001cec: 687b ldr r3, [r7, #4] 8001cee: 7e9b ldrb r3, [r3, #26] 8001cf0: 2b00 cmp r3, #0 8001cf2: d105 bne.n 8001d00 { /* Enable the selected ADC group regular discontinuous mode */ tmp_cfgr1 |= ADC_CFGR1_DISCEN; 8001cf4: 69bb ldr r3, [r7, #24] 8001cf6: 2280 movs r2, #128 @ 0x80 8001cf8: 0252 lsls r2, r2, #9 8001cfa: 4313 orrs r3, r2 8001cfc: 61bb str r3, [r7, #24] 8001cfe: e00b b.n 8001d18 /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001d00: 687b ldr r3, [r7, #4] 8001d02: 6d9b ldr r3, [r3, #88] @ 0x58 8001d04: 2220 movs r2, #32 8001d06: 431a orrs r2, r3 8001d08: 687b ldr r3, [r7, #4] 8001d0a: 659a str r2, [r3, #88] @ 0x58 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001d0c: 687b ldr r3, [r7, #4] 8001d0e: 6ddb ldr r3, [r3, #92] @ 0x5c 8001d10: 2201 movs r2, #1 8001d12: 431a orrs r2, r3 8001d14: 687b ldr r3, [r7, #4] 8001d16: 65da str r2, [r3, #92] @ 0x5c /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8001d18: 687b ldr r3, [r7, #4] 8001d1a: 6a5b ldr r3, [r3, #36] @ 0x24 8001d1c: 2b00 cmp r3, #0 8001d1e: d00a beq.n 8001d36 { tmp_cfgr1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | 8001d20: 687b ldr r3, [r7, #4] 8001d22: 6a5a ldr r2, [r3, #36] @ 0x24 8001d24: 23e0 movs r3, #224 @ 0xe0 8001d26: 005b lsls r3, r3, #1 8001d28: 401a ands r2, r3 hadc->Init.ExternalTrigConvEdge); 8001d2a: 687b ldr r3, [r7, #4] 8001d2c: 6a9b ldr r3, [r3, #40] @ 0x28 tmp_cfgr1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | 8001d2e: 4313 orrs r3, r2 8001d30: 69ba ldr r2, [r7, #24] 8001d32: 4313 orrs r3, r2 8001d34: 61bb str r3, [r7, #24] } /* Update ADC configuration register with previous settings */ MODIFY_REG(hadc->Instance->CFGR1, 8001d36: 687b ldr r3, [r7, #4] 8001d38: 681b ldr r3, [r3, #0] 8001d3a: 68db ldr r3, [r3, #12] 8001d3c: 4a65 ldr r2, [pc, #404] @ (8001ed4 ) 8001d3e: 4013 ands r3, r2 8001d40: 0019 movs r1, r3 8001d42: 687b ldr r3, [r7, #4] 8001d44: 681b ldr r3, [r3, #0] 8001d46: 69ba ldr r2, [r7, #24] 8001d48: 430a orrs r2, r1 8001d4a: 60da str r2, [r3, #12] ADC_CFGR1_ALIGN | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG, tmp_cfgr1); tmp_cfgr2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | 8001d4c: 687b ldr r3, [r7, #4] 8001d4e: 685b ldr r3, [r3, #4] 8001d50: 0f9b lsrs r3, r3, #30 8001d52: 079a lsls r2, r3, #30 hadc->Init.TriggerFrequencyMode 8001d54: 687b ldr r3, [r7, #4] 8001d56: 6cdb ldr r3, [r3, #76] @ 0x4c tmp_cfgr2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | 8001d58: 4313 orrs r3, r2 8001d5a: 697a ldr r2, [r7, #20] 8001d5c: 4313 orrs r3, r2 8001d5e: 617b str r3, [r7, #20] ); if (hadc->Init.OversamplingMode == ENABLE) 8001d60: 687b ldr r3, [r7, #4] 8001d62: 223c movs r2, #60 @ 0x3c 8001d64: 5c9b ldrb r3, [r3, r2] 8001d66: 2b01 cmp r3, #1 8001d68: d111 bne.n 8001d8e { tmp_cfgr2 |= (ADC_CFGR2_OVSE | (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | 8001d6a: 687b ldr r3, [r7, #4] 8001d6c: 685b ldr r3, [r3, #4] 8001d6e: 0f9b lsrs r3, r3, #30 8001d70: 079a lsls r2, r3, #30 hadc->Init.Oversampling.Ratio | 8001d72: 687b ldr r3, [r7, #4] 8001d74: 6c1b ldr r3, [r3, #64] @ 0x40 (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | 8001d76: 431a orrs r2, r3 hadc->Init.Oversampling.RightBitShift | 8001d78: 687b ldr r3, [r7, #4] 8001d7a: 6c5b ldr r3, [r3, #68] @ 0x44 hadc->Init.Oversampling.Ratio | 8001d7c: 431a orrs r2, r3 hadc->Init.Oversampling.TriggeredMode 8001d7e: 687b ldr r3, [r7, #4] 8001d80: 6c9b ldr r3, [r3, #72] @ 0x48 hadc->Init.Oversampling.RightBitShift | 8001d82: 431a orrs r2, r3 tmp_cfgr2 |= (ADC_CFGR2_OVSE | 8001d84: 697b ldr r3, [r7, #20] 8001d86: 4313 orrs r3, r2 8001d88: 2201 movs r2, #1 8001d8a: 4313 orrs r3, r2 8001d8c: 617b str r3, [r7, #20] ); } MODIFY_REG(hadc->Instance->CFGR2, 8001d8e: 687b ldr r3, [r7, #4] 8001d90: 681b ldr r3, [r3, #0] 8001d92: 691b ldr r3, [r3, #16] 8001d94: 4a50 ldr r2, [pc, #320] @ (8001ed8 ) 8001d96: 4013 ands r3, r2 8001d98: 0019 movs r1, r3 8001d9a: 687b ldr r3, [r7, #4] 8001d9c: 681b ldr r3, [r3, #0] 8001d9e: 697a ldr r2, [r7, #20] 8001da0: 430a orrs r2, r1 8001da2: 611a str r2, [r3, #16] ADC_CFGR2_TOVS, tmp_cfgr2); /* Configuration of ADC clock mode: asynchronous clock source */ /* with selectable prescaler. */ if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) && 8001da4: 687b ldr r3, [r7, #4] 8001da6: 685a ldr r2, [r3, #4] 8001da8: 23c0 movs r3, #192 @ 0xc0 8001daa: 061b lsls r3, r3, #24 8001dac: 429a cmp r2, r3 8001dae: d018 beq.n 8001de2 ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) && 8001db0: 687b ldr r3, [r7, #4] 8001db2: 685a ldr r2, [r3, #4] if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) && 8001db4: 2380 movs r3, #128 @ 0x80 8001db6: 05db lsls r3, r3, #23 8001db8: 429a cmp r2, r3 8001dba: d012 beq.n 8001de2 ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4)) 8001dbc: 687b ldr r3, [r7, #4] 8001dbe: 685a ldr r2, [r3, #4] ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) && 8001dc0: 2380 movs r3, #128 @ 0x80 8001dc2: 061b lsls r3, r3, #24 8001dc4: 429a cmp r2, r3 8001dc6: d00c beq.n 8001de2 { MODIFY_REG(ADC1_COMMON->CCR, 8001dc8: 4b44 ldr r3, [pc, #272] @ (8001edc ) 8001dca: 681b ldr r3, [r3, #0] 8001dcc: 4a44 ldr r2, [pc, #272] @ (8001ee0 ) 8001dce: 4013 ands r3, r2 8001dd0: 0019 movs r1, r3 8001dd2: 687b ldr r3, [r7, #4] 8001dd4: 685a ldr r2, [r3, #4] 8001dd6: 23f0 movs r3, #240 @ 0xf0 8001dd8: 039b lsls r3, r3, #14 8001dda: 401a ands r2, r3 8001ddc: 4b3f ldr r3, [pc, #252] @ (8001edc ) 8001dde: 430a orrs r2, r1 8001de0: 601a str r2, [r3, #0] hadc->Init.ClockPrescaler & ADC_CCR_PRESC); } } /* Channel sampling time configuration */ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1); 8001de2: 687b ldr r3, [r7, #4] 8001de4: 6818 ldr r0, [r3, #0] 8001de6: 687b ldr r3, [r7, #4] 8001de8: 6b5b ldr r3, [r3, #52] @ 0x34 8001dea: 001a movs r2, r3 8001dec: 2100 movs r1, #0 8001dee: f7ff fd8a bl 8001906 LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2); 8001df2: 687b ldr r3, [r7, #4] 8001df4: 6818 ldr r0, [r3, #0] 8001df6: 687b ldr r3, [r7, #4] 8001df8: 6b9b ldr r3, [r3, #56] @ 0x38 8001dfa: 493a ldr r1, [pc, #232] @ (8001ee4 ) 8001dfc: 001a movs r2, r3 8001dfe: f7ff fd82 bl 8001906 /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ /* Channels must be configured into each rank using function */ /* "HAL_ADC_ConfigChannel()". */ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) 8001e02: 687b ldr r3, [r7, #4] 8001e04: 691b ldr r3, [r3, #16] 8001e06: 2b00 cmp r3, #0 8001e08: d109 bne.n 8001e1e { /* Set sequencer scan length by clearing ranks above rank 1 */ /* and do not modify rank 1 value. */ SET_BIT(hadc->Instance->CHSELR, 8001e0a: 687b ldr r3, [r7, #4] 8001e0c: 681b ldr r3, [r3, #0] 8001e0e: 6a9a ldr r2, [r3, #40] @ 0x28 8001e10: 687b ldr r3, [r7, #4] 8001e12: 681b ldr r3, [r3, #0] 8001e14: 2110 movs r1, #16 8001e16: 4249 negs r1, r1 8001e18: 430a orrs r2, r1 8001e1a: 629a str r2, [r3, #40] @ 0x28 8001e1c: e018 b.n 8001e50 ADC_CHSELR_SQ2_TO_SQ8); } else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 8001e1e: 687b ldr r3, [r7, #4] 8001e20: 691a ldr r2, [r3, #16] 8001e22: 2380 movs r3, #128 @ 0x80 8001e24: 039b lsls r3, r3, #14 8001e26: 429a cmp r2, r3 8001e28: d112 bne.n 8001e50 /* therefore after the first call of "HAL_ADC_Init()", */ /* each rank corresponding to parameter "NbrOfConversion" */ /* must be set using "HAL_ADC_ConfigChannel()". */ /* - Set sequencer scan length by clearing ranks above maximum rank */ /* and do not modify other ranks value. */ MODIFY_REG(hadc->Instance->CHSELR, 8001e2a: 687b ldr r3, [r7, #4] 8001e2c: 681b ldr r3, [r3, #0] 8001e2e: 6a9b ldr r3, [r3, #40] @ 0x28 8001e30: 687b ldr r3, [r7, #4] 8001e32: 69db ldr r3, [r3, #28] 8001e34: 3b01 subs r3, #1 8001e36: 009b lsls r3, r3, #2 8001e38: 221c movs r2, #28 8001e3a: 4013 ands r3, r2 8001e3c: 2210 movs r2, #16 8001e3e: 4252 negs r2, r2 8001e40: 409a lsls r2, r3 8001e42: 0011 movs r1, r2 8001e44: 687b ldr r3, [r7, #4] 8001e46: 6e1a ldr r2, [r3, #96] @ 0x60 8001e48: 687b ldr r3, [r7, #4] 8001e4a: 681b ldr r3, [r3, #0] 8001e4c: 430a orrs r2, r1 8001e4e: 629a str r2, [r3, #40] @ 0x28 /* Nothing to do */ } /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core peripheral clocking. */ if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) 8001e50: 687b ldr r3, [r7, #4] 8001e52: 681b ldr r3, [r3, #0] 8001e54: 2100 movs r1, #0 8001e56: 0018 movs r0, r3 8001e58: f7ff fd72 bl 8001940 8001e5c: 0002 movs r2, r0 == hadc->Init.SamplingTimeCommon1) 8001e5e: 687b ldr r3, [r7, #4] 8001e60: 6b5b ldr r3, [r3, #52] @ 0x34 if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) 8001e62: 429a cmp r2, r3 8001e64: d10b bne.n 8001e7e { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8001e66: 687b ldr r3, [r7, #4] 8001e68: 2200 movs r2, #0 8001e6a: 65da str r2, [r3, #92] @ 0x5c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001e6c: 687b ldr r3, [r7, #4] 8001e6e: 6d9b ldr r3, [r3, #88] @ 0x58 8001e70: 2203 movs r2, #3 8001e72: 4393 bics r3, r2 8001e74: 2201 movs r2, #1 8001e76: 431a orrs r2, r3 8001e78: 687b ldr r3, [r7, #4] 8001e7a: 659a str r2, [r3, #88] @ 0x58 if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) 8001e7c: e01c b.n 8001eb8 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8001e7e: 687b ldr r3, [r7, #4] 8001e80: 6d9b ldr r3, [r3, #88] @ 0x58 8001e82: 2212 movs r2, #18 8001e84: 4393 bics r3, r2 8001e86: 2210 movs r2, #16 8001e88: 431a orrs r2, r3 8001e8a: 687b ldr r3, [r7, #4] 8001e8c: 659a str r2, [r3, #88] @ 0x58 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001e8e: 687b ldr r3, [r7, #4] 8001e90: 6ddb ldr r3, [r3, #92] @ 0x5c 8001e92: 2201 movs r2, #1 8001e94: 431a orrs r2, r3 8001e96: 687b ldr r3, [r7, #4] 8001e98: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; 8001e9a: 231f movs r3, #31 8001e9c: 18fb adds r3, r7, r3 8001e9e: 2201 movs r2, #1 8001ea0: 701a strb r2, [r3, #0] if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) 8001ea2: e009 b.n 8001eb8 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001ea4: 687b ldr r3, [r7, #4] 8001ea6: 6d9b ldr r3, [r3, #88] @ 0x58 8001ea8: 2210 movs r2, #16 8001eaa: 431a orrs r2, r3 8001eac: 687b ldr r3, [r7, #4] 8001eae: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 8001eb0: 231f movs r3, #31 8001eb2: 18fb adds r3, r7, r3 8001eb4: 2201 movs r2, #1 8001eb6: 701a strb r2, [r3, #0] } return tmp_hal_status; 8001eb8: 231f movs r3, #31 8001eba: 18fb adds r3, r7, r3 8001ebc: 781b ldrb r3, [r3, #0] } 8001ebe: 0018 movs r0, r3 8001ec0: 46bd mov sp, r7 8001ec2: b008 add sp, #32 8001ec4: bd80 pop {r7, pc} 8001ec6: 46c0 nop @ (mov r8, r8) 8001ec8: 20000000 .word 0x20000000 8001ecc: 00030d40 .word 0x00030d40 8001ed0: fffffefd .word 0xfffffefd 8001ed4: ffde0201 .word 0xffde0201 8001ed8: 1ffffc02 .word 0x1ffffc02 8001edc: 40012708 .word 0x40012708 8001ee0: ffc3ffff .word 0xffc3ffff 8001ee4: 07ffff04 .word 0x07ffff04 08001ee8 : * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 8001ee8: b5b0 push {r4, r5, r7, lr} 8001eea: b086 sub sp, #24 8001eec: af00 add r7, sp, #0 8001eee: 60f8 str r0, [r7, #12] 8001ef0: 60b9 str r1, [r7, #8] 8001ef2: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8001ef4: 68fb ldr r3, [r7, #12] 8001ef6: 681b ldr r3, [r3, #0] 8001ef8: 0018 movs r0, r3 8001efa: f7ff fe3b bl 8001b74 8001efe: 1e03 subs r3, r0, #0 8001f00: d16c bne.n 8001fdc { __HAL_LOCK(hadc); 8001f02: 68fb ldr r3, [r7, #12] 8001f04: 2254 movs r2, #84 @ 0x54 8001f06: 5c9b ldrb r3, [r3, r2] 8001f08: 2b01 cmp r3, #1 8001f0a: d101 bne.n 8001f10 8001f0c: 2302 movs r3, #2 8001f0e: e06c b.n 8001fea 8001f10: 68fb ldr r3, [r7, #12] 8001f12: 2254 movs r2, #84 @ 0x54 8001f14: 2101 movs r1, #1 8001f16: 5499 strb r1, [r3, r2] /* Specific case for first call occurrence of this function (DMA transfer */ /* not activated and ADC disabled), DMA transfer must be activated */ /* with ADC disabled. */ if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) == 0UL) 8001f18: 68fb ldr r3, [r7, #12] 8001f1a: 681b ldr r3, [r3, #0] 8001f1c: 68db ldr r3, [r3, #12] 8001f1e: 2201 movs r2, #1 8001f20: 4013 ands r3, r2 8001f22: d113 bne.n 8001f4c { if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8001f24: 68fb ldr r3, [r7, #12] 8001f26: 681b ldr r3, [r3, #0] 8001f28: 0018 movs r0, r3 8001f2a: f7ff fddd bl 8001ae8 8001f2e: 1e03 subs r3, r0, #0 8001f30: d004 beq.n 8001f3c { /* Disable ADC */ LL_ADC_Disable(hadc->Instance); 8001f32: 68fb ldr r3, [r7, #12] 8001f34: 681b ldr r3, [r3, #0] 8001f36: 0018 movs r0, r3 8001f38: f7ff fdc4 bl 8001ac4 } /* Enable ADC DMA mode */ hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; 8001f3c: 68fb ldr r3, [r7, #12] 8001f3e: 681b ldr r3, [r3, #0] 8001f40: 68da ldr r2, [r3, #12] 8001f42: 68fb ldr r3, [r7, #12] 8001f44: 681b ldr r3, [r3, #0] 8001f46: 2101 movs r1, #1 8001f48: 430a orrs r2, r1 8001f4a: 60da str r2, [r3, #12] } /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8001f4c: 2517 movs r5, #23 8001f4e: 197c adds r4, r7, r5 8001f50: 68fb ldr r3, [r7, #12] 8001f52: 0018 movs r0, r3 8001f54: f000 fafa bl 800254c 8001f58: 0003 movs r3, r0 8001f5a: 7023 strb r3, [r4, #0] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8001f5c: 002c movs r4, r5 8001f5e: 193b adds r3, r7, r4 8001f60: 781b ldrb r3, [r3, #0] 8001f62: 2b00 cmp r3, #0 8001f64: d13e bne.n 8001fe4 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8001f66: 68fb ldr r3, [r7, #12] 8001f68: 6d9b ldr r3, [r3, #88] @ 0x58 8001f6a: 4a22 ldr r2, [pc, #136] @ (8001ff4 ) 8001f6c: 4013 ands r3, r2 8001f6e: 2280 movs r2, #128 @ 0x80 8001f70: 0052 lsls r2, r2, #1 8001f72: 431a orrs r2, r3 8001f74: 68fb ldr r3, [r7, #12] 8001f76: 659a str r2, [r3, #88] @ 0x58 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Set ADC error code */ /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8001f78: 68fb ldr r3, [r7, #12] 8001f7a: 2200 movs r2, #0 8001f7c: 65da str r2, [r3, #92] @ 0x5c /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8001f7e: 68fb ldr r3, [r7, #12] 8001f80: 6d1b ldr r3, [r3, #80] @ 0x50 8001f82: 4a1d ldr r2, [pc, #116] @ (8001ff8 ) 8001f84: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8001f86: 68fb ldr r3, [r7, #12] 8001f88: 6d1b ldr r3, [r3, #80] @ 0x50 8001f8a: 4a1c ldr r2, [pc, #112] @ (8001ffc ) 8001f8c: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8001f8e: 68fb ldr r3, [r7, #12] 8001f90: 6d1b ldr r3, [r3, #80] @ 0x50 8001f92: 4a1b ldr r2, [pc, #108] @ (8002000 ) 8001f94: 635a str r2, [r3, #52] @ 0x34 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8001f96: 68fb ldr r3, [r7, #12] 8001f98: 681b ldr r3, [r3, #0] 8001f9a: 221c movs r2, #28 8001f9c: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8001f9e: 68fb ldr r3, [r7, #12] 8001fa0: 2254 movs r2, #84 @ 0x54 8001fa2: 2100 movs r1, #0 8001fa4: 5499 strb r1, [r3, r2] /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 8001fa6: 68fb ldr r3, [r7, #12] 8001fa8: 681b ldr r3, [r3, #0] 8001faa: 685a ldr r2, [r3, #4] 8001fac: 68fb ldr r3, [r7, #12] 8001fae: 681b ldr r3, [r3, #0] 8001fb0: 2110 movs r1, #16 8001fb2: 430a orrs r2, r1 8001fb4: 605a str r2, [r3, #4] /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8001fb6: 68fb ldr r3, [r7, #12] 8001fb8: 6d18 ldr r0, [r3, #80] @ 0x50 8001fba: 68fb ldr r3, [r7, #12] 8001fbc: 681b ldr r3, [r3, #0] 8001fbe: 3340 adds r3, #64 @ 0x40 8001fc0: 0019 movs r1, r3 8001fc2: 68ba ldr r2, [r7, #8] 8001fc4: 193c adds r4, r7, r4 8001fc6: 687b ldr r3, [r7, #4] 8001fc8: f000 ff2e bl 8002e28 8001fcc: 0003 movs r3, r0 8001fce: 7023 strb r3, [r4, #0] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 8001fd0: 68fb ldr r3, [r7, #12] 8001fd2: 681b ldr r3, [r3, #0] 8001fd4: 0018 movs r0, r3 8001fd6: f7ff fda9 bl 8001b2c 8001fda: e003 b.n 8001fe4 } } else { tmp_hal_status = HAL_BUSY; 8001fdc: 2317 movs r3, #23 8001fde: 18fb adds r3, r7, r3 8001fe0: 2202 movs r2, #2 8001fe2: 701a strb r2, [r3, #0] } return tmp_hal_status; 8001fe4: 2317 movs r3, #23 8001fe6: 18fb adds r3, r7, r3 8001fe8: 781b ldrb r3, [r3, #0] } 8001fea: 0018 movs r0, r3 8001fec: 46bd mov sp, r7 8001fee: b006 add sp, #24 8001ff0: bdb0 pop {r4, r5, r7, pc} 8001ff2: 46c0 nop @ (mov r8, r8) 8001ff4: fffff0fe .word 0xfffff0fe 8001ff8: 08002715 .word 0x08002715 8001ffc: 080027dd .word 0x080027dd 8002000: 080027fb .word 0x080027fb 08002004 : * ADC peripheral. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { 8002004: b5b0 push {r4, r5, r7, lr} 8002006: b084 sub sp, #16 8002008: af00 add r7, sp, #0 800200a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); __HAL_LOCK(hadc); 800200c: 687b ldr r3, [r7, #4] 800200e: 2254 movs r2, #84 @ 0x54 8002010: 5c9b ldrb r3, [r3, r2] 8002012: 2b01 cmp r3, #1 8002014: d101 bne.n 800201a 8002016: 2302 movs r3, #2 8002018: e05f b.n 80020da 800201a: 687b ldr r3, [r7, #4] 800201c: 2254 movs r2, #84 @ 0x54 800201e: 2101 movs r1, #1 8002020: 5499 strb r1, [r3, r2] /* 1. Stop potential ADC group regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc); 8002022: 250f movs r5, #15 8002024: 197c adds r4, r7, r5 8002026: 687b ldr r3, [r7, #4] 8002028: 0018 movs r0, r3 800202a: f000 fa4d bl 80024c8 800202e: 0003 movs r3, r0 8002030: 7023 strb r3, [r4, #0] /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) 8002032: 0029 movs r1, r5 8002034: 187b adds r3, r7, r1 8002036: 781b ldrb r3, [r3, #0] 8002038: 2b00 cmp r3, #0 800203a: d147 bne.n 80020cc { /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) 800203c: 687b ldr r3, [r7, #4] 800203e: 6d1b ldr r3, [r3, #80] @ 0x50 8002040: 2225 movs r2, #37 @ 0x25 8002042: 5c9b ldrb r3, [r3, r2] 8002044: b2db uxtb r3, r3 8002046: 2b02 cmp r3, #2 8002048: d112 bne.n 8002070 { tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 800204a: 687b ldr r3, [r7, #4] 800204c: 6d1b ldr r3, [r3, #80] @ 0x50 800204e: 000d movs r5, r1 8002050: 187c adds r4, r7, r1 8002052: 0018 movs r0, r3 8002054: f000 ff6e bl 8002f34 8002058: 0003 movs r3, r0 800205a: 7023 strb r3, [r4, #0] /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) 800205c: 197b adds r3, r7, r5 800205e: 781b ldrb r3, [r3, #0] 8002060: 2b00 cmp r3, #0 8002062: d005 beq.n 8002070 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 8002064: 687b ldr r3, [r7, #4] 8002066: 6d9b ldr r3, [r3, #88] @ 0x58 8002068: 2240 movs r2, #64 @ 0x40 800206a: 431a orrs r2, r3 800206c: 687b ldr r3, [r7, #4] 800206e: 659a str r2, [r3, #88] @ 0x58 } } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); 8002070: 687b ldr r3, [r7, #4] 8002072: 681b ldr r3, [r3, #0] 8002074: 685a ldr r2, [r3, #4] 8002076: 687b ldr r3, [r7, #4] 8002078: 681b ldr r3, [r3, #0] 800207a: 2110 movs r1, #16 800207c: 438a bics r2, r1 800207e: 605a str r2, [r3, #4] /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to keep in memory a potential failing status. */ if (tmp_hal_status == HAL_OK) 8002080: 220f movs r2, #15 8002082: 18bb adds r3, r7, r2 8002084: 781b ldrb r3, [r3, #0] 8002086: 2b00 cmp r3, #0 8002088: d107 bne.n 800209a { tmp_hal_status = ADC_Disable(hadc); 800208a: 18bc adds r4, r7, r2 800208c: 687b ldr r3, [r7, #4] 800208e: 0018 movs r0, r3 8002090: f000 fae2 bl 8002658 8002094: 0003 movs r3, r0 8002096: 7023 strb r3, [r4, #0] 8002098: e003 b.n 80020a2 } else { (void)ADC_Disable(hadc); 800209a: 687b ldr r3, [r7, #4] 800209c: 0018 movs r0, r3 800209e: f000 fadb bl 8002658 } /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 80020a2: 230f movs r3, #15 80020a4: 18fb adds r3, r7, r3 80020a6: 781b ldrb r3, [r3, #0] 80020a8: 2b00 cmp r3, #0 80020aa: d107 bne.n 80020bc { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80020ac: 687b ldr r3, [r7, #4] 80020ae: 6d9b ldr r3, [r3, #88] @ 0x58 80020b0: 4a0c ldr r2, [pc, #48] @ (80020e4 ) 80020b2: 4013 ands r3, r2 80020b4: 2201 movs r2, #1 80020b6: 431a orrs r2, r3 80020b8: 687b ldr r3, [r7, #4] 80020ba: 659a str r2, [r3, #88] @ 0x58 HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_READY); } /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); 80020bc: 687b ldr r3, [r7, #4] 80020be: 681b ldr r3, [r3, #0] 80020c0: 68da ldr r2, [r3, #12] 80020c2: 687b ldr r3, [r7, #4] 80020c4: 681b ldr r3, [r3, #0] 80020c6: 2101 movs r1, #1 80020c8: 438a bics r2, r1 80020ca: 60da str r2, [r3, #12] } __HAL_UNLOCK(hadc); 80020cc: 687b ldr r3, [r7, #4] 80020ce: 2254 movs r2, #84 @ 0x54 80020d0: 2100 movs r1, #0 80020d2: 5499 strb r1, [r3, r2] return tmp_hal_status; 80020d4: 230f movs r3, #15 80020d6: 18fb adds r3, r7, r3 80020d8: 781b ldrb r3, [r3, #0] } 80020da: 0018 movs r0, r3 80020dc: 46bd mov sp, r7 80020de: b004 add sp, #16 80020e0: bdb0 pop {r4, r5, r7, pc} 80020e2: 46c0 nop @ (mov r8, r8) 80020e4: fffffefe .word 0xfffffefe 080020e8 : * @brief Conversion complete callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 80020e8: b580 push {r7, lr} 80020ea: b082 sub sp, #8 80020ec: af00 add r7, sp, #0 80020ee: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ } 80020f0: 46c0 nop @ (mov r8, r8) 80020f2: 46bd mov sp, r7 80020f4: b002 add sp, #8 80020f6: bd80 pop {r7, pc} 080020f8 : * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { 80020f8: b580 push {r7, lr} 80020fa: b082 sub sp, #8 80020fc: af00 add r7, sp, #0 80020fe: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8002100: 46c0 nop @ (mov r8, r8) 8002102: 46bd mov sp, r7 8002104: b002 add sp, #8 8002106: bd80 pop {r7, pc} 08002108 : * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 8002108: b580 push {r7, lr} 800210a: b082 sub sp, #8 800210c: af00 add r7, sp, #0 800210e: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 8002110: 46c0 nop @ (mov r8, r8) 8002112: 46bd mov sp, r7 8002114: b002 add sp, #8 8002116: bd80 pop {r7, pc} 08002118 : * @param hadc ADC handle * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig) { 8002118: b580 push {r7, lr} 800211a: b086 sub sp, #24 800211c: af00 add r7, sp, #0 800211e: 6078 str r0, [r7, #4] 8002120: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002122: 2317 movs r3, #23 8002124: 18fb adds r3, r7, r3 8002126: 2200 movs r2, #0 8002128: 701a strb r2, [r3, #0] uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0UL; 800212a: 2300 movs r3, #0 800212c: 60fb str r3, [r7, #12] assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank)); } __HAL_LOCK(hadc); 800212e: 687b ldr r3, [r7, #4] 8002130: 2254 movs r2, #84 @ 0x54 8002132: 5c9b ldrb r3, [r3, r2] 8002134: 2b01 cmp r3, #1 8002136: d101 bne.n 800213c 8002138: 2302 movs r3, #2 800213a: e1c0 b.n 80024be 800213c: 687b ldr r3, [r7, #4] 800213e: 2254 movs r2, #84 @ 0x54 8002140: 2101 movs r1, #1 8002142: 5499 strb r1, [r3, r2] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel sampling time */ /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8002144: 687b ldr r3, [r7, #4] 8002146: 681b ldr r3, [r3, #0] 8002148: 0018 movs r0, r3 800214a: f7ff fd13 bl 8001b74 800214e: 1e03 subs r3, r0, #0 8002150: d000 beq.n 8002154 8002152: e1a3 b.n 800249c /* If sequencer set to not fully configurable with channel rank set to */ /* none, remove the channel from the sequencer. */ /* Otherwise (sequencer set to fully configurable or to to not fully */ /* configurable with channel rank to be set), configure the selected */ /* channel. */ if (pConfig->Rank != ADC_RANK_NONE) 8002154: 683b ldr r3, [r7, #0] 8002156: 685b ldr r3, [r3, #4] 8002158: 2b02 cmp r3, #2 800215a: d100 bne.n 800215e 800215c: e143 b.n 80023e6 /* Note: ADC channel configuration requires few ADC clock cycles */ /* to be ready. Processing of ADC settings in this function */ /* induce that a specific wait time is not necessary. */ /* For more details on ADC channel configuration ready, */ /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */ if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || 800215e: 687b ldr r3, [r7, #4] 8002160: 691a ldr r2, [r3, #16] 8002162: 2380 movs r3, #128 @ 0x80 8002164: 061b lsls r3, r3, #24 8002166: 429a cmp r2, r3 8002168: d004 beq.n 8002174 (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) 800216a: 687b ldr r3, [r7, #4] 800216c: 691b ldr r3, [r3, #16] if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || 800216e: 4ac1 ldr r2, [pc, #772] @ (8002474 ) 8002170: 4293 cmp r3, r2 8002172: d108 bne.n 8002186 { /* Sequencer set to not fully configurable: */ /* Set the channel by enabling the corresponding bitfield. */ LL_ADC_REG_SetSequencerChAdd(hadc->Instance, pConfig->Channel); 8002174: 687b ldr r3, [r7, #4] 8002176: 681a ldr r2, [r3, #0] 8002178: 683b ldr r3, [r7, #0] 800217a: 681b ldr r3, [r3, #0] 800217c: 0019 movs r1, r3 800217e: 0010 movs r0, r2 8002180: f7ff fc26 bl 80019d0 8002184: e0c9 b.n 800231a { /* Sequencer set to fully configurable: */ /* Set the channel by entering it into the selected rank. */ /* Memorize the channel set into variable in HAL ADC handle */ MODIFY_REG(hadc->ADCGroupRegularSequencerRanks, 8002186: 687b ldr r3, [r7, #4] 8002188: 6e1a ldr r2, [r3, #96] @ 0x60 800218a: 683b ldr r3, [r7, #0] 800218c: 685b ldr r3, [r3, #4] 800218e: 211f movs r1, #31 8002190: 400b ands r3, r1 8002192: 210f movs r1, #15 8002194: 4099 lsls r1, r3 8002196: 000b movs r3, r1 8002198: 43db mvns r3, r3 800219a: 4013 ands r3, r2 800219c: 0019 movs r1, r3 800219e: 683b ldr r3, [r7, #0] 80021a0: 681b ldr r3, [r3, #0] 80021a2: 035b lsls r3, r3, #13 80021a4: 0b5b lsrs r3, r3, #13 80021a6: d105 bne.n 80021b4 80021a8: 683b ldr r3, [r7, #0] 80021aa: 681b ldr r3, [r3, #0] 80021ac: 0e9b lsrs r3, r3, #26 80021ae: 221f movs r2, #31 80021b0: 4013 ands r3, r2 80021b2: e098 b.n 80022e6 80021b4: 683b ldr r3, [r7, #0] 80021b6: 681b ldr r3, [r3, #0] 80021b8: 2201 movs r2, #1 80021ba: 4013 ands r3, r2 80021bc: d000 beq.n 80021c0 80021be: e091 b.n 80022e4 80021c0: 683b ldr r3, [r7, #0] 80021c2: 681b ldr r3, [r3, #0] 80021c4: 2202 movs r2, #2 80021c6: 4013 ands r3, r2 80021c8: d000 beq.n 80021cc 80021ca: e089 b.n 80022e0 80021cc: 683b ldr r3, [r7, #0] 80021ce: 681b ldr r3, [r3, #0] 80021d0: 2204 movs r2, #4 80021d2: 4013 ands r3, r2 80021d4: d000 beq.n 80021d8 80021d6: e081 b.n 80022dc 80021d8: 683b ldr r3, [r7, #0] 80021da: 681b ldr r3, [r3, #0] 80021dc: 2208 movs r2, #8 80021de: 4013 ands r3, r2 80021e0: d000 beq.n 80021e4 80021e2: e079 b.n 80022d8 80021e4: 683b ldr r3, [r7, #0] 80021e6: 681b ldr r3, [r3, #0] 80021e8: 2210 movs r2, #16 80021ea: 4013 ands r3, r2 80021ec: d000 beq.n 80021f0 80021ee: e071 b.n 80022d4 80021f0: 683b ldr r3, [r7, #0] 80021f2: 681b ldr r3, [r3, #0] 80021f4: 2220 movs r2, #32 80021f6: 4013 ands r3, r2 80021f8: d000 beq.n 80021fc 80021fa: e069 b.n 80022d0 80021fc: 683b ldr r3, [r7, #0] 80021fe: 681b ldr r3, [r3, #0] 8002200: 2240 movs r2, #64 @ 0x40 8002202: 4013 ands r3, r2 8002204: d000 beq.n 8002208 8002206: e061 b.n 80022cc 8002208: 683b ldr r3, [r7, #0] 800220a: 681b ldr r3, [r3, #0] 800220c: 2280 movs r2, #128 @ 0x80 800220e: 4013 ands r3, r2 8002210: d000 beq.n 8002214 8002212: e059 b.n 80022c8 8002214: 683b ldr r3, [r7, #0] 8002216: 681a ldr r2, [r3, #0] 8002218: 2380 movs r3, #128 @ 0x80 800221a: 005b lsls r3, r3, #1 800221c: 4013 ands r3, r2 800221e: d151 bne.n 80022c4 8002220: 683b ldr r3, [r7, #0] 8002222: 681a ldr r2, [r3, #0] 8002224: 2380 movs r3, #128 @ 0x80 8002226: 009b lsls r3, r3, #2 8002228: 4013 ands r3, r2 800222a: d149 bne.n 80022c0 800222c: 683b ldr r3, [r7, #0] 800222e: 681a ldr r2, [r3, #0] 8002230: 2380 movs r3, #128 @ 0x80 8002232: 00db lsls r3, r3, #3 8002234: 4013 ands r3, r2 8002236: d141 bne.n 80022bc 8002238: 683b ldr r3, [r7, #0] 800223a: 681a ldr r2, [r3, #0] 800223c: 2380 movs r3, #128 @ 0x80 800223e: 011b lsls r3, r3, #4 8002240: 4013 ands r3, r2 8002242: d139 bne.n 80022b8 8002244: 683b ldr r3, [r7, #0] 8002246: 681a ldr r2, [r3, #0] 8002248: 2380 movs r3, #128 @ 0x80 800224a: 015b lsls r3, r3, #5 800224c: 4013 ands r3, r2 800224e: d131 bne.n 80022b4 8002250: 683b ldr r3, [r7, #0] 8002252: 681a ldr r2, [r3, #0] 8002254: 2380 movs r3, #128 @ 0x80 8002256: 019b lsls r3, r3, #6 8002258: 4013 ands r3, r2 800225a: d129 bne.n 80022b0 800225c: 683b ldr r3, [r7, #0] 800225e: 681a ldr r2, [r3, #0] 8002260: 2380 movs r3, #128 @ 0x80 8002262: 01db lsls r3, r3, #7 8002264: 4013 ands r3, r2 8002266: d121 bne.n 80022ac 8002268: 683b ldr r3, [r7, #0] 800226a: 681a ldr r2, [r3, #0] 800226c: 2380 movs r3, #128 @ 0x80 800226e: 021b lsls r3, r3, #8 8002270: 4013 ands r3, r2 8002272: d119 bne.n 80022a8 8002274: 683b ldr r3, [r7, #0] 8002276: 681a ldr r2, [r3, #0] 8002278: 2380 movs r3, #128 @ 0x80 800227a: 025b lsls r3, r3, #9 800227c: 4013 ands r3, r2 800227e: d111 bne.n 80022a4 8002280: 683b ldr r3, [r7, #0] 8002282: 681a ldr r2, [r3, #0] 8002284: 2380 movs r3, #128 @ 0x80 8002286: 029b lsls r3, r3, #10 8002288: 4013 ands r3, r2 800228a: d109 bne.n 80022a0 800228c: 683b ldr r3, [r7, #0] 800228e: 681a ldr r2, [r3, #0] 8002290: 2380 movs r3, #128 @ 0x80 8002292: 02db lsls r3, r3, #11 8002294: 4013 ands r3, r2 8002296: d001 beq.n 800229c 8002298: 2312 movs r3, #18 800229a: e024 b.n 80022e6 800229c: 2300 movs r3, #0 800229e: e022 b.n 80022e6 80022a0: 2311 movs r3, #17 80022a2: e020 b.n 80022e6 80022a4: 2310 movs r3, #16 80022a6: e01e b.n 80022e6 80022a8: 230f movs r3, #15 80022aa: e01c b.n 80022e6 80022ac: 230e movs r3, #14 80022ae: e01a b.n 80022e6 80022b0: 230d movs r3, #13 80022b2: e018 b.n 80022e6 80022b4: 230c movs r3, #12 80022b6: e016 b.n 80022e6 80022b8: 230b movs r3, #11 80022ba: e014 b.n 80022e6 80022bc: 230a movs r3, #10 80022be: e012 b.n 80022e6 80022c0: 2309 movs r3, #9 80022c2: e010 b.n 80022e6 80022c4: 2308 movs r3, #8 80022c6: e00e b.n 80022e6 80022c8: 2307 movs r3, #7 80022ca: e00c b.n 80022e6 80022cc: 2306 movs r3, #6 80022ce: e00a b.n 80022e6 80022d0: 2305 movs r3, #5 80022d2: e008 b.n 80022e6 80022d4: 2304 movs r3, #4 80022d6: e006 b.n 80022e6 80022d8: 2303 movs r3, #3 80022da: e004 b.n 80022e6 80022dc: 2302 movs r3, #2 80022de: e002 b.n 80022e6 80022e0: 2301 movs r3, #1 80022e2: e000 b.n 80022e6 80022e4: 2300 movs r3, #0 80022e6: 683a ldr r2, [r7, #0] 80022e8: 6852 ldr r2, [r2, #4] 80022ea: 201f movs r0, #31 80022ec: 4002 ands r2, r0 80022ee: 4093 lsls r3, r2 80022f0: 000a movs r2, r1 80022f2: 431a orrs r2, r3 80022f4: 687b ldr r3, [r7, #4] 80022f6: 661a str r2, [r3, #96] @ 0x60 /* If the selected rank is below ADC group regular sequencer length, */ /* apply the configuration in ADC register. */ /* Note: Otherwise, configuration is not applied. */ /* To apply it, parameter'NbrOfConversion' must be increased. */ if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) 80022f8: 683b ldr r3, [r7, #0] 80022fa: 685b ldr r3, [r3, #4] 80022fc: 089b lsrs r3, r3, #2 80022fe: 1c5a adds r2, r3, #1 8002300: 687b ldr r3, [r7, #4] 8002302: 69db ldr r3, [r3, #28] 8002304: 429a cmp r2, r3 8002306: d808 bhi.n 800231a { LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); 8002308: 687b ldr r3, [r7, #4] 800230a: 6818 ldr r0, [r3, #0] 800230c: 683b ldr r3, [r7, #0] 800230e: 6859 ldr r1, [r3, #4] 8002310: 683b ldr r3, [r7, #0] 8002312: 681b ldr r3, [r3, #0] 8002314: 001a movs r2, r3 8002316: f7ff fb3b bl 8001990 } } /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); 800231a: 687b ldr r3, [r7, #4] 800231c: 6818 ldr r0, [r3, #0] 800231e: 683b ldr r3, [r7, #0] 8002320: 6819 ldr r1, [r3, #0] 8002322: 683b ldr r3, [r7, #0] 8002324: 689b ldr r3, [r3, #8] 8002326: 001a movs r2, r3 8002328: f7ff fb76 bl 8001a18 /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit() or removing the channel from sequencer with */ /* channel configuration parameter "Rank". */ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) 800232c: 683b ldr r3, [r7, #0] 800232e: 681b ldr r3, [r3, #0] 8002330: 2b00 cmp r3, #0 8002332: db00 blt.n 8002336 8002334: e0bc b.n 80024b0 { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8002336: 4b50 ldr r3, [pc, #320] @ (8002478 ) 8002338: 0018 movs r0, r3 800233a: f7ff fad7 bl 80018ec 800233e: 0003 movs r3, r0 8002340: 613b str r3, [r7, #16] /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && 8002342: 683b ldr r3, [r7, #0] 8002344: 681b ldr r3, [r3, #0] 8002346: 4a4d ldr r2, [pc, #308] @ (800247c ) 8002348: 4293 cmp r3, r2 800234a: d122 bne.n 8002392 ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 800234c: 693a ldr r2, [r7, #16] 800234e: 2380 movs r3, #128 @ 0x80 8002350: 041b lsls r3, r3, #16 8002352: 4013 ands r3, r2 if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && 8002354: d11d bne.n 8002392 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 8002356: 693b ldr r3, [r7, #16] 8002358: 2280 movs r2, #128 @ 0x80 800235a: 0412 lsls r2, r2, #16 800235c: 4313 orrs r3, r2 800235e: 4a46 ldr r2, [pc, #280] @ (8002478 ) 8002360: 0019 movs r1, r3 8002362: 0010 movs r0, r2 8002364: f7ff faae bl 80018c4 /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8002368: 4b45 ldr r3, [pc, #276] @ (8002480 ) 800236a: 681b ldr r3, [r3, #0] 800236c: 4945 ldr r1, [pc, #276] @ (8002484 ) 800236e: 0018 movs r0, r3 8002370: f7fd fec6 bl 8000100 <__udivsi3> 8002374: 0003 movs r3, r0 8002376: 1c5a adds r2, r3, #1 8002378: 0013 movs r3, r2 800237a: 005b lsls r3, r3, #1 800237c: 189b adds r3, r3, r2 800237e: 009b lsls r3, r3, #2 8002380: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 8002382: e002 b.n 800238a { wait_loop_index--; 8002384: 68fb ldr r3, [r7, #12] 8002386: 3b01 subs r3, #1 8002388: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 800238a: 68fb ldr r3, [r7, #12] 800238c: 2b00 cmp r3, #0 800238e: d1f9 bne.n 8002384 if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && 8002390: e08e b.n 80024b0 } } else if ((pConfig->Channel == ADC_CHANNEL_VBAT) 8002392: 683b ldr r3, [r7, #0] 8002394: 681b ldr r3, [r3, #0] 8002396: 4a3c ldr r2, [pc, #240] @ (8002488 ) 8002398: 4293 cmp r3, r2 800239a: d10e bne.n 80023ba && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 800239c: 693a ldr r2, [r7, #16] 800239e: 2380 movs r3, #128 @ 0x80 80023a0: 045b lsls r3, r3, #17 80023a2: 4013 ands r3, r2 80023a4: d109 bne.n 80023ba { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 80023a6: 693b ldr r3, [r7, #16] 80023a8: 2280 movs r2, #128 @ 0x80 80023aa: 0452 lsls r2, r2, #17 80023ac: 4313 orrs r3, r2 80023ae: 4a32 ldr r2, [pc, #200] @ (8002478 ) 80023b0: 0019 movs r1, r3 80023b2: 0010 movs r0, r2 80023b4: f7ff fa86 bl 80018c4 80023b8: e07a b.n 80024b0 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) && 80023ba: 683b ldr r3, [r7, #0] 80023bc: 681b ldr r3, [r3, #0] 80023be: 4a33 ldr r2, [pc, #204] @ (800248c ) 80023c0: 4293 cmp r3, r2 80023c2: d000 beq.n 80023c6 80023c4: e074 b.n 80024b0 ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 80023c6: 693a ldr r2, [r7, #16] 80023c8: 2380 movs r3, #128 @ 0x80 80023ca: 03db lsls r3, r3, #15 80023cc: 4013 ands r3, r2 else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) && 80023ce: d000 beq.n 80023d2 80023d0: e06e b.n 80024b0 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 80023d2: 693b ldr r3, [r7, #16] 80023d4: 2280 movs r2, #128 @ 0x80 80023d6: 03d2 lsls r2, r2, #15 80023d8: 4313 orrs r3, r2 80023da: 4a27 ldr r2, [pc, #156] @ (8002478 ) 80023dc: 0019 movs r1, r3 80023de: 0010 movs r0, r2 80023e0: f7ff fa70 bl 80018c4 80023e4: e064 b.n 80024b0 /* Regular sequencer configuration */ /* Note: Case of sequencer set to fully configurable: */ /* Sequencer rank cannot be disabled, only affected to */ /* another channel. */ /* To remove a rank, use parameter 'NbrOfConversion". */ if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || 80023e6: 687b ldr r3, [r7, #4] 80023e8: 691a ldr r2, [r3, #16] 80023ea: 2380 movs r3, #128 @ 0x80 80023ec: 061b lsls r3, r3, #24 80023ee: 429a cmp r2, r3 80023f0: d004 beq.n 80023fc (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) 80023f2: 687b ldr r3, [r7, #4] 80023f4: 691b ldr r3, [r3, #16] if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || 80023f6: 4a1f ldr r2, [pc, #124] @ (8002474 ) 80023f8: 4293 cmp r3, r2 80023fa: d107 bne.n 800240c { /* Sequencer set to not fully configurable: */ /* Reset the channel by disabling the corresponding bitfield. */ LL_ADC_REG_SetSequencerChRem(hadc->Instance, pConfig->Channel); 80023fc: 687b ldr r3, [r7, #4] 80023fe: 681a ldr r2, [r3, #0] 8002400: 683b ldr r3, [r7, #0] 8002402: 681b ldr r3, [r3, #0] 8002404: 0019 movs r1, r3 8002406: 0010 movs r0, r2 8002408: f7ff faf3 bl 80019f2 } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) 800240c: 683b ldr r3, [r7, #0] 800240e: 681b ldr r3, [r3, #0] 8002410: 2b00 cmp r3, #0 8002412: da4d bge.n 80024b0 { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8002414: 4b18 ldr r3, [pc, #96] @ (8002478 ) 8002416: 0018 movs r0, r3 8002418: f7ff fa68 bl 80018ec 800241c: 0003 movs r3, r0 800241e: 613b str r3, [r7, #16] if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8002420: 683b ldr r3, [r7, #0] 8002422: 681b ldr r3, [r3, #0] 8002424: 4a15 ldr r2, [pc, #84] @ (800247c ) 8002426: 4293 cmp r3, r2 8002428: d108 bne.n 800243c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 800242a: 693b ldr r3, [r7, #16] 800242c: 4a18 ldr r2, [pc, #96] @ (8002490 ) 800242e: 4013 ands r3, r2 8002430: 4a11 ldr r2, [pc, #68] @ (8002478 ) 8002432: 0019 movs r1, r3 8002434: 0010 movs r0, r2 8002436: f7ff fa45 bl 80018c4 800243a: e039 b.n 80024b0 ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel); } else if (pConfig->Channel == ADC_CHANNEL_VBAT) 800243c: 683b ldr r3, [r7, #0] 800243e: 681b ldr r3, [r3, #0] 8002440: 4a11 ldr r2, [pc, #68] @ (8002488 ) 8002442: 4293 cmp r3, r2 8002444: d108 bne.n 8002458 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 8002446: 693b ldr r3, [r7, #16] 8002448: 4a12 ldr r2, [pc, #72] @ (8002494 ) 800244a: 4013 ands r3, r2 800244c: 4a0a ldr r2, [pc, #40] @ (8002478 ) 800244e: 0019 movs r1, r3 8002450: 0010 movs r0, r2 8002452: f7ff fa37 bl 80018c4 8002456: e02b b.n 80024b0 ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel); } else if (pConfig->Channel == ADC_CHANNEL_VREFINT) 8002458: 683b ldr r3, [r7, #0] 800245a: 681b ldr r3, [r3, #0] 800245c: 4a0b ldr r2, [pc, #44] @ (800248c ) 800245e: 4293 cmp r3, r2 8002460: d126 bne.n 80024b0 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 8002462: 693b ldr r3, [r7, #16] 8002464: 4a0c ldr r2, [pc, #48] @ (8002498 ) 8002466: 4013 ands r3, r2 8002468: 4a03 ldr r2, [pc, #12] @ (8002478 ) 800246a: 0019 movs r1, r3 800246c: 0010 movs r0, r2 800246e: f7ff fa29 bl 80018c4 8002472: e01d b.n 80024b0 8002474: 80000004 .word 0x80000004 8002478: 40012708 .word 0x40012708 800247c: b0001000 .word 0xb0001000 8002480: 20000000 .word 0x20000000 8002484: 00030d40 .word 0x00030d40 8002488: b8004000 .word 0xb8004000 800248c: b4002000 .word 0xb4002000 8002490: ff7fffff .word 0xff7fffff 8002494: feffffff .word 0xfeffffff 8002498: ffbfffff .word 0xffbfffff /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800249c: 687b ldr r3, [r7, #4] 800249e: 6d9b ldr r3, [r3, #88] @ 0x58 80024a0: 2220 movs r2, #32 80024a2: 431a orrs r2, r3 80024a4: 687b ldr r3, [r7, #4] 80024a6: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 80024a8: 2317 movs r3, #23 80024aa: 18fb adds r3, r7, r3 80024ac: 2201 movs r2, #1 80024ae: 701a strb r2, [r3, #0] } __HAL_UNLOCK(hadc); 80024b0: 687b ldr r3, [r7, #4] 80024b2: 2254 movs r2, #84 @ 0x54 80024b4: 2100 movs r1, #0 80024b6: 5499 strb r1, [r3, r2] return tmp_hal_status; 80024b8: 2317 movs r3, #23 80024ba: 18fb adds r3, r7, r3 80024bc: 781b ldrb r3, [r3, #0] } 80024be: 0018 movs r0, r3 80024c0: 46bd mov sp, r7 80024c2: b006 add sp, #24 80024c4: bd80 pop {r7, pc} 80024c6: 46c0 nop @ (mov r8, r8) 080024c8 : * stopped to disable the ADC. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc) { 80024c8: b580 push {r7, lr} 80024ca: b084 sub sp, #16 80024cc: af00 add r7, sp, #0 80024ce: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Verification if ADC is not already stopped on regular group to bypass */ /* this function if not needed. */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) 80024d0: 687b ldr r3, [r7, #4] 80024d2: 681b ldr r3, [r3, #0] 80024d4: 0018 movs r0, r3 80024d6: f7ff fb4d bl 8001b74 80024da: 1e03 subs r3, r0, #0 80024dc: d031 beq.n 8002542 { /* Stop potential conversion on going on regular group */ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) 80024de: 687b ldr r3, [r7, #4] 80024e0: 681b ldr r3, [r3, #0] 80024e2: 0018 movs r0, r3 80024e4: f7ff fb11 bl 8001b0a 80024e8: 1e03 subs r3, r0, #0 80024ea: d104 bne.n 80024f6 { /* Stop ADC group regular conversion */ LL_ADC_REG_StopConversion(hadc->Instance); 80024ec: 687b ldr r3, [r7, #4] 80024ee: 681b ldr r3, [r3, #0] 80024f0: 0018 movs r0, r3 80024f2: f7ff fb2d bl 8001b50 } /* Wait for conversion effectively stopped */ /* Get tick count */ tickstart = HAL_GetTick(); 80024f6: f7ff f9b7 bl 8001868 80024fa: 0003 movs r3, r0 80024fc: 60fb str r3, [r7, #12] while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) 80024fe: e01a b.n 8002536 { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) 8002500: f7ff f9b2 bl 8001868 8002504: 0002 movs r2, r0 8002506: 68fb ldr r3, [r7, #12] 8002508: 1ad3 subs r3, r2, r3 800250a: 2b02 cmp r3, #2 800250c: d913 bls.n 8002536 { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) 800250e: 687b ldr r3, [r7, #4] 8002510: 681b ldr r3, [r3, #0] 8002512: 689b ldr r3, [r3, #8] 8002514: 2204 movs r2, #4 8002516: 4013 ands r3, r2 8002518: d00d beq.n 8002536 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800251a: 687b ldr r3, [r7, #4] 800251c: 6d9b ldr r3, [r3, #88] @ 0x58 800251e: 2210 movs r2, #16 8002520: 431a orrs r2, r3 8002522: 687b ldr r3, [r7, #4] 8002524: 659a str r2, [r3, #88] @ 0x58 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002526: 687b ldr r3, [r7, #4] 8002528: 6ddb ldr r3, [r3, #92] @ 0x5c 800252a: 2201 movs r2, #1 800252c: 431a orrs r2, r3 800252e: 687b ldr r3, [r7, #4] 8002530: 65da str r2, [r3, #92] @ 0x5c return HAL_ERROR; 8002532: 2301 movs r3, #1 8002534: e006 b.n 8002544 while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) 8002536: 687b ldr r3, [r7, #4] 8002538: 681b ldr r3, [r3, #0] 800253a: 689b ldr r3, [r3, #8] 800253c: 2204 movs r2, #4 800253e: 4013 ands r3, r2 8002540: d1de bne.n 8002500 } } /* Return HAL status */ return HAL_OK; 8002542: 2300 movs r3, #0 } 8002544: 0018 movs r0, r3 8002546: 46bd mov sp, r7 8002548: b004 add sp, #16 800254a: bd80 pop {r7, pc} 0800254c : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { 800254c: b580 push {r7, lr} 800254e: b084 sub sp, #16 8002550: af00 add r7, sp, #0 8002552: 6078 str r0, [r7, #4] uint32_t tickstart; __IO uint32_t wait_loop_index = 0UL; 8002554: 2300 movs r3, #0 8002556: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8002558: 687b ldr r3, [r7, #4] 800255a: 681b ldr r3, [r3, #0] 800255c: 0018 movs r0, r3 800255e: f7ff fac3 bl 8001ae8 8002562: 1e03 subs r3, r0, #0 8002564: d000 beq.n 8002568 8002566: e069 b.n 800263c { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 8002568: 687b ldr r3, [r7, #4] 800256a: 681b ldr r3, [r3, #0] 800256c: 689b ldr r3, [r3, #8] 800256e: 4a36 ldr r2, [pc, #216] @ (8002648 ) 8002570: 4013 ands r3, r2 8002572: d00d beq.n 8002590 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002574: 687b ldr r3, [r7, #4] 8002576: 6d9b ldr r3, [r3, #88] @ 0x58 8002578: 2210 movs r2, #16 800257a: 431a orrs r2, r3 800257c: 687b ldr r3, [r7, #4] 800257e: 659a str r2, [r3, #88] @ 0x58 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002580: 687b ldr r3, [r7, #4] 8002582: 6ddb ldr r3, [r3, #92] @ 0x5c 8002584: 2201 movs r2, #1 8002586: 431a orrs r2, r3 8002588: 687b ldr r3, [r7, #4] 800258a: 65da str r2, [r3, #92] @ 0x5c return HAL_ERROR; 800258c: 2301 movs r3, #1 800258e: e056 b.n 800263e } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); 8002590: 687b ldr r3, [r7, #4] 8002592: 681b ldr r3, [r3, #0] 8002594: 0018 movs r0, r3 8002596: f7ff fa83 bl 8001aa0 if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) 800259a: 4b2c ldr r3, [pc, #176] @ (800264c ) 800259c: 0018 movs r0, r3 800259e: f7ff f9a5 bl 80018ec 80025a2: 0002 movs r2, r0 80025a4: 2380 movs r3, #128 @ 0x80 80025a6: 041b lsls r3, r3, #16 80025a8: 4013 ands r3, r2 80025aa: d00f beq.n 80025cc /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80025ac: 4b28 ldr r3, [pc, #160] @ (8002650 ) 80025ae: 681b ldr r3, [r3, #0] 80025b0: 4928 ldr r1, [pc, #160] @ (8002654 ) 80025b2: 0018 movs r0, r3 80025b4: f7fd fda4 bl 8000100 <__udivsi3> 80025b8: 0003 movs r3, r0 80025ba: 3301 adds r3, #1 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) 80025bc: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 80025be: e002 b.n 80025c6 { wait_loop_index--; 80025c0: 68bb ldr r3, [r7, #8] 80025c2: 3b01 subs r3, #1 80025c4: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 80025c6: 68bb ldr r3, [r7, #8] 80025c8: 2b00 cmp r3, #0 80025ca: d1f9 bne.n 80025c0 } } /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ /* performed automatically by hardware and flag ADC ready is not set. */ if (hadc->Init.LowPowerAutoPowerOff != ENABLE) 80025cc: 687b ldr r3, [r7, #4] 80025ce: 7e5b ldrb r3, [r3, #25] 80025d0: 2b01 cmp r3, #1 80025d2: d033 beq.n 800263c { /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 80025d4: f7ff f948 bl 8001868 80025d8: 0003 movs r3, r0 80025da: 60fb str r3, [r7, #12] while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 80025dc: e027 b.n 800262e The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80025de: 687b ldr r3, [r7, #4] 80025e0: 681b ldr r3, [r3, #0] 80025e2: 0018 movs r0, r3 80025e4: f7ff fa80 bl 8001ae8 80025e8: 1e03 subs r3, r0, #0 80025ea: d104 bne.n 80025f6 { LL_ADC_Enable(hadc->Instance); 80025ec: 687b ldr r3, [r7, #4] 80025ee: 681b ldr r3, [r3, #0] 80025f0: 0018 movs r0, r3 80025f2: f7ff fa55 bl 8001aa0 } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80025f6: f7ff f937 bl 8001868 80025fa: 0002 movs r2, r0 80025fc: 68fb ldr r3, [r7, #12] 80025fe: 1ad3 subs r3, r2, r3 8002600: 2b02 cmp r3, #2 8002602: d914 bls.n 800262e { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8002604: 687b ldr r3, [r7, #4] 8002606: 681b ldr r3, [r3, #0] 8002608: 681b ldr r3, [r3, #0] 800260a: 2201 movs r2, #1 800260c: 4013 ands r3, r2 800260e: 2b01 cmp r3, #1 8002610: d00d beq.n 800262e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002612: 687b ldr r3, [r7, #4] 8002614: 6d9b ldr r3, [r3, #88] @ 0x58 8002616: 2210 movs r2, #16 8002618: 431a orrs r2, r3 800261a: 687b ldr r3, [r7, #4] 800261c: 659a str r2, [r3, #88] @ 0x58 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800261e: 687b ldr r3, [r7, #4] 8002620: 6ddb ldr r3, [r3, #92] @ 0x5c 8002622: 2201 movs r2, #1 8002624: 431a orrs r2, r3 8002626: 687b ldr r3, [r7, #4] 8002628: 65da str r2, [r3, #92] @ 0x5c return HAL_ERROR; 800262a: 2301 movs r3, #1 800262c: e007 b.n 800263e while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 800262e: 687b ldr r3, [r7, #4] 8002630: 681b ldr r3, [r3, #0] 8002632: 681b ldr r3, [r3, #0] 8002634: 2201 movs r2, #1 8002636: 4013 ands r3, r2 8002638: 2b01 cmp r3, #1 800263a: d1d0 bne.n 80025de } } } /* Return HAL status */ return HAL_OK; 800263c: 2300 movs r3, #0 } 800263e: 0018 movs r0, r3 8002640: 46bd mov sp, r7 8002642: b004 add sp, #16 8002644: bd80 pop {r7, pc} 8002646: 46c0 nop @ (mov r8, r8) 8002648: 80000017 .word 0x80000017 800264c: 40012708 .word 0x40012708 8002650: 20000000 .word 0x20000000 8002654: 00030d40 .word 0x00030d40 08002658 : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 8002658: b580 push {r7, lr} 800265a: b084 sub sp, #16 800265c: af00 add r7, sp, #0 800265e: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 8002660: 687b ldr r3, [r7, #4] 8002662: 681b ldr r3, [r3, #0] 8002664: 0018 movs r0, r3 8002666: f7ff fa50 bl 8001b0a 800266a: 0003 movs r3, r0 800266c: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 800266e: 687b ldr r3, [r7, #4] 8002670: 681b ldr r3, [r3, #0] 8002672: 0018 movs r0, r3 8002674: f7ff fa38 bl 8001ae8 8002678: 1e03 subs r3, r0, #0 800267a: d046 beq.n 800270a && (tmp_adc_is_disable_on_going == 0UL) 800267c: 68fb ldr r3, [r7, #12] 800267e: 2b00 cmp r3, #0 8002680: d143 bne.n 800270a ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 8002682: 687b ldr r3, [r7, #4] 8002684: 681b ldr r3, [r3, #0] 8002686: 689b ldr r3, [r3, #8] 8002688: 2205 movs r2, #5 800268a: 4013 ands r3, r2 800268c: 2b01 cmp r3, #1 800268e: d10d bne.n 80026ac { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 8002690: 687b ldr r3, [r7, #4] 8002692: 681b ldr r3, [r3, #0] 8002694: 0018 movs r0, r3 8002696: f7ff fa15 bl 8001ac4 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 800269a: 687b ldr r3, [r7, #4] 800269c: 681b ldr r3, [r3, #0] 800269e: 2203 movs r2, #3 80026a0: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 80026a2: f7ff f8e1 bl 8001868 80026a6: 0003 movs r3, r0 80026a8: 60bb str r3, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 80026aa: e028 b.n 80026fe SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80026ac: 687b ldr r3, [r7, #4] 80026ae: 6d9b ldr r3, [r3, #88] @ 0x58 80026b0: 2210 movs r2, #16 80026b2: 431a orrs r2, r3 80026b4: 687b ldr r3, [r7, #4] 80026b6: 659a str r2, [r3, #88] @ 0x58 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80026b8: 687b ldr r3, [r7, #4] 80026ba: 6ddb ldr r3, [r3, #92] @ 0x5c 80026bc: 2201 movs r2, #1 80026be: 431a orrs r2, r3 80026c0: 687b ldr r3, [r7, #4] 80026c2: 65da str r2, [r3, #92] @ 0x5c return HAL_ERROR; 80026c4: 2301 movs r3, #1 80026c6: e021 b.n 800270c { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 80026c8: f7ff f8ce bl 8001868 80026cc: 0002 movs r2, r0 80026ce: 68bb ldr r3, [r7, #8] 80026d0: 1ad3 subs r3, r2, r3 80026d2: 2b02 cmp r3, #2 80026d4: d913 bls.n 80026fe { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 80026d6: 687b ldr r3, [r7, #4] 80026d8: 681b ldr r3, [r3, #0] 80026da: 689b ldr r3, [r3, #8] 80026dc: 2201 movs r2, #1 80026de: 4013 ands r3, r2 80026e0: d00d beq.n 80026fe { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80026e2: 687b ldr r3, [r7, #4] 80026e4: 6d9b ldr r3, [r3, #88] @ 0x58 80026e6: 2210 movs r2, #16 80026e8: 431a orrs r2, r3 80026ea: 687b ldr r3, [r7, #4] 80026ec: 659a str r2, [r3, #88] @ 0x58 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80026ee: 687b ldr r3, [r7, #4] 80026f0: 6ddb ldr r3, [r3, #92] @ 0x5c 80026f2: 2201 movs r2, #1 80026f4: 431a orrs r2, r3 80026f6: 687b ldr r3, [r7, #4] 80026f8: 65da str r2, [r3, #92] @ 0x5c return HAL_ERROR; 80026fa: 2301 movs r3, #1 80026fc: e006 b.n 800270c while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 80026fe: 687b ldr r3, [r7, #4] 8002700: 681b ldr r3, [r3, #0] 8002702: 689b ldr r3, [r3, #8] 8002704: 2201 movs r2, #1 8002706: 4013 ands r3, r2 8002708: d1de bne.n 80026c8 } } } /* Return HAL status */ return HAL_OK; 800270a: 2300 movs r3, #0 } 800270c: 0018 movs r0, r3 800270e: 46bd mov sp, r7 8002710: b004 add sp, #16 8002712: bd80 pop {r7, pc} 08002714 : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 8002714: b580 push {r7, lr} 8002716: b084 sub sp, #16 8002718: af00 add r7, sp, #0 800271a: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800271c: 687b ldr r3, [r7, #4] 800271e: 6a9b ldr r3, [r3, #40] @ 0x28 8002720: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8002722: 68fb ldr r3, [r7, #12] 8002724: 6d9b ldr r3, [r3, #88] @ 0x58 8002726: 2250 movs r2, #80 @ 0x50 8002728: 4013 ands r3, r2 800272a: d141 bne.n 80027b0 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800272c: 68fb ldr r3, [r7, #12] 800272e: 6d9b ldr r3, [r3, #88] @ 0x58 8002730: 2280 movs r2, #128 @ 0x80 8002732: 0092 lsls r2, r2, #2 8002734: 431a orrs r2, r3 8002736: 68fb ldr r3, [r7, #12] 8002738: 659a str r2, [r3, #88] @ 0x58 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 800273a: 68fb ldr r3, [r7, #12] 800273c: 681b ldr r3, [r3, #0] 800273e: 0018 movs r0, r3 8002740: f7ff f915 bl 800196e 8002744: 1e03 subs r3, r0, #0 8002746: d02e beq.n 80027a6 && (hadc->Init.ContinuousConvMode == DISABLE) 8002748: 68fb ldr r3, [r7, #12] 800274a: 7e9b ldrb r3, [r3, #26] 800274c: 2b00 cmp r3, #0 800274e: d12a bne.n 80027a6 ) { /* If End of Sequence is reached, disable interrupts */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) 8002750: 68fb ldr r3, [r7, #12] 8002752: 681b ldr r3, [r3, #0] 8002754: 681b ldr r3, [r3, #0] 8002756: 2208 movs r2, #8 8002758: 4013 ands r3, r2 800275a: 2b08 cmp r3, #8 800275c: d123 bne.n 80027a6 { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 800275e: 68fb ldr r3, [r7, #12] 8002760: 681b ldr r3, [r3, #0] 8002762: 0018 movs r0, r3 8002764: f7ff fa06 bl 8001b74 8002768: 1e03 subs r3, r0, #0 800276a: d110 bne.n 800278e { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); 800276c: 68fb ldr r3, [r7, #12] 800276e: 681b ldr r3, [r3, #0] 8002770: 685a ldr r2, [r3, #4] 8002772: 68fb ldr r3, [r7, #12] 8002774: 681b ldr r3, [r3, #0] 8002776: 210c movs r1, #12 8002778: 438a bics r2, r1 800277a: 605a str r2, [r3, #4] /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800277c: 68fb ldr r3, [r7, #12] 800277e: 6d9b ldr r3, [r3, #88] @ 0x58 8002780: 4a15 ldr r2, [pc, #84] @ (80027d8 ) 8002782: 4013 ands r3, r2 8002784: 2201 movs r2, #1 8002786: 431a orrs r2, r3 8002788: 68fb ldr r3, [r7, #12] 800278a: 659a str r2, [r3, #88] @ 0x58 800278c: e00b b.n 80027a6 HAL_ADC_STATE_READY); } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800278e: 68fb ldr r3, [r7, #12] 8002790: 6d9b ldr r3, [r3, #88] @ 0x58 8002792: 2220 movs r2, #32 8002794: 431a orrs r2, r3 8002796: 68fb ldr r3, [r7, #12] 8002798: 659a str r2, [r3, #88] @ 0x58 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800279a: 68fb ldr r3, [r7, #12] 800279c: 6ddb ldr r3, [r3, #92] @ 0x5c 800279e: 2201 movs r2, #1 80027a0: 431a orrs r2, r3 80027a2: 68fb ldr r3, [r7, #12] 80027a4: 65da str r2, [r3, #92] @ 0x5c /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 80027a6: 68fb ldr r3, [r7, #12] 80027a8: 0018 movs r0, r3 80027aa: f7ff fc9d bl 80020e8 { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } 80027ae: e00f b.n 80027d0 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 80027b0: 68fb ldr r3, [r7, #12] 80027b2: 6d9b ldr r3, [r3, #88] @ 0x58 80027b4: 2210 movs r2, #16 80027b6: 4013 ands r3, r2 80027b8: d004 beq.n 80027c4 HAL_ADC_ErrorCallback(hadc); 80027ba: 68fb ldr r3, [r7, #12] 80027bc: 0018 movs r0, r3 80027be: f7ff fca3 bl 8002108 } 80027c2: e005 b.n 80027d0 hadc->DMA_Handle->XferErrorCallback(hdma); 80027c4: 68fb ldr r3, [r7, #12] 80027c6: 6d1b ldr r3, [r3, #80] @ 0x50 80027c8: 6b5b ldr r3, [r3, #52] @ 0x34 80027ca: 687a ldr r2, [r7, #4] 80027cc: 0010 movs r0, r2 80027ce: 4798 blx r3 } 80027d0: 46c0 nop @ (mov r8, r8) 80027d2: 46bd mov sp, r7 80027d4: b004 add sp, #16 80027d6: bd80 pop {r7, pc} 80027d8: fffffefe .word 0xfffffefe 080027dc : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 80027dc: b580 push {r7, lr} 80027de: b084 sub sp, #16 80027e0: af00 add r7, sp, #0 80027e2: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80027e4: 687b ldr r3, [r7, #4] 80027e6: 6a9b ldr r3, [r3, #40] @ 0x28 80027e8: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 80027ea: 68fb ldr r3, [r7, #12] 80027ec: 0018 movs r0, r3 80027ee: f7ff fc83 bl 80020f8 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 80027f2: 46c0 nop @ (mov r8, r8) 80027f4: 46bd mov sp, r7 80027f6: b004 add sp, #16 80027f8: bd80 pop {r7, pc} 080027fa : * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAError(DMA_HandleTypeDef *hdma) { 80027fa: b580 push {r7, lr} 80027fc: b084 sub sp, #16 80027fe: af00 add r7, sp, #0 8002800: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8002802: 687b ldr r3, [r7, #4] 8002804: 6a9b ldr r3, [r3, #40] @ 0x28 8002806: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 8002808: 68fb ldr r3, [r7, #12] 800280a: 6d9b ldr r3, [r3, #88] @ 0x58 800280c: 2240 movs r2, #64 @ 0x40 800280e: 431a orrs r2, r3 8002810: 68fb ldr r3, [r7, #12] 8002812: 659a str r2, [r3, #88] @ 0x58 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8002814: 68fb ldr r3, [r7, #12] 8002816: 6ddb ldr r3, [r3, #92] @ 0x5c 8002818: 2204 movs r2, #4 800281a: 431a orrs r2, r3 800281c: 68fb ldr r3, [r7, #12] 800281e: 65da str r2, [r3, #92] @ 0x5c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8002820: 68fb ldr r3, [r7, #12] 8002822: 0018 movs r0, r3 8002824: f7ff fc70 bl 8002108 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8002828: 46c0 nop @ (mov r8, r8) 800282a: 46bd mov sp, r7 800282c: b004 add sp, #16 800282e: bd80 pop {r7, pc} 08002830 : { 8002830: b580 push {r7, lr} 8002832: b082 sub sp, #8 8002834: af00 add r7, sp, #0 8002836: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); 8002838: 687b ldr r3, [r7, #4] 800283a: 681a ldr r2, [r3, #0] 800283c: 23f0 movs r3, #240 @ 0xf0 800283e: 039b lsls r3, r3, #14 8002840: 4013 ands r3, r2 } 8002842: 0018 movs r0, r3 8002844: 46bd mov sp, r7 8002846: b002 add sp, #8 8002848: bd80 pop {r7, pc} 0800284a : { 800284a: b580 push {r7, lr} 800284c: b082 sub sp, #8 800284e: af00 add r7, sp, #0 8002850: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); 8002852: 687b ldr r3, [r7, #4] 8002854: 691b ldr r3, [r3, #16] 8002856: 0f9b lsrs r3, r3, #30 8002858: 079b lsls r3, r3, #30 } 800285a: 0018 movs r0, r3 800285c: 46bd mov sp, r7 800285e: b002 add sp, #8 8002860: bd80 pop {r7, pc} 08002862 : { 8002862: b580 push {r7, lr} 8002864: b082 sub sp, #8 8002866: af00 add r7, sp, #0 8002868: 6078 str r0, [r7, #4] 800286a: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CALFACT, 800286c: 687b ldr r3, [r7, #4] 800286e: 22b4 movs r2, #180 @ 0xb4 8002870: 589b ldr r3, [r3, r2] 8002872: 227f movs r2, #127 @ 0x7f 8002874: 4393 bics r3, r2 8002876: 001a movs r2, r3 8002878: 683b ldr r3, [r7, #0] 800287a: 431a orrs r2, r3 800287c: 687b ldr r3, [r7, #4] 800287e: 21b4 movs r1, #180 @ 0xb4 8002880: 505a str r2, [r3, r1] } 8002882: 46c0 nop @ (mov r8, r8) 8002884: 46bd mov sp, r7 8002886: b002 add sp, #8 8002888: bd80 pop {r7, pc} 0800288a : { 800288a: b580 push {r7, lr} 800288c: b082 sub sp, #8 800288e: af00 add r7, sp, #0 8002890: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT)); 8002892: 687b ldr r3, [r7, #4] 8002894: 22b4 movs r2, #180 @ 0xb4 8002896: 589b ldr r3, [r3, r2] 8002898: 227f movs r2, #127 @ 0x7f 800289a: 4013 ands r3, r2 } 800289c: 0018 movs r0, r3 800289e: 46bd mov sp, r7 80028a0: b002 add sp, #8 80028a2: bd80 pop {r7, pc} 080028a4 : { 80028a4: b580 push {r7, lr} 80028a6: b082 sub sp, #8 80028a8: af00 add r7, sp, #0 80028aa: 6078 str r0, [r7, #4] MODIFY_REG(ADCx->CR, 80028ac: 687b ldr r3, [r7, #4] 80028ae: 689b ldr r3, [r3, #8] 80028b0: 4a04 ldr r2, [pc, #16] @ (80028c4 ) 80028b2: 4013 ands r3, r2 80028b4: 2201 movs r2, #1 80028b6: 431a orrs r2, r3 80028b8: 687b ldr r3, [r7, #4] 80028ba: 609a str r2, [r3, #8] } 80028bc: 46c0 nop @ (mov r8, r8) 80028be: 46bd mov sp, r7 80028c0: b002 add sp, #8 80028c2: bd80 pop {r7, pc} 80028c4: 7fffffe8 .word 0x7fffffe8 080028c8 : { 80028c8: b580 push {r7, lr} 80028ca: b082 sub sp, #8 80028cc: af00 add r7, sp, #0 80028ce: 6078 str r0, [r7, #4] MODIFY_REG(ADCx->CR, 80028d0: 687b ldr r3, [r7, #4] 80028d2: 689b ldr r3, [r3, #8] 80028d4: 4a04 ldr r2, [pc, #16] @ (80028e8 ) 80028d6: 4013 ands r3, r2 80028d8: 2202 movs r2, #2 80028da: 431a orrs r2, r3 80028dc: 687b ldr r3, [r7, #4] 80028de: 609a str r2, [r3, #8] } 80028e0: 46c0 nop @ (mov r8, r8) 80028e2: 46bd mov sp, r7 80028e4: b002 add sp, #8 80028e6: bd80 pop {r7, pc} 80028e8: 7fffffe8 .word 0x7fffffe8 080028ec : { 80028ec: b580 push {r7, lr} 80028ee: b082 sub sp, #8 80028f0: af00 add r7, sp, #0 80028f2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80028f4: 687b ldr r3, [r7, #4] 80028f6: 689b ldr r3, [r3, #8] 80028f8: 2201 movs r2, #1 80028fa: 4013 ands r3, r2 80028fc: 2b01 cmp r3, #1 80028fe: d101 bne.n 8002904 8002900: 2301 movs r3, #1 8002902: e000 b.n 8002906 8002904: 2300 movs r3, #0 } 8002906: 0018 movs r0, r3 8002908: 46bd mov sp, r7 800290a: b002 add sp, #8 800290c: bd80 pop {r7, pc} ... 08002910 : { 8002910: b580 push {r7, lr} 8002912: b082 sub sp, #8 8002914: af00 add r7, sp, #0 8002916: 6078 str r0, [r7, #4] MODIFY_REG(ADCx->CR, 8002918: 687b ldr r3, [r7, #4] 800291a: 689b ldr r3, [r3, #8] 800291c: 4a05 ldr r2, [pc, #20] @ (8002934 ) 800291e: 4013 ands r3, r2 8002920: 2280 movs r2, #128 @ 0x80 8002922: 0612 lsls r2, r2, #24 8002924: 431a orrs r2, r3 8002926: 687b ldr r3, [r7, #4] 8002928: 609a str r2, [r3, #8] } 800292a: 46c0 nop @ (mov r8, r8) 800292c: 46bd mov sp, r7 800292e: b002 add sp, #8 8002930: bd80 pop {r7, pc} 8002932: 46c0 nop @ (mov r8, r8) 8002934: 7fffffe8 .word 0x7fffffe8 08002938 : { 8002938: b580 push {r7, lr} 800293a: b082 sub sp, #8 800293c: af00 add r7, sp, #0 800293e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 8002940: 687b ldr r3, [r7, #4] 8002942: 689b ldr r3, [r3, #8] 8002944: 0fdb lsrs r3, r3, #31 8002946: 07da lsls r2, r3, #31 8002948: 2380 movs r3, #128 @ 0x80 800294a: 061b lsls r3, r3, #24 800294c: 429a cmp r2, r3 800294e: d101 bne.n 8002954 8002950: 2301 movs r3, #1 8002952: e000 b.n 8002956 8002954: 2300 movs r3, #0 } 8002956: 0018 movs r0, r3 8002958: 46bd mov sp, r7 800295a: b002 add sp, #8 800295c: bd80 pop {r7, pc} ... 08002960 : * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) { 8002960: b590 push {r4, r7, lr} 8002962: b08b sub sp, #44 @ 0x2c 8002964: af00 add r7, sp, #0 8002966: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 8002968: 2300 movs r3, #0 800296a: 60fb str r3, [r7, #12] uint32_t backup_setting_cfgr1; uint32_t calibration_index; uint32_t calibration_factor_accumulated = 0; 800296c: 2300 movs r3, #0 800296e: 623b str r3, [r7, #32] __IO uint32_t delay_cpu_cycles; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); __HAL_LOCK(hadc); 8002970: 687b ldr r3, [r7, #4] 8002972: 2254 movs r2, #84 @ 0x54 8002974: 5c9b ldrb r3, [r3, r2] 8002976: 2b01 cmp r3, #1 8002978: d101 bne.n 800297e 800297a: 2302 movs r3, #2 800297c: e0dd b.n 8002b3a 800297e: 687b ldr r3, [r7, #4] 8002980: 2254 movs r2, #84 @ 0x54 8002982: 2101 movs r1, #1 8002984: 5499 strb r1, [r3, r2] /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 8002986: 231f movs r3, #31 8002988: 18fc adds r4, r7, r3 800298a: 687b ldr r3, [r7, #4] 800298c: 0018 movs r0, r3 800298e: f7ff fe63 bl 8002658 8002992: 0003 movs r3, r0 8002994: 7023 strb r3, [r4, #0] /* Check if ADC is effectively disabled */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8002996: 687b ldr r3, [r7, #4] 8002998: 681b ldr r3, [r3, #0] 800299a: 0018 movs r0, r3 800299c: f7ff ffa6 bl 80028ec 80029a0: 1e03 subs r3, r0, #0 80029a2: d000 beq.n 80029a6 80029a4: e0bc b.n 8002b20 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80029a6: 687b ldr r3, [r7, #4] 80029a8: 6d9b ldr r3, [r3, #88] @ 0x58 80029aa: 4a66 ldr r2, [pc, #408] @ (8002b44 ) 80029ac: 4013 ands r3, r2 80029ae: 2202 movs r2, #2 80029b0: 431a orrs r2, r3 80029b2: 687b ldr r3, [r7, #4] 80029b4: 659a str r2, [r3, #88] @ 0x58 /* Note: Specificity of this STM32 series: Calibration factor is */ /* available in data register and also transferred by DMA. */ /* To not insert ADC calibration factor among ADC conversion data */ /* in array variable, DMA transfer must be disabled during */ /* calibration. */ backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF); 80029b6: 687b ldr r3, [r7, #4] 80029b8: 681b ldr r3, [r3, #0] 80029ba: 68db ldr r3, [r3, #12] 80029bc: 4a62 ldr r2, [pc, #392] @ (8002b48 ) 80029be: 4013 ands r3, r2 80029c0: 61bb str r3, [r7, #24] CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF); 80029c2: 687b ldr r3, [r7, #4] 80029c4: 681b ldr r3, [r3, #0] 80029c6: 68da ldr r2, [r3, #12] 80029c8: 687b ldr r3, [r7, #4] 80029ca: 681b ldr r3, [r3, #0] 80029cc: 495f ldr r1, [pc, #380] @ (8002b4c ) 80029ce: 400a ands r2, r1 80029d0: 60da str r2, [r3, #12] /* ADC calibration procedure */ /* Note: Perform an averaging of 8 calibrations for optimized accuracy */ for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++) 80029d2: 2300 movs r3, #0 80029d4: 627b str r3, [r7, #36] @ 0x24 80029d6: e02d b.n 8002a34 { /* Start ADC calibration */ LL_ADC_StartCalibration(hadc->Instance); 80029d8: 687b ldr r3, [r7, #4] 80029da: 681b ldr r3, [r3, #0] 80029dc: 0018 movs r0, r3 80029de: f7ff ff97 bl 8002910 /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 80029e2: e014 b.n 8002a0e { wait_loop_index++; 80029e4: 68fb ldr r3, [r7, #12] 80029e6: 3301 adds r3, #1 80029e8: 60fb str r3, [r7, #12] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 80029ea: 68fb ldr r3, [r7, #12] 80029ec: 4a58 ldr r2, [pc, #352] @ (8002b50 ) 80029ee: 4293 cmp r3, r2 80029f0: d90d bls.n 8002a0e { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80029f2: 687b ldr r3, [r7, #4] 80029f4: 6d9b ldr r3, [r3, #88] @ 0x58 80029f6: 2212 movs r2, #18 80029f8: 4393 bics r3, r2 80029fa: 2210 movs r2, #16 80029fc: 431a orrs r2, r3 80029fe: 687b ldr r3, [r7, #4] 8002a00: 659a str r2, [r3, #88] @ 0x58 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); __HAL_UNLOCK(hadc); 8002a02: 687b ldr r3, [r7, #4] 8002a04: 2254 movs r2, #84 @ 0x54 8002a06: 2100 movs r1, #0 8002a08: 5499 strb r1, [r3, r2] return HAL_ERROR; 8002a0a: 2301 movs r3, #1 8002a0c: e095 b.n 8002b3a while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8002a0e: 687b ldr r3, [r7, #4] 8002a10: 681b ldr r3, [r3, #0] 8002a12: 0018 movs r0, r3 8002a14: f7ff ff90 bl 8002938 8002a18: 1e03 subs r3, r0, #0 8002a1a: d1e3 bne.n 80029e4 } } calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance); 8002a1c: 687b ldr r3, [r7, #4] 8002a1e: 681b ldr r3, [r3, #0] 8002a20: 0018 movs r0, r3 8002a22: f7ff ff32 bl 800288a 8002a26: 0002 movs r2, r0 8002a28: 6a3b ldr r3, [r7, #32] 8002a2a: 189b adds r3, r3, r2 8002a2c: 623b str r3, [r7, #32] for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++) 8002a2e: 6a7b ldr r3, [r7, #36] @ 0x24 8002a30: 3301 adds r3, #1 8002a32: 627b str r3, [r7, #36] @ 0x24 8002a34: 6a7b ldr r3, [r7, #36] @ 0x24 8002a36: 2b07 cmp r3, #7 8002a38: d9ce bls.n 80029d8 } /* Compute average */ calibration_factor_accumulated /= calibration_index; 8002a3a: 6a79 ldr r1, [r7, #36] @ 0x24 8002a3c: 6a38 ldr r0, [r7, #32] 8002a3e: f7fd fb5f bl 8000100 <__udivsi3> 8002a42: 0003 movs r3, r0 8002a44: 623b str r3, [r7, #32] /* Apply calibration factor (requires ADC enable and disable process) */ LL_ADC_Enable(hadc->Instance); 8002a46: 687b ldr r3, [r7, #4] 8002a48: 681b ldr r3, [r3, #0] 8002a4a: 0018 movs r0, r3 8002a4c: f7ff ff2a bl 80028a4 /* Case of ADC clocked at low frequency: Delay required between ADC enable and disable actions */ if (LL_ADC_GetClock(hadc->Instance) == LL_ADC_CLOCK_ASYNC) 8002a50: 687b ldr r3, [r7, #4] 8002a52: 681b ldr r3, [r3, #0] 8002a54: 0018 movs r0, r3 8002a56: f7ff fef8 bl 800284a 8002a5a: 1e03 subs r3, r0, #0 8002a5c: d11b bne.n 8002a96 { adc_clk_async_presc = LL_ADC_GetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8002a5e: 4b3d ldr r3, [pc, #244] @ (8002b54 ) 8002a60: 0018 movs r0, r3 8002a62: f7ff fee5 bl 8002830 8002a66: 0003 movs r3, r0 8002a68: 617b str r3, [r7, #20] if (adc_clk_async_presc >= LL_ADC_CLOCK_ASYNC_DIV16) 8002a6a: 697a ldr r2, [r7, #20] 8002a6c: 23e0 movs r3, #224 @ 0xe0 8002a6e: 035b lsls r3, r3, #13 8002a70: 429a cmp r2, r3 8002a72: d310 bcc.n 8002a96 { /* Delay loop initialization and execution */ /* Delay depends on ADC clock prescaler: Compute ADC clock asynchronous prescaler to decimal format */ delay_cpu_cycles = (1UL << ((adc_clk_async_presc >> ADC_CCR_PRESC_Pos) - 3UL)); 8002a74: 697b ldr r3, [r7, #20] 8002a76: 0c9b lsrs r3, r3, #18 8002a78: 3b03 subs r3, #3 8002a7a: 2201 movs r2, #1 8002a7c: 409a lsls r2, r3 8002a7e: 0013 movs r3, r2 8002a80: 60bb str r3, [r7, #8] /* Divide variable by 2 to compensate partially CPU processing cycles */ delay_cpu_cycles >>= 1UL; 8002a82: 68bb ldr r3, [r7, #8] 8002a84: 085b lsrs r3, r3, #1 8002a86: 60bb str r3, [r7, #8] while (delay_cpu_cycles != 0UL) 8002a88: e002 b.n 8002a90 { delay_cpu_cycles--; 8002a8a: 68bb ldr r3, [r7, #8] 8002a8c: 3b01 subs r3, #1 8002a8e: 60bb str r3, [r7, #8] while (delay_cpu_cycles != 0UL) 8002a90: 68bb ldr r3, [r7, #8] 8002a92: 2b00 cmp r3, #0 8002a94: d1f9 bne.n 8002a8a } } } LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated); 8002a96: 687b ldr r3, [r7, #4] 8002a98: 681b ldr r3, [r3, #0] 8002a9a: 6a3a ldr r2, [r7, #32] 8002a9c: 0011 movs r1, r2 8002a9e: 0018 movs r0, r3 8002aa0: f7ff fedf bl 8002862 LL_ADC_Disable(hadc->Instance); 8002aa4: 687b ldr r3, [r7, #4] 8002aa6: 681b ldr r3, [r3, #0] 8002aa8: 0018 movs r0, r3 8002aaa: f7ff ff0d bl 80028c8 /* Wait for ADC effectively disabled before changing configuration */ /* Get tick count */ tickstart = HAL_GetTick(); 8002aae: f7fe fedb bl 8001868 8002ab2: 0003 movs r3, r0 8002ab4: 613b str r3, [r7, #16] while (LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8002ab6: e01b b.n 8002af0 { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8002ab8: f7fe fed6 bl 8001868 8002abc: 0002 movs r2, r0 8002abe: 693b ldr r3, [r7, #16] 8002ac0: 1ad3 subs r3, r2, r3 8002ac2: 2b02 cmp r3, #2 8002ac4: d914 bls.n 8002af0 { /* New check to avoid false timeout detection in case of preemption */ if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8002ac6: 687b ldr r3, [r7, #4] 8002ac8: 681b ldr r3, [r3, #0] 8002aca: 0018 movs r0, r3 8002acc: f7ff ff0e bl 80028ec 8002ad0: 1e03 subs r3, r0, #0 8002ad2: d00d beq.n 8002af0 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002ad4: 687b ldr r3, [r7, #4] 8002ad6: 6d9b ldr r3, [r3, #88] @ 0x58 8002ad8: 2210 movs r2, #16 8002ada: 431a orrs r2, r3 8002adc: 687b ldr r3, [r7, #4] 8002ade: 659a str r2, [r3, #88] @ 0x58 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002ae0: 687b ldr r3, [r7, #4] 8002ae2: 6ddb ldr r3, [r3, #92] @ 0x5c 8002ae4: 2201 movs r2, #1 8002ae6: 431a orrs r2, r3 8002ae8: 687b ldr r3, [r7, #4] 8002aea: 65da str r2, [r3, #92] @ 0x5c return HAL_ERROR; 8002aec: 2301 movs r3, #1 8002aee: e024 b.n 8002b3a while (LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8002af0: 687b ldr r3, [r7, #4] 8002af2: 681b ldr r3, [r3, #0] 8002af4: 0018 movs r0, r3 8002af6: f7ff fef9 bl 80028ec 8002afa: 1e03 subs r3, r0, #0 8002afc: d1dc bne.n 8002ab8 } } } /* Restore configuration after calibration */ SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1); 8002afe: 687b ldr r3, [r7, #4] 8002b00: 681b ldr r3, [r3, #0] 8002b02: 68d9 ldr r1, [r3, #12] 8002b04: 687b ldr r3, [r7, #4] 8002b06: 681b ldr r3, [r3, #0] 8002b08: 69ba ldr r2, [r7, #24] 8002b0a: 430a orrs r2, r1 8002b0c: 60da str r2, [r3, #12] /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002b0e: 687b ldr r3, [r7, #4] 8002b10: 6d9b ldr r3, [r3, #88] @ 0x58 8002b12: 2203 movs r2, #3 8002b14: 4393 bics r3, r2 8002b16: 2201 movs r2, #1 8002b18: 431a orrs r2, r3 8002b1a: 687b ldr r3, [r7, #4] 8002b1c: 659a str r2, [r3, #88] @ 0x58 8002b1e: e005 b.n 8002b2c HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002b20: 687b ldr r3, [r7, #4] 8002b22: 6d9b ldr r3, [r3, #88] @ 0x58 8002b24: 2210 movs r2, #16 8002b26: 431a orrs r2, r3 8002b28: 687b ldr r3, [r7, #4] 8002b2a: 659a str r2, [r3, #88] @ 0x58 /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } __HAL_UNLOCK(hadc); 8002b2c: 687b ldr r3, [r7, #4] 8002b2e: 2254 movs r2, #84 @ 0x54 8002b30: 2100 movs r1, #0 8002b32: 5499 strb r1, [r3, r2] return tmp_hal_status; 8002b34: 231f movs r3, #31 8002b36: 18fb adds r3, r7, r3 8002b38: 781b ldrb r3, [r3, #0] } 8002b3a: 0018 movs r0, r3 8002b3c: 46bd mov sp, r7 8002b3e: b00b add sp, #44 @ 0x2c 8002b40: bd90 pop {r4, r7, pc} 8002b42: 46c0 nop @ (mov r8, r8) 8002b44: fffffefd .word 0xfffffefd 8002b48: 00008003 .word 0x00008003 8002b4c: ffff7ffc .word 0xffff7ffc 8002b50: 0002f1ff .word 0x0002f1ff 8002b54: 40012708 .word 0x40012708 08002b58 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8002b58: b580 push {r7, lr} 8002b5a: b082 sub sp, #8 8002b5c: af00 add r7, sp, #0 8002b5e: 0002 movs r2, r0 8002b60: 1dfb adds r3, r7, #7 8002b62: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8002b64: 1dfb adds r3, r7, #7 8002b66: 781b ldrb r3, [r3, #0] 8002b68: 2b7f cmp r3, #127 @ 0x7f 8002b6a: d809 bhi.n 8002b80 <__NVIC_EnableIRQ+0x28> { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8002b6c: 1dfb adds r3, r7, #7 8002b6e: 781b ldrb r3, [r3, #0] 8002b70: 001a movs r2, r3 8002b72: 231f movs r3, #31 8002b74: 401a ands r2, r3 8002b76: 4b04 ldr r3, [pc, #16] @ (8002b88 <__NVIC_EnableIRQ+0x30>) 8002b78: 2101 movs r1, #1 8002b7a: 4091 lsls r1, r2 8002b7c: 000a movs r2, r1 8002b7e: 601a str r2, [r3, #0] __COMPILER_BARRIER(); } } 8002b80: 46c0 nop @ (mov r8, r8) 8002b82: 46bd mov sp, r7 8002b84: b002 add sp, #8 8002b86: bd80 pop {r7, pc} 8002b88: e000e100 .word 0xe000e100 08002b8c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8002b8c: b590 push {r4, r7, lr} 8002b8e: b083 sub sp, #12 8002b90: af00 add r7, sp, #0 8002b92: 0002 movs r2, r0 8002b94: 6039 str r1, [r7, #0] 8002b96: 1dfb adds r3, r7, #7 8002b98: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8002b9a: 1dfb adds r3, r7, #7 8002b9c: 781b ldrb r3, [r3, #0] 8002b9e: 2b7f cmp r3, #127 @ 0x7f 8002ba0: d828 bhi.n 8002bf4 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8002ba2: 4a2f ldr r2, [pc, #188] @ (8002c60 <__NVIC_SetPriority+0xd4>) 8002ba4: 1dfb adds r3, r7, #7 8002ba6: 781b ldrb r3, [r3, #0] 8002ba8: b25b sxtb r3, r3 8002baa: 089b lsrs r3, r3, #2 8002bac: 33c0 adds r3, #192 @ 0xc0 8002bae: 009b lsls r3, r3, #2 8002bb0: 589b ldr r3, [r3, r2] 8002bb2: 1dfa adds r2, r7, #7 8002bb4: 7812 ldrb r2, [r2, #0] 8002bb6: 0011 movs r1, r2 8002bb8: 2203 movs r2, #3 8002bba: 400a ands r2, r1 8002bbc: 00d2 lsls r2, r2, #3 8002bbe: 21ff movs r1, #255 @ 0xff 8002bc0: 4091 lsls r1, r2 8002bc2: 000a movs r2, r1 8002bc4: 43d2 mvns r2, r2 8002bc6: 401a ands r2, r3 8002bc8: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8002bca: 683b ldr r3, [r7, #0] 8002bcc: 019b lsls r3, r3, #6 8002bce: 22ff movs r2, #255 @ 0xff 8002bd0: 401a ands r2, r3 8002bd2: 1dfb adds r3, r7, #7 8002bd4: 781b ldrb r3, [r3, #0] 8002bd6: 0018 movs r0, r3 8002bd8: 2303 movs r3, #3 8002bda: 4003 ands r3, r0 8002bdc: 00db lsls r3, r3, #3 8002bde: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8002be0: 481f ldr r0, [pc, #124] @ (8002c60 <__NVIC_SetPriority+0xd4>) 8002be2: 1dfb adds r3, r7, #7 8002be4: 781b ldrb r3, [r3, #0] 8002be6: b25b sxtb r3, r3 8002be8: 089b lsrs r3, r3, #2 8002bea: 430a orrs r2, r1 8002bec: 33c0 adds r3, #192 @ 0xc0 8002bee: 009b lsls r3, r3, #2 8002bf0: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 8002bf2: e031 b.n 8002c58 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8002bf4: 4a1b ldr r2, [pc, #108] @ (8002c64 <__NVIC_SetPriority+0xd8>) 8002bf6: 1dfb adds r3, r7, #7 8002bf8: 781b ldrb r3, [r3, #0] 8002bfa: 0019 movs r1, r3 8002bfc: 230f movs r3, #15 8002bfe: 400b ands r3, r1 8002c00: 3b08 subs r3, #8 8002c02: 089b lsrs r3, r3, #2 8002c04: 3306 adds r3, #6 8002c06: 009b lsls r3, r3, #2 8002c08: 18d3 adds r3, r2, r3 8002c0a: 3304 adds r3, #4 8002c0c: 681b ldr r3, [r3, #0] 8002c0e: 1dfa adds r2, r7, #7 8002c10: 7812 ldrb r2, [r2, #0] 8002c12: 0011 movs r1, r2 8002c14: 2203 movs r2, #3 8002c16: 400a ands r2, r1 8002c18: 00d2 lsls r2, r2, #3 8002c1a: 21ff movs r1, #255 @ 0xff 8002c1c: 4091 lsls r1, r2 8002c1e: 000a movs r2, r1 8002c20: 43d2 mvns r2, r2 8002c22: 401a ands r2, r3 8002c24: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8002c26: 683b ldr r3, [r7, #0] 8002c28: 019b lsls r3, r3, #6 8002c2a: 22ff movs r2, #255 @ 0xff 8002c2c: 401a ands r2, r3 8002c2e: 1dfb adds r3, r7, #7 8002c30: 781b ldrb r3, [r3, #0] 8002c32: 0018 movs r0, r3 8002c34: 2303 movs r3, #3 8002c36: 4003 ands r3, r0 8002c38: 00db lsls r3, r3, #3 8002c3a: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8002c3c: 4809 ldr r0, [pc, #36] @ (8002c64 <__NVIC_SetPriority+0xd8>) 8002c3e: 1dfb adds r3, r7, #7 8002c40: 781b ldrb r3, [r3, #0] 8002c42: 001c movs r4, r3 8002c44: 230f movs r3, #15 8002c46: 4023 ands r3, r4 8002c48: 3b08 subs r3, #8 8002c4a: 089b lsrs r3, r3, #2 8002c4c: 430a orrs r2, r1 8002c4e: 3306 adds r3, #6 8002c50: 009b lsls r3, r3, #2 8002c52: 18c3 adds r3, r0, r3 8002c54: 3304 adds r3, #4 8002c56: 601a str r2, [r3, #0] } 8002c58: 46c0 nop @ (mov r8, r8) 8002c5a: 46bd mov sp, r7 8002c5c: b003 add sp, #12 8002c5e: bd90 pop {r4, r7, pc} 8002c60: e000e100 .word 0xe000e100 8002c64: e000ed00 .word 0xe000ed00 08002c68 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8002c68: b580 push {r7, lr} 8002c6a: b082 sub sp, #8 8002c6c: af00 add r7, sp, #0 8002c6e: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8002c70: 687b ldr r3, [r7, #4] 8002c72: 1e5a subs r2, r3, #1 8002c74: 2380 movs r3, #128 @ 0x80 8002c76: 045b lsls r3, r3, #17 8002c78: 429a cmp r2, r3 8002c7a: d301 bcc.n 8002c80 { return (1UL); /* Reload value impossible */ 8002c7c: 2301 movs r3, #1 8002c7e: e010 b.n 8002ca2 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8002c80: 4b0a ldr r3, [pc, #40] @ (8002cac ) 8002c82: 687a ldr r2, [r7, #4] 8002c84: 3a01 subs r2, #1 8002c86: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8002c88: 2301 movs r3, #1 8002c8a: 425b negs r3, r3 8002c8c: 2103 movs r1, #3 8002c8e: 0018 movs r0, r3 8002c90: f7ff ff7c bl 8002b8c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8002c94: 4b05 ldr r3, [pc, #20] @ (8002cac ) 8002c96: 2200 movs r2, #0 8002c98: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8002c9a: 4b04 ldr r3, [pc, #16] @ (8002cac ) 8002c9c: 2207 movs r2, #7 8002c9e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8002ca0: 2300 movs r3, #0 } 8002ca2: 0018 movs r0, r3 8002ca4: 46bd mov sp, r7 8002ca6: b002 add sp, #8 8002ca8: bd80 pop {r7, pc} 8002caa: 46c0 nop @ (mov r8, r8) 8002cac: e000e010 .word 0xe000e010 08002cb0 : * with stm32g0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0+ based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8002cb0: b580 push {r7, lr} 8002cb2: b084 sub sp, #16 8002cb4: af00 add r7, sp, #0 8002cb6: 60b9 str r1, [r7, #8] 8002cb8: 607a str r2, [r7, #4] 8002cba: 210f movs r1, #15 8002cbc: 187b adds r3, r7, r1 8002cbe: 1c02 adds r2, r0, #0 8002cc0: 701a strb r2, [r3, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(SubPriority); /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn, PreemptPriority); 8002cc2: 68ba ldr r2, [r7, #8] 8002cc4: 187b adds r3, r7, r1 8002cc6: 781b ldrb r3, [r3, #0] 8002cc8: b25b sxtb r3, r3 8002cca: 0011 movs r1, r2 8002ccc: 0018 movs r0, r3 8002cce: f7ff ff5d bl 8002b8c <__NVIC_SetPriority> } 8002cd2: 46c0 nop @ (mov r8, r8) 8002cd4: 46bd mov sp, r7 8002cd6: b004 add sp, #16 8002cd8: bd80 pop {r7, pc} 08002cda : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002cda: b580 push {r7, lr} 8002cdc: b082 sub sp, #8 8002cde: af00 add r7, sp, #0 8002ce0: 0002 movs r2, r0 8002ce2: 1dfb adds r3, r7, #7 8002ce4: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8002ce6: 1dfb adds r3, r7, #7 8002ce8: 781b ldrb r3, [r3, #0] 8002cea: b25b sxtb r3, r3 8002cec: 0018 movs r0, r3 8002cee: f7ff ff33 bl 8002b58 <__NVIC_EnableIRQ> } 8002cf2: 46c0 nop @ (mov r8, r8) 8002cf4: 46bd mov sp, r7 8002cf6: b002 add sp, #8 8002cf8: bd80 pop {r7, pc} 08002cfa : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8002cfa: b580 push {r7, lr} 8002cfc: b082 sub sp, #8 8002cfe: af00 add r7, sp, #0 8002d00: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8002d02: 687b ldr r3, [r7, #4] 8002d04: 0018 movs r0, r3 8002d06: f7ff ffaf bl 8002c68 8002d0a: 0003 movs r3, r0 } 8002d0c: 0018 movs r0, r3 8002d0e: 46bd mov sp, r7 8002d10: b002 add sp, #8 8002d12: bd80 pop {r7, pc} 08002d14 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8002d14: b580 push {r7, lr} 8002d16: b082 sub sp, #8 8002d18: af00 add r7, sp, #0 8002d1a: 6078 str r0, [r7, #4] /* Check the DMA handle allocation */ if (hdma == NULL) 8002d1c: 687b ldr r3, [r7, #4] 8002d1e: 2b00 cmp r3, #0 8002d20: d101 bne.n 8002d26 { return HAL_ERROR; 8002d22: 2301 movs r3, #1 8002d24: e077 b.n 8002e16 /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; hdma->DmaBaseAddress = DMA2; } #else hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 8002d26: 687b ldr r3, [r7, #4] 8002d28: 681b ldr r3, [r3, #0] 8002d2a: 4a3d ldr r2, [pc, #244] @ (8002e20 ) 8002d2c: 4694 mov ip, r2 8002d2e: 4463 add r3, ip 8002d30: 2114 movs r1, #20 8002d32: 0018 movs r0, r3 8002d34: f7fd f9e4 bl 8000100 <__udivsi3> 8002d38: 0003 movs r3, r0 8002d3a: 009a lsls r2, r3, #2 8002d3c: 687b ldr r3, [r7, #4] 8002d3e: 641a str r2, [r3, #64] @ 0x40 #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002d40: 687b ldr r3, [r7, #4] 8002d42: 2225 movs r2, #37 @ 0x25 8002d44: 2102 movs r1, #2 8002d46: 5499 strb r1, [r3, r2] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 8002d48: 687b ldr r3, [r7, #4] 8002d4a: 681b ldr r3, [r3, #0] 8002d4c: 681a ldr r2, [r3, #0] 8002d4e: 687b ldr r3, [r7, #4] 8002d50: 681b ldr r3, [r3, #0] 8002d52: 4934 ldr r1, [pc, #208] @ (8002e24 ) 8002d54: 400a ands r2, r1 8002d56: 601a str r2, [r3, #0] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Set the DMA Channel configuration */ SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ 8002d58: 687b ldr r3, [r7, #4] 8002d5a: 681b ldr r3, [r3, #0] 8002d5c: 6819 ldr r1, [r3, #0] 8002d5e: 687b ldr r3, [r7, #4] 8002d60: 689a ldr r2, [r3, #8] 8002d62: 687b ldr r3, [r7, #4] 8002d64: 68db ldr r3, [r3, #12] 8002d66: 431a orrs r2, r3 8002d68: 687b ldr r3, [r7, #4] 8002d6a: 691b ldr r3, [r3, #16] 8002d6c: 431a orrs r2, r3 8002d6e: 687b ldr r3, [r7, #4] 8002d70: 695b ldr r3, [r3, #20] 8002d72: 431a orrs r2, r3 8002d74: 687b ldr r3, [r7, #4] 8002d76: 699b ldr r3, [r3, #24] 8002d78: 431a orrs r2, r3 8002d7a: 687b ldr r3, [r7, #4] 8002d7c: 69db ldr r3, [r3, #28] 8002d7e: 431a orrs r2, r3 8002d80: 687b ldr r3, [r7, #4] 8002d82: 6a1b ldr r3, [r3, #32] 8002d84: 431a orrs r2, r3 8002d86: 687b ldr r3, [r7, #4] 8002d88: 681b ldr r3, [r3, #0] 8002d8a: 430a orrs r2, r1 8002d8c: 601a str r2, [r3, #0] hdma->Init.Mode | hdma->Init.Priority)); /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8002d8e: 687b ldr r3, [r7, #4] 8002d90: 0018 movs r0, r3 8002d92: f000 fa2d bl 80031f0 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8002d96: 687b ldr r3, [r7, #4] 8002d98: 689a ldr r2, [r3, #8] 8002d9a: 2380 movs r3, #128 @ 0x80 8002d9c: 01db lsls r3, r3, #7 8002d9e: 429a cmp r2, r3 8002da0: d102 bne.n 8002da8 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8002da2: 687b ldr r3, [r7, #4] 8002da4: 2200 movs r2, #0 8002da6: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8002da8: 687b ldr r3, [r7, #4] 8002daa: 685a ldr r2, [r3, #4] 8002dac: 687b ldr r3, [r7, #4] 8002dae: 6c5b ldr r3, [r3, #68] @ 0x44 8002db0: 213f movs r1, #63 @ 0x3f 8002db2: 400a ands r2, r1 8002db4: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8002db6: 687b ldr r3, [r7, #4] 8002db8: 6c9b ldr r3, [r3, #72] @ 0x48 8002dba: 687a ldr r2, [r7, #4] 8002dbc: 6cd2 ldr r2, [r2, #76] @ 0x4c 8002dbe: 605a str r2, [r3, #4] if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 8002dc0: 687b ldr r3, [r7, #4] 8002dc2: 685b ldr r3, [r3, #4] 8002dc4: 2b00 cmp r3, #0 8002dc6: d011 beq.n 8002dec 8002dc8: 687b ldr r3, [r7, #4] 8002dca: 685b ldr r3, [r3, #4] 8002dcc: 2b04 cmp r3, #4 8002dce: d80d bhi.n 8002dec { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8002dd0: 687b ldr r3, [r7, #4] 8002dd2: 0018 movs r0, r3 8002dd4: f000 fa38 bl 8003248 /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; 8002dd8: 687b ldr r3, [r7, #4] 8002dda: 6d1b ldr r3, [r3, #80] @ 0x50 8002ddc: 2200 movs r2, #0 8002dde: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8002de0: 687b ldr r3, [r7, #4] 8002de2: 6d5b ldr r3, [r3, #84] @ 0x54 8002de4: 687a ldr r2, [r7, #4] 8002de6: 6d92 ldr r2, [r2, #88] @ 0x58 8002de8: 605a str r2, [r3, #4] 8002dea: e008 b.n 8002dfe } else { hdma->DMAmuxRequestGen = 0U; 8002dec: 687b ldr r3, [r7, #4] 8002dee: 2200 movs r2, #0 8002df0: 651a str r2, [r3, #80] @ 0x50 hdma->DMAmuxRequestGenStatus = 0U; 8002df2: 687b ldr r3, [r7, #4] 8002df4: 2200 movs r2, #0 8002df6: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatusMask = 0U; 8002df8: 687b ldr r3, [r7, #4] 8002dfa: 2200 movs r2, #0 8002dfc: 659a str r2, [r3, #88] @ 0x58 } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002dfe: 687b ldr r3, [r7, #4] 8002e00: 2200 movs r2, #0 8002e02: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8002e04: 687b ldr r3, [r7, #4] 8002e06: 2225 movs r2, #37 @ 0x25 8002e08: 2101 movs r1, #1 8002e0a: 5499 strb r1, [r3, r2] /* Release Lock */ __HAL_UNLOCK(hdma); 8002e0c: 687b ldr r3, [r7, #4] 8002e0e: 2224 movs r2, #36 @ 0x24 8002e10: 2100 movs r1, #0 8002e12: 5499 strb r1, [r3, r2] return HAL_OK; 8002e14: 2300 movs r3, #0 } 8002e16: 0018 movs r0, r3 8002e18: 46bd mov sp, r7 8002e1a: b002 add sp, #8 8002e1c: bd80 pop {r7, pc} 8002e1e: 46c0 nop @ (mov r8, r8) 8002e20: bffdfff8 .word 0xbffdfff8 8002e24: ffff800f .word 0xffff800f 08002e28 : * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002e28: b580 push {r7, lr} 8002e2a: b086 sub sp, #24 8002e2c: af00 add r7, sp, #0 8002e2e: 60f8 str r0, [r7, #12] 8002e30: 60b9 str r1, [r7, #8] 8002e32: 607a str r2, [r7, #4] 8002e34: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8002e36: 2317 movs r3, #23 8002e38: 18fb adds r3, r7, r3 8002e3a: 2200 movs r2, #0 8002e3c: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8002e3e: 68fb ldr r3, [r7, #12] 8002e40: 2224 movs r2, #36 @ 0x24 8002e42: 5c9b ldrb r3, [r3, r2] 8002e44: 2b01 cmp r3, #1 8002e46: d101 bne.n 8002e4c 8002e48: 2302 movs r3, #2 8002e4a: e06f b.n 8002f2c 8002e4c: 68fb ldr r3, [r7, #12] 8002e4e: 2224 movs r2, #36 @ 0x24 8002e50: 2101 movs r1, #1 8002e52: 5499 strb r1, [r3, r2] if (hdma->State == HAL_DMA_STATE_READY) 8002e54: 68fb ldr r3, [r7, #12] 8002e56: 2225 movs r2, #37 @ 0x25 8002e58: 5c9b ldrb r3, [r3, r2] 8002e5a: b2db uxtb r3, r3 8002e5c: 2b01 cmp r3, #1 8002e5e: d157 bne.n 8002f10 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002e60: 68fb ldr r3, [r7, #12] 8002e62: 2225 movs r2, #37 @ 0x25 8002e64: 2102 movs r1, #2 8002e66: 5499 strb r1, [r3, r2] hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002e68: 68fb ldr r3, [r7, #12] 8002e6a: 2200 movs r2, #0 8002e6c: 63da str r2, [r3, #60] @ 0x3c /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8002e6e: 68fb ldr r3, [r7, #12] 8002e70: 681b ldr r3, [r3, #0] 8002e72: 681a ldr r2, [r3, #0] 8002e74: 68fb ldr r3, [r7, #12] 8002e76: 681b ldr r3, [r3, #0] 8002e78: 2101 movs r1, #1 8002e7a: 438a bics r2, r1 8002e7c: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8002e7e: 683b ldr r3, [r7, #0] 8002e80: 687a ldr r2, [r7, #4] 8002e82: 68b9 ldr r1, [r7, #8] 8002e84: 68f8 ldr r0, [r7, #12] 8002e86: f000 f973 bl 8003170 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) 8002e8a: 68fb ldr r3, [r7, #12] 8002e8c: 6b1b ldr r3, [r3, #48] @ 0x30 8002e8e: 2b00 cmp r3, #0 8002e90: d008 beq.n 8002ea4 { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002e92: 68fb ldr r3, [r7, #12] 8002e94: 681b ldr r3, [r3, #0] 8002e96: 681a ldr r2, [r3, #0] 8002e98: 68fb ldr r3, [r7, #12] 8002e9a: 681b ldr r3, [r3, #0] 8002e9c: 210e movs r1, #14 8002e9e: 430a orrs r2, r1 8002ea0: 601a str r2, [r3, #0] 8002ea2: e00f b.n 8002ec4 } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8002ea4: 68fb ldr r3, [r7, #12] 8002ea6: 681b ldr r3, [r3, #0] 8002ea8: 681a ldr r2, [r3, #0] 8002eaa: 68fb ldr r3, [r7, #12] 8002eac: 681b ldr r3, [r3, #0] 8002eae: 2104 movs r1, #4 8002eb0: 438a bics r2, r1 8002eb2: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 8002eb4: 68fb ldr r3, [r7, #12] 8002eb6: 681b ldr r3, [r3, #0] 8002eb8: 681a ldr r2, [r3, #0] 8002eba: 68fb ldr r3, [r7, #12] 8002ebc: 681b ldr r3, [r3, #0] 8002ebe: 210a movs r1, #10 8002ec0: 430a orrs r2, r1 8002ec2: 601a str r2, [r3, #0] } /* Check if DMAMUX Synchronization is enabled*/ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8002ec4: 68fb ldr r3, [r7, #12] 8002ec6: 6c5b ldr r3, [r3, #68] @ 0x44 8002ec8: 681a ldr r2, [r3, #0] 8002eca: 2380 movs r3, #128 @ 0x80 8002ecc: 025b lsls r3, r3, #9 8002ece: 4013 ands r3, r2 8002ed0: d008 beq.n 8002ee4 { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8002ed2: 68fb ldr r3, [r7, #12] 8002ed4: 6c5b ldr r3, [r3, #68] @ 0x44 8002ed6: 681a ldr r2, [r3, #0] 8002ed8: 68fb ldr r3, [r7, #12] 8002eda: 6c5b ldr r3, [r3, #68] @ 0x44 8002edc: 2180 movs r1, #128 @ 0x80 8002ede: 0049 lsls r1, r1, #1 8002ee0: 430a orrs r2, r1 8002ee2: 601a str r2, [r3, #0] } if (hdma->DMAmuxRequestGen != 0U) 8002ee4: 68fb ldr r3, [r7, #12] 8002ee6: 6d1b ldr r3, [r3, #80] @ 0x50 8002ee8: 2b00 cmp r3, #0 8002eea: d008 beq.n 8002efe { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8002eec: 68fb ldr r3, [r7, #12] 8002eee: 6d1b ldr r3, [r3, #80] @ 0x50 8002ef0: 681a ldr r2, [r3, #0] 8002ef2: 68fb ldr r3, [r7, #12] 8002ef4: 6d1b ldr r3, [r3, #80] @ 0x50 8002ef6: 2180 movs r1, #128 @ 0x80 8002ef8: 0049 lsls r1, r1, #1 8002efa: 430a orrs r2, r1 8002efc: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8002efe: 68fb ldr r3, [r7, #12] 8002f00: 681b ldr r3, [r3, #0] 8002f02: 681a ldr r2, [r3, #0] 8002f04: 68fb ldr r3, [r7, #12] 8002f06: 681b ldr r3, [r3, #0] 8002f08: 2101 movs r1, #1 8002f0a: 430a orrs r2, r1 8002f0c: 601a str r2, [r3, #0] 8002f0e: e00a b.n 8002f26 } else { /* Change the error code */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8002f10: 68fb ldr r3, [r7, #12] 8002f12: 2280 movs r2, #128 @ 0x80 8002f14: 63da str r2, [r3, #60] @ 0x3c /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002f16: 68fb ldr r3, [r7, #12] 8002f18: 2224 movs r2, #36 @ 0x24 8002f1a: 2100 movs r1, #0 8002f1c: 5499 strb r1, [r3, r2] /* Return error status */ status = HAL_ERROR; 8002f1e: 2317 movs r3, #23 8002f20: 18fb adds r3, r7, r3 8002f22: 2201 movs r2, #1 8002f24: 701a strb r2, [r3, #0] } return status; 8002f26: 2317 movs r3, #23 8002f28: 18fb adds r3, r7, r3 8002f2a: 781b ldrb r3, [r3, #0] } 8002f2c: 0018 movs r0, r3 8002f2e: 46bd mov sp, r7 8002f30: b006 add sp, #24 8002f32: bd80 pop {r7, pc} 08002f34 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8002f34: b580 push {r7, lr} 8002f36: b082 sub sp, #8 8002f38: af00 add r7, sp, #0 8002f3a: 6078 str r0, [r7, #4] /* Check the DMA peripheral handle */ if (NULL == hdma) 8002f3c: 687b ldr r3, [r7, #4] 8002f3e: 2b00 cmp r3, #0 8002f40: d101 bne.n 8002f46 { return HAL_ERROR; 8002f42: 2301 movs r3, #1 8002f44: e050 b.n 8002fe8 } /* Check the DMA peripheral state */ if (hdma->State != HAL_DMA_STATE_BUSY) 8002f46: 687b ldr r3, [r7, #4] 8002f48: 2225 movs r2, #37 @ 0x25 8002f4a: 5c9b ldrb r3, [r3, r2] 8002f4c: b2db uxtb r3, r3 8002f4e: 2b02 cmp r3, #2 8002f50: d008 beq.n 8002f64 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002f52: 687b ldr r3, [r7, #4] 8002f54: 2204 movs r2, #4 8002f56: 63da str r2, [r3, #60] @ 0x3c /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002f58: 687b ldr r3, [r7, #4] 8002f5a: 2224 movs r2, #36 @ 0x24 8002f5c: 2100 movs r1, #0 8002f5e: 5499 strb r1, [r3, r2] return HAL_ERROR; 8002f60: 2301 movs r3, #1 8002f62: e041 b.n 8002fe8 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002f64: 687b ldr r3, [r7, #4] 8002f66: 681b ldr r3, [r3, #0] 8002f68: 681a ldr r2, [r3, #0] 8002f6a: 687b ldr r3, [r7, #4] 8002f6c: 681b ldr r3, [r3, #0] 8002f6e: 210e movs r1, #14 8002f70: 438a bics r2, r1 8002f72: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8002f74: 687b ldr r3, [r7, #4] 8002f76: 6c5b ldr r3, [r3, #68] @ 0x44 8002f78: 681a ldr r2, [r3, #0] 8002f7a: 687b ldr r3, [r7, #4] 8002f7c: 6c5b ldr r3, [r3, #68] @ 0x44 8002f7e: 491c ldr r1, [pc, #112] @ (8002ff0 ) 8002f80: 400a ands r2, r1 8002f82: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002f84: 687b ldr r3, [r7, #4] 8002f86: 681b ldr r3, [r3, #0] 8002f88: 681a ldr r2, [r3, #0] 8002f8a: 687b ldr r3, [r7, #4] 8002f8c: 681b ldr r3, [r3, #0] 8002f8e: 2101 movs r1, #1 8002f90: 438a bics r2, r1 8002f92: 601a str r2, [r3, #0] /* Clear all flags */ #if defined(DMA2) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); 8002f94: 4b17 ldr r3, [pc, #92] @ (8002ff4 ) 8002f96: 6859 ldr r1, [r3, #4] 8002f98: 687b ldr r3, [r7, #4] 8002f9a: 6c1b ldr r3, [r3, #64] @ 0x40 8002f9c: 221c movs r2, #28 8002f9e: 4013 ands r3, r2 8002fa0: 2201 movs r2, #1 8002fa2: 409a lsls r2, r3 8002fa4: 4b13 ldr r3, [pc, #76] @ (8002ff4 ) 8002fa6: 430a orrs r2, r1 8002fa8: 605a str r2, [r3, #4] #endif /* DMA2 */ /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8002faa: 687b ldr r3, [r7, #4] 8002fac: 6c9b ldr r3, [r3, #72] @ 0x48 8002fae: 687a ldr r2, [r7, #4] 8002fb0: 6cd2 ldr r2, [r2, #76] @ 0x4c 8002fb2: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 8002fb4: 687b ldr r3, [r7, #4] 8002fb6: 6d1b ldr r3, [r3, #80] @ 0x50 8002fb8: 2b00 cmp r3, #0 8002fba: d00c beq.n 8002fd6 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8002fbc: 687b ldr r3, [r7, #4] 8002fbe: 6d1b ldr r3, [r3, #80] @ 0x50 8002fc0: 681a ldr r2, [r3, #0] 8002fc2: 687b ldr r3, [r7, #4] 8002fc4: 6d1b ldr r3, [r3, #80] @ 0x50 8002fc6: 490a ldr r1, [pc, #40] @ (8002ff0 ) 8002fc8: 400a ands r2, r1 8002fca: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8002fcc: 687b ldr r3, [r7, #4] 8002fce: 6d5b ldr r3, [r3, #84] @ 0x54 8002fd0: 687a ldr r2, [r7, #4] 8002fd2: 6d92 ldr r2, [r2, #88] @ 0x58 8002fd4: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002fd6: 687b ldr r3, [r7, #4] 8002fd8: 2225 movs r2, #37 @ 0x25 8002fda: 2101 movs r1, #1 8002fdc: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002fde: 687b ldr r3, [r7, #4] 8002fe0: 2224 movs r2, #36 @ 0x24 8002fe2: 2100 movs r1, #0 8002fe4: 5499 strb r1, [r3, r2] } return HAL_OK; 8002fe6: 2300 movs r3, #0 } 8002fe8: 0018 movs r0, r3 8002fea: 46bd mov sp, r7 8002fec: b002 add sp, #8 8002fee: bd80 pop {r7, pc} 8002ff0: fffffeff .word 0xfffffeff 8002ff4: 40020000 .word 0x40020000 08002ff8 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8002ff8: b580 push {r7, lr} 8002ffa: b084 sub sp, #16 8002ffc: af00 add r7, sp, #0 8002ffe: 6078 str r0, [r7, #4] #if defined(DMA2) uint32_t flag_it = hdma->DmaBaseAddress->ISR; #else uint32_t flag_it = DMA1->ISR; 8003000: 4b55 ldr r3, [pc, #340] @ (8003158 ) 8003002: 681b ldr r3, [r3, #0] 8003004: 60fb str r3, [r7, #12] #endif /* DMA2 */ uint32_t source_it = hdma->Instance->CCR; 8003006: 687b ldr r3, [r7, #4] 8003008: 681b ldr r3, [r3, #0] 800300a: 681b ldr r3, [r3, #0] 800300c: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) 800300e: 687b ldr r3, [r7, #4] 8003010: 6c1b ldr r3, [r3, #64] @ 0x40 8003012: 221c movs r2, #28 8003014: 4013 ands r3, r2 8003016: 2204 movs r2, #4 8003018: 409a lsls r2, r3 800301a: 0013 movs r3, r2 800301c: 68fa ldr r2, [r7, #12] 800301e: 4013 ands r3, r2 8003020: d027 beq.n 8003072 8003022: 68bb ldr r3, [r7, #8] 8003024: 2204 movs r2, #4 8003026: 4013 ands r3, r2 8003028: d023 beq.n 8003072 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 800302a: 687b ldr r3, [r7, #4] 800302c: 681b ldr r3, [r3, #0] 800302e: 681b ldr r3, [r3, #0] 8003030: 2220 movs r2, #32 8003032: 4013 ands r3, r2 8003034: d107 bne.n 8003046 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8003036: 687b ldr r3, [r7, #4] 8003038: 681b ldr r3, [r3, #0] 800303a: 681a ldr r2, [r3, #0] 800303c: 687b ldr r3, [r7, #4] 800303e: 681b ldr r3, [r3, #0] 8003040: 2104 movs r1, #4 8003042: 438a bics r2, r1 8003044: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ #if defined(DMA2) hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); #else __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); 8003046: 4b44 ldr r3, [pc, #272] @ (8003158 ) 8003048: 6859 ldr r1, [r3, #4] 800304a: 687b ldr r3, [r7, #4] 800304c: 6c1b ldr r3, [r3, #64] @ 0x40 800304e: 221c movs r2, #28 8003050: 4013 ands r3, r2 8003052: 2204 movs r2, #4 8003054: 409a lsls r2, r3 8003056: 4b40 ldr r3, [pc, #256] @ (8003158 ) 8003058: 430a orrs r2, r1 800305a: 605a str r2, [r3, #4] #endif /* DMA2 */ /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) 800305c: 687b ldr r3, [r7, #4] 800305e: 6b1b ldr r3, [r3, #48] @ 0x30 8003060: 2b00 cmp r3, #0 8003062: d100 bne.n 8003066 8003064: e073 b.n 800314e { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8003066: 687b ldr r3, [r7, #4] 8003068: 6b1b ldr r3, [r3, #48] @ 0x30 800306a: 687a ldr r2, [r7, #4] 800306c: 0010 movs r0, r2 800306e: 4798 blx r3 if (hdma->XferHalfCpltCallback != NULL) 8003070: e06d b.n 800314e } } /* Transfer Complete Interrupt management ***********************************/ else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC))) 8003072: 687b ldr r3, [r7, #4] 8003074: 6c1b ldr r3, [r3, #64] @ 0x40 8003076: 221c movs r2, #28 8003078: 4013 ands r3, r2 800307a: 2202 movs r2, #2 800307c: 409a lsls r2, r3 800307e: 0013 movs r3, r2 8003080: 68fa ldr r2, [r7, #12] 8003082: 4013 ands r3, r2 8003084: d02e beq.n 80030e4 8003086: 68bb ldr r3, [r7, #8] 8003088: 2202 movs r2, #2 800308a: 4013 ands r3, r2 800308c: d02a beq.n 80030e4 { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 800308e: 687b ldr r3, [r7, #4] 8003090: 681b ldr r3, [r3, #0] 8003092: 681b ldr r3, [r3, #0] 8003094: 2220 movs r2, #32 8003096: 4013 ands r3, r2 8003098: d10b bne.n 80030b2 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800309a: 687b ldr r3, [r7, #4] 800309c: 681b ldr r3, [r3, #0] 800309e: 681a ldr r2, [r3, #0] 80030a0: 687b ldr r3, [r7, #4] 80030a2: 681b ldr r3, [r3, #0] 80030a4: 210a movs r1, #10 80030a6: 438a bics r2, r1 80030a8: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80030aa: 687b ldr r3, [r7, #4] 80030ac: 2225 movs r2, #37 @ 0x25 80030ae: 2101 movs r1, #1 80030b0: 5499 strb r1, [r3, r2] } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); 80030b2: 4b29 ldr r3, [pc, #164] @ (8003158 ) 80030b4: 6859 ldr r1, [r3, #4] 80030b6: 687b ldr r3, [r7, #4] 80030b8: 6c1b ldr r3, [r3, #64] @ 0x40 80030ba: 221c movs r2, #28 80030bc: 4013 ands r3, r2 80030be: 2202 movs r2, #2 80030c0: 409a lsls r2, r3 80030c2: 4b25 ldr r3, [pc, #148] @ (8003158 ) 80030c4: 430a orrs r2, r1 80030c6: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 80030c8: 687b ldr r3, [r7, #4] 80030ca: 2224 movs r2, #36 @ 0x24 80030cc: 2100 movs r1, #0 80030ce: 5499 strb r1, [r3, r2] if (hdma->XferCpltCallback != NULL) 80030d0: 687b ldr r3, [r7, #4] 80030d2: 6adb ldr r3, [r3, #44] @ 0x2c 80030d4: 2b00 cmp r3, #0 80030d6: d03a beq.n 800314e { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 80030d8: 687b ldr r3, [r7, #4] 80030da: 6adb ldr r3, [r3, #44] @ 0x2c 80030dc: 687a ldr r2, [r7, #4] 80030de: 0010 movs r0, r2 80030e0: 4798 blx r3 if (hdma->XferCpltCallback != NULL) 80030e2: e034 b.n 800314e } } /* Transfer Error Interrupt management **************************************/ else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) 80030e4: 687b ldr r3, [r7, #4] 80030e6: 6c1b ldr r3, [r3, #64] @ 0x40 80030e8: 221c movs r2, #28 80030ea: 4013 ands r3, r2 80030ec: 2208 movs r2, #8 80030ee: 409a lsls r2, r3 80030f0: 0013 movs r3, r2 80030f2: 68fa ldr r2, [r7, #12] 80030f4: 4013 ands r3, r2 80030f6: d02b beq.n 8003150 80030f8: 68bb ldr r3, [r7, #8] 80030fa: 2208 movs r2, #8 80030fc: 4013 ands r3, r2 80030fe: d027 beq.n 8003150 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8003100: 687b ldr r3, [r7, #4] 8003102: 681b ldr r3, [r3, #0] 8003104: 681a ldr r2, [r3, #0] 8003106: 687b ldr r3, [r7, #4] 8003108: 681b ldr r3, [r3, #0] 800310a: 210e movs r1, #14 800310c: 438a bics r2, r1 800310e: 601a str r2, [r3, #0] /* Clear all flags */ #if defined(DMA2) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); 8003110: 4b11 ldr r3, [pc, #68] @ (8003158 ) 8003112: 6859 ldr r1, [r3, #4] 8003114: 687b ldr r3, [r7, #4] 8003116: 6c1b ldr r3, [r3, #64] @ 0x40 8003118: 221c movs r2, #28 800311a: 4013 ands r3, r2 800311c: 2201 movs r2, #1 800311e: 409a lsls r2, r3 8003120: 4b0d ldr r3, [pc, #52] @ (8003158 ) 8003122: 430a orrs r2, r1 8003124: 605a str r2, [r3, #4] #endif /* DMA2 */ /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8003126: 687b ldr r3, [r7, #4] 8003128: 2201 movs r2, #1 800312a: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800312c: 687b ldr r3, [r7, #4] 800312e: 2225 movs r2, #37 @ 0x25 8003130: 2101 movs r1, #1 8003132: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003134: 687b ldr r3, [r7, #4] 8003136: 2224 movs r2, #36 @ 0x24 8003138: 2100 movs r1, #0 800313a: 5499 strb r1, [r3, r2] if (hdma->XferErrorCallback != NULL) 800313c: 687b ldr r3, [r7, #4] 800313e: 6b5b ldr r3, [r3, #52] @ 0x34 8003140: 2b00 cmp r3, #0 8003142: d005 beq.n 8003150 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8003144: 687b ldr r3, [r7, #4] 8003146: 6b5b ldr r3, [r3, #52] @ 0x34 8003148: 687a ldr r2, [r7, #4] 800314a: 0010 movs r0, r2 800314c: 4798 blx r3 } else { /* Nothing To Do */ } return; 800314e: 46c0 nop @ (mov r8, r8) 8003150: 46c0 nop @ (mov r8, r8) } 8003152: 46bd mov sp, r7 8003154: b004 add sp, #16 8003156: bd80 pop {r7, pc} 8003158: 40020000 .word 0x40020000 0800315c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { 800315c: b580 push {r7, lr} 800315e: b082 sub sp, #8 8003160: af00 add r7, sp, #0 8003162: 6078 str r0, [r7, #4] /* Return the DMA error code */ return hdma->ErrorCode; 8003164: 687b ldr r3, [r7, #4] 8003166: 6bdb ldr r3, [r3, #60] @ 0x3c } 8003168: 0018 movs r0, r3 800316a: 46bd mov sp, r7 800316c: b002 add sp, #8 800316e: bd80 pop {r7, pc} 08003170 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8003170: b580 push {r7, lr} 8003172: b084 sub sp, #16 8003174: af00 add r7, sp, #0 8003176: 60f8 str r0, [r7, #12] 8003178: 60b9 str r1, [r7, #8] 800317a: 607a str r2, [r7, #4] 800317c: 603b str r3, [r7, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800317e: 68fb ldr r3, [r7, #12] 8003180: 6c9b ldr r3, [r3, #72] @ 0x48 8003182: 68fa ldr r2, [r7, #12] 8003184: 6cd2 ldr r2, [r2, #76] @ 0x4c 8003186: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 8003188: 68fb ldr r3, [r7, #12] 800318a: 6d1b ldr r3, [r3, #80] @ 0x50 800318c: 2b00 cmp r3, #0 800318e: d004 beq.n 800319a { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8003190: 68fb ldr r3, [r7, #12] 8003192: 6d5b ldr r3, [r3, #84] @ 0x54 8003194: 68fa ldr r2, [r7, #12] 8003196: 6d92 ldr r2, [r2, #88] @ 0x58 8003198: 605a str r2, [r3, #4] /* Clear all flags */ #if defined(DMA2) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); 800319a: 4b14 ldr r3, [pc, #80] @ (80031ec ) 800319c: 6859 ldr r1, [r3, #4] 800319e: 68fb ldr r3, [r7, #12] 80031a0: 6c1b ldr r3, [r3, #64] @ 0x40 80031a2: 221c movs r2, #28 80031a4: 4013 ands r3, r2 80031a6: 2201 movs r2, #1 80031a8: 409a lsls r2, r3 80031aa: 4b10 ldr r3, [pc, #64] @ (80031ec ) 80031ac: 430a orrs r2, r1 80031ae: 605a str r2, [r3, #4] #endif /* DMA2 */ /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 80031b0: 68fb ldr r3, [r7, #12] 80031b2: 681b ldr r3, [r3, #0] 80031b4: 683a ldr r2, [r7, #0] 80031b6: 605a str r2, [r3, #4] /* Memory to Peripheral */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 80031b8: 68fb ldr r3, [r7, #12] 80031ba: 689b ldr r3, [r3, #8] 80031bc: 2b10 cmp r3, #16 80031be: d108 bne.n 80031d2 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 80031c0: 68fb ldr r3, [r7, #12] 80031c2: 681b ldr r3, [r3, #0] 80031c4: 687a ldr r2, [r7, #4] 80031c6: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 80031c8: 68fb ldr r3, [r7, #12] 80031ca: 681b ldr r3, [r3, #0] 80031cc: 68ba ldr r2, [r7, #8] 80031ce: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 80031d0: e007 b.n 80031e2 hdma->Instance->CPAR = SrcAddress; 80031d2: 68fb ldr r3, [r7, #12] 80031d4: 681b ldr r3, [r3, #0] 80031d6: 68ba ldr r2, [r7, #8] 80031d8: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 80031da: 68fb ldr r3, [r7, #12] 80031dc: 681b ldr r3, [r3, #0] 80031de: 687a ldr r2, [r7, #4] 80031e0: 60da str r2, [r3, #12] } 80031e2: 46c0 nop @ (mov r8, r8) 80031e4: 46bd mov sp, r7 80031e6: b004 add sp, #16 80031e8: bd80 pop {r7, pc} 80031ea: 46c0 nop @ (mov r8, r8) 80031ec: 40020000 .word 0x40020000 080031f0 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 80031f0: b580 push {r7, lr} 80031f2: b084 sub sp, #16 80031f4: af00 add r7, sp, #0 80031f6: 6078 str r0, [r7, #4] /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U); } #else /* Associate a DMA Channel to a DMAMUX channel */ hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); 80031f8: 687b ldr r3, [r7, #4] 80031fa: 6c1b ldr r3, [r3, #64] @ 0x40 80031fc: 089b lsrs r3, r3, #2 80031fe: 4a10 ldr r2, [pc, #64] @ (8003240 ) 8003200: 4694 mov ip, r2 8003202: 4463 add r3, ip 8003204: 009b lsls r3, r3, #2 8003206: 001a movs r2, r3 8003208: 687b ldr r3, [r7, #4] 800320a: 645a str r2, [r3, #68] @ 0x44 /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 800320c: 687b ldr r3, [r7, #4] 800320e: 681b ldr r3, [r3, #0] 8003210: 001a movs r2, r3 8003212: 23ff movs r3, #255 @ 0xff 8003214: 4013 ands r3, r2 8003216: 3b08 subs r3, #8 8003218: 2114 movs r1, #20 800321a: 0018 movs r0, r3 800321c: f7fc ff70 bl 8000100 <__udivsi3> 8003220: 0003 movs r3, r0 8003222: 60fb str r3, [r7, #12] #endif /* DMA2 */ /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */ hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 8003224: 687b ldr r3, [r7, #4] 8003226: 4a07 ldr r2, [pc, #28] @ (8003244 ) 8003228: 649a str r2, [r3, #72] @ 0x48 /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 800322a: 68fb ldr r3, [r7, #12] 800322c: 221f movs r2, #31 800322e: 4013 ands r3, r2 8003230: 2201 movs r2, #1 8003232: 409a lsls r2, r3 8003234: 687b ldr r3, [r7, #4] 8003236: 64da str r2, [r3, #76] @ 0x4c } 8003238: 46c0 nop @ (mov r8, r8) 800323a: 46bd mov sp, r7 800323c: b004 add sp, #16 800323e: bd80 pop {r7, pc} 8003240: 10008200 .word 0x10008200 8003244: 40020880 .word 0x40020880 08003248 : * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 8003248: b580 push {r7, lr} 800324a: b084 sub sp, #16 800324c: af00 add r7, sp, #0 800324e: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 8003250: 687b ldr r3, [r7, #4] 8003252: 685b ldr r3, [r3, #4] 8003254: 223f movs r2, #63 @ 0x3f 8003256: 4013 ands r3, r2 8003258: 60fb str r3, [r7, #12] /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800325a: 68fb ldr r3, [r7, #12] 800325c: 4a0a ldr r2, [pc, #40] @ (8003288 ) 800325e: 4694 mov ip, r2 8003260: 4463 add r3, ip 8003262: 009b lsls r3, r3, #2 8003264: 001a movs r2, r3 8003266: 687b ldr r3, [r7, #4] 8003268: 651a str r2, [r3, #80] @ 0x50 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800326a: 687b ldr r3, [r7, #4] 800326c: 4a07 ldr r2, [pc, #28] @ (800328c ) 800326e: 655a str r2, [r3, #84] @ 0x54 /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); 8003270: 68fb ldr r3, [r7, #12] 8003272: 3b01 subs r3, #1 8003274: 2203 movs r2, #3 8003276: 4013 ands r3, r2 8003278: 2201 movs r2, #1 800327a: 409a lsls r2, r3 800327c: 687b ldr r3, [r7, #4] 800327e: 659a str r2, [r3, #88] @ 0x58 } 8003280: 46c0 nop @ (mov r8, r8) 8003282: 46bd mov sp, r7 8003284: b004 add sp, #16 8003286: bd80 pop {r7, pc} 8003288: 1000823f .word 0x1000823f 800328c: 40020940 .word 0x40020940 08003290 : * TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit). * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { 8003290: b5b0 push {r4, r5, r7, lr} 8003292: b086 sub sp, #24 8003294: af00 add r7, sp, #0 8003296: 60f8 str r0, [r7, #12] 8003298: 60b9 str r1, [r7, #8] 800329a: 603a str r2, [r7, #0] 800329c: 607b str r3, [r7, #4] /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); /* Process Locked */ __HAL_LOCK(&pFlash); 800329e: 4b21 ldr r3, [pc, #132] @ (8003324 ) 80032a0: 781b ldrb r3, [r3, #0] 80032a2: 2b01 cmp r3, #1 80032a4: d101 bne.n 80032aa 80032a6: 2302 movs r3, #2 80032a8: e038 b.n 800331c 80032aa: 4b1e ldr r3, [pc, #120] @ (8003324 ) 80032ac: 2201 movs r2, #1 80032ae: 701a strb r2, [r3, #0] /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 80032b0: 4b1c ldr r3, [pc, #112] @ (8003324 ) 80032b2: 2200 movs r2, #0 80032b4: 605a str r2, [r3, #4] /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 80032b6: 2517 movs r5, #23 80032b8: 197c adds r4, r7, r5 80032ba: 23fa movs r3, #250 @ 0xfa 80032bc: 009b lsls r3, r3, #2 80032be: 0018 movs r0, r3 80032c0: f000 f87a bl 80033b8 80032c4: 0003 movs r3, r0 80032c6: 7023 strb r3, [r4, #0] if (status == HAL_OK) 80032c8: 197b adds r3, r7, r5 80032ca: 781b ldrb r3, [r3, #0] 80032cc: 2b00 cmp r3, #0 80032ce: d11f bne.n 8003310 { if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) 80032d0: 68fb ldr r3, [r7, #12] 80032d2: 2b01 cmp r3, #1 80032d4: d106 bne.n 80032e4 { /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Program double-word (64-bit) at a specified address */ FLASH_Program_DoubleWord(Address, Data); 80032d6: 683a ldr r2, [r7, #0] 80032d8: 687b ldr r3, [r7, #4] 80032da: 68b9 ldr r1, [r7, #8] 80032dc: 0008 movs r0, r1 80032de: f000 f8b9 bl 8003454 80032e2: e005 b.n 80032f0 { /* Check the parameters */ assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); /* Fast program a 32 row double-word (64-bit) at a specified address */ FLASH_Program_Fast(Address, (uint32_t)Data); 80032e4: 683a ldr r2, [r7, #0] 80032e6: 68bb ldr r3, [r7, #8] 80032e8: 0011 movs r1, r2 80032ea: 0018 movs r0, r3 80032ec: f002 feb0 bl 8006050 <__FLASH_Program_Fast_veneer> } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 80032f0: 2317 movs r3, #23 80032f2: 18fc adds r4, r7, r3 80032f4: 23fa movs r3, #250 @ 0xfa 80032f6: 009b lsls r3, r3, #2 80032f8: 0018 movs r0, r3 80032fa: f000 f85d bl 80033b8 80032fe: 0003 movs r3, r0 8003300: 7023 strb r3, [r4, #0] /* If the program operation is completed, disable the PG or FSTPG Bit */ CLEAR_BIT(FLASH->CR, TypeProgram); 8003302: 4b09 ldr r3, [pc, #36] @ (8003328 ) 8003304: 695a ldr r2, [r3, #20] 8003306: 68fb ldr r3, [r7, #12] 8003308: 43d9 mvns r1, r3 800330a: 4b07 ldr r3, [pc, #28] @ (8003328 ) 800330c: 400a ands r2, r1 800330e: 615a str r2, [r3, #20] } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 8003310: 4b04 ldr r3, [pc, #16] @ (8003324 ) 8003312: 2200 movs r2, #0 8003314: 701a strb r2, [r3, #0] /* return status */ return status; 8003316: 2317 movs r3, #23 8003318: 18fb adds r3, r7, r3 800331a: 781b ldrb r3, [r3, #0] } 800331c: 0018 movs r0, r3 800331e: 46bd mov sp, r7 8003320: b006 add sp, #24 8003322: bdb0 pop {r4, r5, r7, pc} 8003324: 20000514 .word 0x20000514 8003328: 40022000 .word 0x40022000 0800332c : /** * @brief Unlock the FLASH control register access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { 800332c: b580 push {r7, lr} 800332e: b082 sub sp, #8 8003330: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 8003332: 1dfb adds r3, r7, #7 8003334: 2200 movs r2, #0 8003336: 701a strb r2, [r3, #0] if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) 8003338: 4b0b ldr r3, [pc, #44] @ (8003368 ) 800333a: 695b ldr r3, [r3, #20] 800333c: 2b00 cmp r3, #0 800333e: da0c bge.n 800335a { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); 8003340: 4b09 ldr r3, [pc, #36] @ (8003368 ) 8003342: 4a0a ldr r2, [pc, #40] @ (800336c ) 8003344: 609a str r2, [r3, #8] WRITE_REG(FLASH->KEYR, FLASH_KEY2); 8003346: 4b08 ldr r3, [pc, #32] @ (8003368 ) 8003348: 4a09 ldr r2, [pc, #36] @ (8003370 ) 800334a: 609a str r2, [r3, #8] /* verify Flash is unlock */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) 800334c: 4b06 ldr r3, [pc, #24] @ (8003368 ) 800334e: 695b ldr r3, [r3, #20] 8003350: 2b00 cmp r3, #0 8003352: da02 bge.n 800335a { status = HAL_ERROR; 8003354: 1dfb adds r3, r7, #7 8003356: 2201 movs r2, #1 8003358: 701a strb r2, [r3, #0] } } return status; 800335a: 1dfb adds r3, r7, #7 800335c: 781b ldrb r3, [r3, #0] } 800335e: 0018 movs r0, r3 8003360: 46bd mov sp, r7 8003362: b002 add sp, #8 8003364: bd80 pop {r7, pc} 8003366: 46c0 nop @ (mov r8, r8) 8003368: 40022000 .word 0x40022000 800336c: 45670123 .word 0x45670123 8003370: cdef89ab .word 0xcdef89ab 08003374 : /** * @brief Lock the FLASH control register access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { 8003374: b580 push {r7, lr} 8003376: b082 sub sp, #8 8003378: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_ERROR; 800337a: 1dfb adds r3, r7, #7 800337c: 2201 movs r2, #1 800337e: 701a strb r2, [r3, #0] /* Wait for last operation to be completed */ (void)FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8003380: 23fa movs r3, #250 @ 0xfa 8003382: 009b lsls r3, r3, #2 8003384: 0018 movs r0, r3 8003386: f000 f817 bl 80033b8 /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); 800338a: 4b0a ldr r3, [pc, #40] @ (80033b4 ) 800338c: 695a ldr r2, [r3, #20] 800338e: 4b09 ldr r3, [pc, #36] @ (80033b4 ) 8003390: 2180 movs r1, #128 @ 0x80 8003392: 0609 lsls r1, r1, #24 8003394: 430a orrs r2, r1 8003396: 615a str r2, [r3, #20] /* verify Flash is locked */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u) 8003398: 4b06 ldr r3, [pc, #24] @ (80033b4 ) 800339a: 695b ldr r3, [r3, #20] 800339c: 2b00 cmp r3, #0 800339e: da02 bge.n 80033a6 { status = HAL_OK; 80033a0: 1dfb adds r3, r7, #7 80033a2: 2200 movs r2, #0 80033a4: 701a strb r2, [r3, #0] } return status; 80033a6: 1dfb adds r3, r7, #7 80033a8: 781b ldrb r3, [r3, #0] } 80033aa: 0018 movs r0, r3 80033ac: 46bd mov sp, r7 80033ae: b002 add sp, #8 80033b0: bd80 pop {r7, pc} 80033b2: 46c0 nop @ (mov r8, r8) 80033b4: 40022000 .word 0x40022000 080033b8 : * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { 80033b8: b580 push {r7, lr} 80033ba: b084 sub sp, #16 80033bc: af00 add r7, sp, #0 80033be: 6078 str r0, [r7, #4] uint32_t error; uint32_t tickstart = HAL_GetTick(); 80033c0: f7fe fa52 bl 8001868 80033c4: 0003 movs r3, r0 80033c6: 60fb str r3, [r7, #12] flag will be set */ #if defined(FLASH_DBANK_SUPPORT) error = (FLASH_SR_BSY1 | FLASH_SR_BSY2); #else error = FLASH_SR_BSY1; 80033c8: 2380 movs r3, #128 @ 0x80 80033ca: 025b lsls r3, r3, #9 80033cc: 60bb str r3, [r7, #8] #endif /* FLASH_DBANK_SUPPORT */ while ((FLASH->SR & error) != 0x00U) 80033ce: e00c b.n 80033ea { if(Timeout != HAL_MAX_DELAY) 80033d0: 687b ldr r3, [r7, #4] 80033d2: 3301 adds r3, #1 80033d4: d009 beq.n 80033ea { if ((HAL_GetTick() - tickstart) >= Timeout) 80033d6: f7fe fa47 bl 8001868 80033da: 0002 movs r2, r0 80033dc: 68fb ldr r3, [r7, #12] 80033de: 1ad3 subs r3, r2, r3 80033e0: 687a ldr r2, [r7, #4] 80033e2: 429a cmp r2, r3 80033e4: d801 bhi.n 80033ea { return HAL_TIMEOUT; 80033e6: 2303 movs r3, #3 80033e8: e028 b.n 800343c while ((FLASH->SR & error) != 0x00U) 80033ea: 4b16 ldr r3, [pc, #88] @ (8003444 ) 80033ec: 691b ldr r3, [r3, #16] 80033ee: 68ba ldr r2, [r7, #8] 80033f0: 4013 ands r3, r2 80033f2: d1ed bne.n 80033d0 } } } /* check flash errors */ error = (FLASH->SR & FLASH_SR_ERRORS); 80033f4: 4b13 ldr r3, [pc, #76] @ (8003444 ) 80033f6: 691b ldr r3, [r3, #16] 80033f8: 4a13 ldr r2, [pc, #76] @ (8003448 ) 80033fa: 4013 ands r3, r2 80033fc: 60bb str r3, [r7, #8] /* Clear SR register */ FLASH->SR = FLASH_SR_CLEAR; 80033fe: 4b11 ldr r3, [pc, #68] @ (8003444 ) 8003400: 4a12 ldr r2, [pc, #72] @ (800344c ) 8003402: 611a str r2, [r3, #16] if (error != 0x00U) 8003404: 68bb ldr r3, [r7, #8] 8003406: 2b00 cmp r3, #0 8003408: d011 beq.n 800342e { /*Save the error code*/ pFlash.ErrorCode = error; 800340a: 4b11 ldr r3, [pc, #68] @ (8003450 ) 800340c: 68ba ldr r2, [r7, #8] 800340e: 605a str r2, [r3, #4] return HAL_ERROR; 8003410: 2301 movs r3, #1 8003412: e013 b.n 800343c } /* Wait for control register to be written */ while ((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U) { if(Timeout != HAL_MAX_DELAY) 8003414: 687b ldr r3, [r7, #4] 8003416: 3301 adds r3, #1 8003418: d009 beq.n 800342e { if ((HAL_GetTick() - tickstart) >= Timeout) 800341a: f7fe fa25 bl 8001868 800341e: 0002 movs r2, r0 8003420: 68fb ldr r3, [r7, #12] 8003422: 1ad3 subs r3, r2, r3 8003424: 687a ldr r2, [r7, #4] 8003426: 429a cmp r2, r3 8003428: d801 bhi.n 800342e { return HAL_TIMEOUT; 800342a: 2303 movs r3, #3 800342c: e006 b.n 800343c while ((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U) 800342e: 4b05 ldr r3, [pc, #20] @ (8003444 ) 8003430: 691a ldr r2, [r3, #16] 8003432: 2380 movs r3, #128 @ 0x80 8003434: 02db lsls r3, r3, #11 8003436: 4013 ands r3, r2 8003438: d1ec bne.n 8003414 } } } return HAL_OK; 800343a: 2300 movs r3, #0 } 800343c: 0018 movs r0, r3 800343e: 46bd mov sp, r7 8003440: b004 add sp, #16 8003442: bd80 pop {r7, pc} 8003444: 40022000 .word 0x40022000 8003448: 000083fa .word 0x000083fa 800344c: 000083fb .word 0x000083fb 8003450: 20000514 .word 0x20000514 08003454 : * @param Address Specifies the address to be programmed. * @param Data Specifies the data to be programmed. * @retval None */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) { 8003454: b5b0 push {r4, r5, r7, lr} 8003456: b084 sub sp, #16 8003458: af00 add r7, sp, #0 800345a: 60f8 str r0, [r7, #12] 800345c: 603a str r2, [r7, #0] 800345e: 607b str r3, [r7, #4] /* Set PG bit */ SET_BIT(FLASH->CR, FLASH_CR_PG); 8003460: 4b0b ldr r3, [pc, #44] @ (8003490 ) 8003462: 695a ldr r2, [r3, #20] 8003464: 4b0a ldr r3, [pc, #40] @ (8003490 ) 8003466: 2101 movs r1, #1 8003468: 430a orrs r2, r1 800346a: 615a str r2, [r3, #20] /* Program first word */ *(uint32_t *)Address = (uint32_t)Data; 800346c: 68fb ldr r3, [r7, #12] 800346e: 683a ldr r2, [r7, #0] 8003470: 601a str r2, [r3, #0] so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __STATIC_FORCEINLINE void __ISB(void) { __ASM volatile ("isb 0xF":::"memory"); 8003472: f3bf 8f6f isb sy } 8003476: 46c0 nop @ (mov r8, r8) /* Barrier to ensure programming is performed in 2 steps, in right order (independently of compiler optimization behavior) */ __ISB(); /* Program second word */ *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U); 8003478: 687b ldr r3, [r7, #4] 800347a: 001c movs r4, r3 800347c: 2300 movs r3, #0 800347e: 001d movs r5, r3 8003480: 68fb ldr r3, [r7, #12] 8003482: 3304 adds r3, #4 8003484: 0022 movs r2, r4 8003486: 601a str r2, [r3, #0] } 8003488: 46c0 nop @ (mov r8, r8) 800348a: 46bd mov sp, r7 800348c: b004 add sp, #16 800348e: bdb0 pop {r4, r5, r7, pc} 8003490: 40022000 .word 0x40022000 08003494 : * information on faulty page in case of error (0xFFFFFFFF means that all * the pages have been correctly erased) * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { 8003494: b5b0 push {r4, r5, r7, lr} 8003496: b084 sub sp, #16 8003498: af00 add r7, sp, #0 800349a: 6078 str r0, [r7, #4] 800349c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); /* Process Locked */ __HAL_LOCK(&pFlash); 800349e: 4b35 ldr r3, [pc, #212] @ (8003574 ) 80034a0: 781b ldrb r3, [r3, #0] 80034a2: 2b01 cmp r3, #1 80034a4: d101 bne.n 80034aa 80034a6: 2302 movs r3, #2 80034a8: e05f b.n 800356a 80034aa: 4b32 ldr r3, [pc, #200] @ (8003574 ) 80034ac: 2201 movs r2, #1 80034ae: 701a strb r2, [r3, #0] /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 80034b0: 4b30 ldr r3, [pc, #192] @ (8003574 ) 80034b2: 2200 movs r2, #0 80034b4: 605a str r2, [r3, #4] /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 80034b6: 250f movs r5, #15 80034b8: 197c adds r4, r7, r5 80034ba: 23fa movs r3, #250 @ 0xfa 80034bc: 009b lsls r3, r3, #2 80034be: 0018 movs r0, r3 80034c0: f7ff ff7a bl 80033b8 80034c4: 0003 movs r3, r0 80034c6: 7023 strb r3, [r4, #0] if (status == HAL_OK) 80034c8: 002c movs r4, r5 80034ca: 193b adds r3, r7, r4 80034cc: 781b ldrb r3, [r3, #0] 80034ce: 2b00 cmp r3, #0 80034d0: d145 bne.n 800355e { #if !defined(FLASH_DBANK_SUPPORT) /* For single bank product force Banks to Bank 1 */ pEraseInit->Banks = FLASH_BANK_1; 80034d2: 687b ldr r3, [r7, #4] 80034d4: 2204 movs r2, #4 80034d6: 605a str r2, [r3, #4] #endif /* FLASH_DBANK_SUPPORT */ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS) 80034d8: 687b ldr r3, [r7, #4] 80034da: 681b ldr r3, [r3, #0] 80034dc: 2b04 cmp r3, #4 80034de: d10d bne.n 80034fc { /* Proceed to Mass Erase */ FLASH_MassErase(pEraseInit->Banks); 80034e0: 687b ldr r3, [r7, #4] 80034e2: 685b ldr r3, [r3, #4] 80034e4: 0018 movs r0, r3 80034e6: f000 f849 bl 800357c /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 80034ea: 193c adds r4, r7, r4 80034ec: 23fa movs r3, #250 @ 0xfa 80034ee: 009b lsls r3, r3, #2 80034f0: 0018 movs r0, r3 80034f2: f7ff ff61 bl 80033b8 80034f6: 0003 movs r3, r0 80034f8: 7023 strb r3, [r4, #0] 80034fa: e030 b.n 800355e } else { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; 80034fc: 683b ldr r3, [r7, #0] 80034fe: 2201 movs r2, #1 8003500: 4252 negs r2, r2 8003502: 601a str r2, [r3, #0] for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++) 8003504: 687b ldr r3, [r7, #4] 8003506: 689b ldr r3, [r3, #8] 8003508: 60bb str r3, [r7, #8] 800350a: e01a b.n 8003542 { /* Start erase page */ FLASH_PageErase(pEraseInit->Banks, index); 800350c: 687b ldr r3, [r7, #4] 800350e: 685b ldr r3, [r3, #4] 8003510: 68ba ldr r2, [r7, #8] 8003512: 0011 movs r1, r2 8003514: 0018 movs r0, r3 8003516: f000 f845 bl 80035a4 /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 800351a: 250f movs r5, #15 800351c: 197c adds r4, r7, r5 800351e: 23fa movs r3, #250 @ 0xfa 8003520: 009b lsls r3, r3, #2 8003522: 0018 movs r0, r3 8003524: f7ff ff48 bl 80033b8 8003528: 0003 movs r3, r0 800352a: 7023 strb r3, [r4, #0] if (status != HAL_OK) 800352c: 197b adds r3, r7, r5 800352e: 781b ldrb r3, [r3, #0] 8003530: 2b00 cmp r3, #0 8003532: d003 beq.n 800353c { /* In case of error, stop erase procedure and return the faulty address */ *PageError = index; 8003534: 683b ldr r3, [r7, #0] 8003536: 68ba ldr r2, [r7, #8] 8003538: 601a str r2, [r3, #0] break; 800353a: e00a b.n 8003552 for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++) 800353c: 68bb ldr r3, [r7, #8] 800353e: 3301 adds r3, #1 8003540: 60bb str r3, [r7, #8] 8003542: 687b ldr r3, [r7, #4] 8003544: 689a ldr r2, [r3, #8] 8003546: 687b ldr r3, [r7, #4] 8003548: 68db ldr r3, [r3, #12] 800354a: 18d3 adds r3, r2, r3 800354c: 68ba ldr r2, [r7, #8] 800354e: 429a cmp r2, r3 8003550: d3dc bcc.n 800350c } } /* If operation is completed or interrupted, disable the Page Erase Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); 8003552: 4b09 ldr r3, [pc, #36] @ (8003578 ) 8003554: 695a ldr r2, [r3, #20] 8003556: 4b08 ldr r3, [pc, #32] @ (8003578 ) 8003558: 2102 movs r1, #2 800355a: 438a bics r2, r1 800355c: 615a str r2, [r3, #20] } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 800355e: 4b05 ldr r3, [pc, #20] @ (8003574 ) 8003560: 2200 movs r2, #0 8003562: 701a strb r2, [r3, #0] /* return status */ return status; 8003564: 230f movs r3, #15 8003566: 18fb adds r3, r7, r3 8003568: 781b ldrb r3, [r3, #0] } 800356a: 0018 movs r0, r3 800356c: 46bd mov sp, r7 800356e: b004 add sp, #16 8003570: bdb0 pop {r4, r5, r7, pc} 8003572: 46c0 nop @ (mov r8, r8) 8003574: 20000514 .word 0x20000514 8003578: 40022000 .word 0x40022000 0800357c : * @arg FLASH_BANK_2: Bank2 to be erased* * @note (*) availability depends on devices * @retval None */ static void FLASH_MassErase(uint32_t Banks) { 800357c: b580 push {r7, lr} 800357e: b082 sub sp, #8 8003580: af00 add r7, sp, #0 8003582: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Set the Mass Erase Bit and start bit */ FLASH->CR |= (FLASH_CR_STRT | Banks); 8003584: 4b06 ldr r3, [pc, #24] @ (80035a0 ) 8003586: 695a ldr r2, [r3, #20] 8003588: 687b ldr r3, [r7, #4] 800358a: 431a orrs r2, r3 800358c: 4b04 ldr r3, [pc, #16] @ (80035a0 ) 800358e: 2180 movs r1, #128 @ 0x80 8003590: 0249 lsls r1, r1, #9 8003592: 430a orrs r2, r1 8003594: 615a str r2, [r3, #20] } 8003596: 46c0 nop @ (mov r8, r8) 8003598: 46bd mov sp, r7 800359a: b002 add sp, #8 800359c: bd80 pop {r7, pc} 800359e: 46c0 nop @ (mov r8, r8) 80035a0: 40022000 .word 0x40022000 080035a4 : * This parameter must be a value between 0 and (max number of pages in Flash - 1) * @note (*) availability depends on devices * @retval None */ void FLASH_PageErase(uint32_t Banks, uint32_t Page) { 80035a4: b580 push {r7, lr} 80035a6: b084 sub sp, #16 80035a8: af00 add r7, sp, #0 80035aa: 6078 str r0, [r7, #4] 80035ac: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); assert_param(IS_FLASH_PAGE(Page)); /* Get configuration register, then clear page number */ tmp = (FLASH->CR & ~FLASH_CR_PNB); 80035ae: 4b08 ldr r3, [pc, #32] @ (80035d0 ) 80035b0: 695b ldr r3, [r3, #20] 80035b2: 4a08 ldr r2, [pc, #32] @ (80035d4 ) 80035b4: 4013 ands r3, r2 80035b6: 60fb str r3, [r7, #12] /* Prevent unused argument(s) compilation warning */ UNUSED(Banks); #endif /* FLASH_DBANK_SUPPORT */ /* Set page number, Page Erase bit & Start bit */ FLASH->CR = (tmp | (FLASH_CR_STRT | (Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER)); 80035b8: 683b ldr r3, [r7, #0] 80035ba: 00da lsls r2, r3, #3 80035bc: 68fb ldr r3, [r7, #12] 80035be: 431a orrs r2, r3 80035c0: 4b03 ldr r3, [pc, #12] @ (80035d0 ) 80035c2: 4905 ldr r1, [pc, #20] @ (80035d8 ) 80035c4: 430a orrs r2, r1 80035c6: 615a str r2, [r3, #20] } 80035c8: 46c0 nop @ (mov r8, r8) 80035ca: 46bd mov sp, r7 80035cc: b004 add sp, #16 80035ce: bd80 pop {r7, pc} 80035d0: 40022000 .word 0x40022000 80035d4: ffffe007 .word 0xffffe007 80035d8: 00010002 .word 0x00010002 080035dc : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80035dc: b580 push {r7, lr} 80035de: b086 sub sp, #24 80035e0: af00 add r7, sp, #0 80035e2: 6078 str r0, [r7, #4] 80035e4: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80035e6: 2300 movs r3, #0 80035e8: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80035ea: e147 b.n 800387c { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 80035ec: 683b ldr r3, [r7, #0] 80035ee: 681b ldr r3, [r3, #0] 80035f0: 2101 movs r1, #1 80035f2: 697a ldr r2, [r7, #20] 80035f4: 4091 lsls r1, r2 80035f6: 000a movs r2, r1 80035f8: 4013 ands r3, r2 80035fa: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 80035fc: 68fb ldr r3, [r7, #12] 80035fe: 2b00 cmp r3, #0 8003600: d100 bne.n 8003604 8003602: e138 b.n 8003876 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8003604: 683b ldr r3, [r7, #0] 8003606: 685b ldr r3, [r3, #4] 8003608: 2203 movs r2, #3 800360a: 4013 ands r3, r2 800360c: 2b01 cmp r3, #1 800360e: d005 beq.n 800361c 8003610: 683b ldr r3, [r7, #0] 8003612: 685b ldr r3, [r3, #4] 8003614: 2203 movs r2, #3 8003616: 4013 ands r3, r2 8003618: 2b02 cmp r3, #2 800361a: d130 bne.n 800367e { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800361c: 687b ldr r3, [r7, #4] 800361e: 689b ldr r3, [r3, #8] 8003620: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); 8003622: 697b ldr r3, [r7, #20] 8003624: 005b lsls r3, r3, #1 8003626: 2203 movs r2, #3 8003628: 409a lsls r2, r3 800362a: 0013 movs r3, r2 800362c: 43da mvns r2, r3 800362e: 693b ldr r3, [r7, #16] 8003630: 4013 ands r3, r2 8003632: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8003634: 683b ldr r3, [r7, #0] 8003636: 68da ldr r2, [r3, #12] 8003638: 697b ldr r3, [r7, #20] 800363a: 005b lsls r3, r3, #1 800363c: 409a lsls r2, r3 800363e: 0013 movs r3, r2 8003640: 693a ldr r2, [r7, #16] 8003642: 4313 orrs r3, r2 8003644: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8003646: 687b ldr r3, [r7, #4] 8003648: 693a ldr r2, [r7, #16] 800364a: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800364c: 687b ldr r3, [r7, #4] 800364e: 685b ldr r3, [r3, #4] 8003650: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8003652: 2201 movs r2, #1 8003654: 697b ldr r3, [r7, #20] 8003656: 409a lsls r2, r3 8003658: 0013 movs r3, r2 800365a: 43da mvns r2, r3 800365c: 693b ldr r3, [r7, #16] 800365e: 4013 ands r3, r2 8003660: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8003662: 683b ldr r3, [r7, #0] 8003664: 685b ldr r3, [r3, #4] 8003666: 091b lsrs r3, r3, #4 8003668: 2201 movs r2, #1 800366a: 401a ands r2, r3 800366c: 697b ldr r3, [r7, #20] 800366e: 409a lsls r2, r3 8003670: 0013 movs r3, r2 8003672: 693a ldr r2, [r7, #16] 8003674: 4313 orrs r3, r2 8003676: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8003678: 687b ldr r3, [r7, #4] 800367a: 693a ldr r2, [r7, #16] 800367c: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800367e: 683b ldr r3, [r7, #0] 8003680: 685b ldr r3, [r3, #4] 8003682: 2203 movs r2, #3 8003684: 4013 ands r3, r2 8003686: 2b03 cmp r3, #3 8003688: d017 beq.n 80036ba { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800368a: 687b ldr r3, [r7, #4] 800368c: 68db ldr r3, [r3, #12] 800368e: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); 8003690: 697b ldr r3, [r7, #20] 8003692: 005b lsls r3, r3, #1 8003694: 2203 movs r2, #3 8003696: 409a lsls r2, r3 8003698: 0013 movs r3, r2 800369a: 43da mvns r2, r3 800369c: 693b ldr r3, [r7, #16] 800369e: 4013 ands r3, r2 80036a0: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 80036a2: 683b ldr r3, [r7, #0] 80036a4: 689a ldr r2, [r3, #8] 80036a6: 697b ldr r3, [r7, #20] 80036a8: 005b lsls r3, r3, #1 80036aa: 409a lsls r2, r3 80036ac: 0013 movs r3, r2 80036ae: 693a ldr r2, [r7, #16] 80036b0: 4313 orrs r3, r2 80036b2: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 80036b4: 687b ldr r3, [r7, #4] 80036b6: 693a ldr r2, [r7, #16] 80036b8: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80036ba: 683b ldr r3, [r7, #0] 80036bc: 685b ldr r3, [r3, #4] 80036be: 2203 movs r2, #3 80036c0: 4013 ands r3, r2 80036c2: 2b02 cmp r3, #2 80036c4: d123 bne.n 800370e /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 80036c6: 697b ldr r3, [r7, #20] 80036c8: 08da lsrs r2, r3, #3 80036ca: 687b ldr r3, [r7, #4] 80036cc: 3208 adds r2, #8 80036ce: 0092 lsls r2, r2, #2 80036d0: 58d3 ldr r3, [r2, r3] 80036d2: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 80036d4: 697b ldr r3, [r7, #20] 80036d6: 2207 movs r2, #7 80036d8: 4013 ands r3, r2 80036da: 009b lsls r3, r3, #2 80036dc: 220f movs r2, #15 80036de: 409a lsls r2, r3 80036e0: 0013 movs r3, r2 80036e2: 43da mvns r2, r3 80036e4: 693b ldr r3, [r7, #16] 80036e6: 4013 ands r3, r2 80036e8: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 80036ea: 683b ldr r3, [r7, #0] 80036ec: 691a ldr r2, [r3, #16] 80036ee: 697b ldr r3, [r7, #20] 80036f0: 2107 movs r1, #7 80036f2: 400b ands r3, r1 80036f4: 009b lsls r3, r3, #2 80036f6: 409a lsls r2, r3 80036f8: 0013 movs r3, r2 80036fa: 693a ldr r2, [r7, #16] 80036fc: 4313 orrs r3, r2 80036fe: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8003700: 697b ldr r3, [r7, #20] 8003702: 08da lsrs r2, r3, #3 8003704: 687b ldr r3, [r7, #4] 8003706: 3208 adds r2, #8 8003708: 0092 lsls r2, r2, #2 800370a: 6939 ldr r1, [r7, #16] 800370c: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800370e: 687b ldr r3, [r7, #4] 8003710: 681b ldr r3, [r3, #0] 8003712: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); 8003714: 697b ldr r3, [r7, #20] 8003716: 005b lsls r3, r3, #1 8003718: 2203 movs r2, #3 800371a: 409a lsls r2, r3 800371c: 0013 movs r3, r2 800371e: 43da mvns r2, r3 8003720: 693b ldr r3, [r7, #16] 8003722: 4013 ands r3, r2 8003724: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8003726: 683b ldr r3, [r7, #0] 8003728: 685b ldr r3, [r3, #4] 800372a: 2203 movs r2, #3 800372c: 401a ands r2, r3 800372e: 697b ldr r3, [r7, #20] 8003730: 005b lsls r3, r3, #1 8003732: 409a lsls r2, r3 8003734: 0013 movs r3, r2 8003736: 693a ldr r2, [r7, #16] 8003738: 4313 orrs r3, r2 800373a: 613b str r3, [r7, #16] GPIOx->MODER = temp; 800373c: 687b ldr r3, [r7, #4] 800373e: 693a ldr r2, [r7, #16] 8003740: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8003742: 683b ldr r3, [r7, #0] 8003744: 685a ldr r2, [r3, #4] 8003746: 23c0 movs r3, #192 @ 0xc0 8003748: 029b lsls r3, r3, #10 800374a: 4013 ands r3, r2 800374c: d100 bne.n 8003750 800374e: e092 b.n 8003876 { temp = EXTI->EXTICR[position >> 2u]; 8003750: 4a50 ldr r2, [pc, #320] @ (8003894 ) 8003752: 697b ldr r3, [r7, #20] 8003754: 089b lsrs r3, r3, #2 8003756: 3318 adds r3, #24 8003758: 009b lsls r3, r3, #2 800375a: 589b ldr r3, [r3, r2] 800375c: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (8u * (position & 0x03u))); 800375e: 697b ldr r3, [r7, #20] 8003760: 2203 movs r2, #3 8003762: 4013 ands r3, r2 8003764: 00db lsls r3, r3, #3 8003766: 220f movs r2, #15 8003768: 409a lsls r2, r3 800376a: 0013 movs r3, r2 800376c: 43da mvns r2, r3 800376e: 693b ldr r3, [r7, #16] 8003770: 4013 ands r3, r2 8003772: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); 8003774: 687a ldr r2, [r7, #4] 8003776: 23a0 movs r3, #160 @ 0xa0 8003778: 05db lsls r3, r3, #23 800377a: 429a cmp r2, r3 800377c: d013 beq.n 80037a6 800377e: 687b ldr r3, [r7, #4] 8003780: 4a45 ldr r2, [pc, #276] @ (8003898 ) 8003782: 4293 cmp r3, r2 8003784: d00d beq.n 80037a2 8003786: 687b ldr r3, [r7, #4] 8003788: 4a44 ldr r2, [pc, #272] @ (800389c ) 800378a: 4293 cmp r3, r2 800378c: d007 beq.n 800379e 800378e: 687b ldr r3, [r7, #4] 8003790: 4a43 ldr r2, [pc, #268] @ (80038a0 ) 8003792: 4293 cmp r3, r2 8003794: d101 bne.n 800379a 8003796: 2303 movs r3, #3 8003798: e006 b.n 80037a8 800379a: 2305 movs r3, #5 800379c: e004 b.n 80037a8 800379e: 2302 movs r3, #2 80037a0: e002 b.n 80037a8 80037a2: 2301 movs r3, #1 80037a4: e000 b.n 80037a8 80037a6: 2300 movs r3, #0 80037a8: 697a ldr r2, [r7, #20] 80037aa: 2103 movs r1, #3 80037ac: 400a ands r2, r1 80037ae: 00d2 lsls r2, r2, #3 80037b0: 4093 lsls r3, r2 80037b2: 693a ldr r2, [r7, #16] 80037b4: 4313 orrs r3, r2 80037b6: 613b str r3, [r7, #16] EXTI->EXTICR[position >> 2u] = temp; 80037b8: 4936 ldr r1, [pc, #216] @ (8003894 ) 80037ba: 697b ldr r3, [r7, #20] 80037bc: 089b lsrs r3, r3, #2 80037be: 3318 adds r3, #24 80037c0: 009b lsls r3, r3, #2 80037c2: 693a ldr r2, [r7, #16] 80037c4: 505a str r2, [r3, r1] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 80037c6: 4b33 ldr r3, [pc, #204] @ (8003894 ) 80037c8: 681b ldr r3, [r3, #0] 80037ca: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80037cc: 68fb ldr r3, [r7, #12] 80037ce: 43da mvns r2, r3 80037d0: 693b ldr r3, [r7, #16] 80037d2: 4013 ands r3, r2 80037d4: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 80037d6: 683b ldr r3, [r7, #0] 80037d8: 685a ldr r2, [r3, #4] 80037da: 2380 movs r3, #128 @ 0x80 80037dc: 035b lsls r3, r3, #13 80037de: 4013 ands r3, r2 80037e0: d003 beq.n 80037ea { temp |= iocurrent; 80037e2: 693a ldr r2, [r7, #16] 80037e4: 68fb ldr r3, [r7, #12] 80037e6: 4313 orrs r3, r2 80037e8: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 80037ea: 4b2a ldr r3, [pc, #168] @ (8003894 ) 80037ec: 693a ldr r2, [r7, #16] 80037ee: 601a str r2, [r3, #0] temp = EXTI->FTSR1; 80037f0: 4b28 ldr r3, [pc, #160] @ (8003894 ) 80037f2: 685b ldr r3, [r3, #4] 80037f4: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80037f6: 68fb ldr r3, [r7, #12] 80037f8: 43da mvns r2, r3 80037fa: 693b ldr r3, [r7, #16] 80037fc: 4013 ands r3, r2 80037fe: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8003800: 683b ldr r3, [r7, #0] 8003802: 685a ldr r2, [r3, #4] 8003804: 2380 movs r3, #128 @ 0x80 8003806: 039b lsls r3, r3, #14 8003808: 4013 ands r3, r2 800380a: d003 beq.n 8003814 { temp |= iocurrent; 800380c: 693a ldr r2, [r7, #16] 800380e: 68fb ldr r3, [r7, #12] 8003810: 4313 orrs r3, r2 8003812: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 8003814: 4b1f ldr r3, [pc, #124] @ (8003894 ) 8003816: 693a ldr r2, [r7, #16] 8003818: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI->EMR1; 800381a: 4a1e ldr r2, [pc, #120] @ (8003894 ) 800381c: 2384 movs r3, #132 @ 0x84 800381e: 58d3 ldr r3, [r2, r3] 8003820: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8003822: 68fb ldr r3, [r7, #12] 8003824: 43da mvns r2, r3 8003826: 693b ldr r3, [r7, #16] 8003828: 4013 ands r3, r2 800382a: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 800382c: 683b ldr r3, [r7, #0] 800382e: 685a ldr r2, [r3, #4] 8003830: 2380 movs r3, #128 @ 0x80 8003832: 029b lsls r3, r3, #10 8003834: 4013 ands r3, r2 8003836: d003 beq.n 8003840 { temp |= iocurrent; 8003838: 693a ldr r2, [r7, #16] 800383a: 68fb ldr r3, [r7, #12] 800383c: 4313 orrs r3, r2 800383e: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 8003840: 4914 ldr r1, [pc, #80] @ (8003894 ) 8003842: 2284 movs r2, #132 @ 0x84 8003844: 693b ldr r3, [r7, #16] 8003846: 508b str r3, [r1, r2] temp = EXTI->IMR1; 8003848: 4a12 ldr r2, [pc, #72] @ (8003894 ) 800384a: 2380 movs r3, #128 @ 0x80 800384c: 58d3 ldr r3, [r2, r3] 800384e: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8003850: 68fb ldr r3, [r7, #12] 8003852: 43da mvns r2, r3 8003854: 693b ldr r3, [r7, #16] 8003856: 4013 ands r3, r2 8003858: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) 800385a: 683b ldr r3, [r7, #0] 800385c: 685a ldr r2, [r3, #4] 800385e: 2380 movs r3, #128 @ 0x80 8003860: 025b lsls r3, r3, #9 8003862: 4013 ands r3, r2 8003864: d003 beq.n 800386e { temp |= iocurrent; 8003866: 693a ldr r2, [r7, #16] 8003868: 68fb ldr r3, [r7, #12] 800386a: 4313 orrs r3, r2 800386c: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 800386e: 4909 ldr r1, [pc, #36] @ (8003894 ) 8003870: 2280 movs r2, #128 @ 0x80 8003872: 693b ldr r3, [r7, #16] 8003874: 508b str r3, [r1, r2] } } position++; 8003876: 697b ldr r3, [r7, #20] 8003878: 3301 adds r3, #1 800387a: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 800387c: 683b ldr r3, [r7, #0] 800387e: 681a ldr r2, [r3, #0] 8003880: 697b ldr r3, [r7, #20] 8003882: 40da lsrs r2, r3 8003884: 1e13 subs r3, r2, #0 8003886: d000 beq.n 800388a 8003888: e6b0 b.n 80035ec } } 800388a: 46c0 nop @ (mov r8, r8) 800388c: 46c0 nop @ (mov r8, r8) 800388e: 46bd mov sp, r7 8003890: b006 add sp, #24 8003892: bd80 pop {r7, pc} 8003894: 40021800 .word 0x40021800 8003898: 50000400 .word 0x50000400 800389c: 50000800 .word 0x50000800 80038a0: 50000c00 .word 0x50000c00 080038a4 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80038a4: b580 push {r7, lr} 80038a6: b084 sub sp, #16 80038a8: af00 add r7, sp, #0 80038aa: 6078 str r0, [r7, #4] 80038ac: 000a movs r2, r1 80038ae: 1cbb adds r3, r7, #2 80038b0: 801a strh r2, [r3, #0] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00u) 80038b2: 687b ldr r3, [r7, #4] 80038b4: 691b ldr r3, [r3, #16] 80038b6: 1cba adds r2, r7, #2 80038b8: 8812 ldrh r2, [r2, #0] 80038ba: 4013 ands r3, r2 80038bc: d004 beq.n 80038c8 { bitstatus = GPIO_PIN_SET; 80038be: 230f movs r3, #15 80038c0: 18fb adds r3, r7, r3 80038c2: 2201 movs r2, #1 80038c4: 701a strb r2, [r3, #0] 80038c6: e003 b.n 80038d0 } else { bitstatus = GPIO_PIN_RESET; 80038c8: 230f movs r3, #15 80038ca: 18fb adds r3, r7, r3 80038cc: 2200 movs r2, #0 80038ce: 701a strb r2, [r3, #0] } return bitstatus; 80038d0: 230f movs r3, #15 80038d2: 18fb adds r3, r7, r3 80038d4: 781b ldrb r3, [r3, #0] } 80038d6: 0018 movs r0, r3 80038d8: 46bd mov sp, r7 80038da: b004 add sp, #16 80038dc: bd80 pop {r7, pc} ... 080038e0 : * cleared before returning the status. If the flag is not cleared within * 6 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 80038e0: b580 push {r7, lr} 80038e2: b084 sub sp, #16 80038e4: af00 add r7, sp, #0 80038e6: 6078 str r0, [r7, #4] uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); /* Modify voltage scaling range */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); 80038e8: 4b19 ldr r3, [pc, #100] @ (8003950 ) 80038ea: 681b ldr r3, [r3, #0] 80038ec: 4a19 ldr r2, [pc, #100] @ (8003954 ) 80038ee: 4013 ands r3, r2 80038f0: 0019 movs r1, r3 80038f2: 4b17 ldr r3, [pc, #92] @ (8003950 ) 80038f4: 687a ldr r2, [r7, #4] 80038f6: 430a orrs r2, r1 80038f8: 601a str r2, [r3, #0] /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 80038fa: 687a ldr r2, [r7, #4] 80038fc: 2380 movs r3, #128 @ 0x80 80038fe: 009b lsls r3, r3, #2 8003900: 429a cmp r2, r3 8003902: d11f bne.n 8003944 { /* Set timeout value */ wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; 8003904: 4b14 ldr r3, [pc, #80] @ (8003958 ) 8003906: 681a ldr r2, [r3, #0] 8003908: 0013 movs r3, r2 800390a: 005b lsls r3, r3, #1 800390c: 189b adds r3, r3, r2 800390e: 005b lsls r3, r3, #1 8003910: 4912 ldr r1, [pc, #72] @ (800395c ) 8003912: 0018 movs r0, r3 8003914: f7fc fbf4 bl 8000100 <__udivsi3> 8003918: 0003 movs r3, r0 800391a: 3301 adds r3, #1 800391c: 60fb str r3, [r7, #12] /* Wait until VOSF is reset */ while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 800391e: e008 b.n 8003932 { if (wait_loop_index != 0U) 8003920: 68fb ldr r3, [r7, #12] 8003922: 2b00 cmp r3, #0 8003924: d003 beq.n 800392e { wait_loop_index--; 8003926: 68fb ldr r3, [r7, #12] 8003928: 3b01 subs r3, #1 800392a: 60fb str r3, [r7, #12] 800392c: e001 b.n 8003932 } else { return HAL_TIMEOUT; 800392e: 2303 movs r3, #3 8003930: e009 b.n 8003946 while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 8003932: 4b07 ldr r3, [pc, #28] @ (8003950 ) 8003934: 695a ldr r2, [r3, #20] 8003936: 2380 movs r3, #128 @ 0x80 8003938: 00db lsls r3, r3, #3 800393a: 401a ands r2, r3 800393c: 2380 movs r3, #128 @ 0x80 800393e: 00db lsls r3, r3, #3 8003940: 429a cmp r2, r3 8003942: d0ed beq.n 8003920 } } } return HAL_OK; 8003944: 2300 movs r3, #0 } 8003946: 0018 movs r0, r3 8003948: 46bd mov sp, r7 800394a: b004 add sp, #16 800394c: bd80 pop {r7, pc} 800394e: 46c0 nop @ (mov r8, r8) 8003950: 40007000 .word 0x40007000 8003954: fffff9ff .word 0xfffff9ff 8003958: 20000000 .word 0x20000000 800395c: 000f4240 .word 0x000f4240 08003960 : * @arg @ref LL_RCC_APB1_DIV_4 * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) { 8003960: b580 push {r7, lr} 8003962: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); 8003964: 4b03 ldr r3, [pc, #12] @ (8003974 ) 8003966: 689a ldr r2, [r3, #8] 8003968: 23e0 movs r3, #224 @ 0xe0 800396a: 01db lsls r3, r3, #7 800396c: 4013 ands r3, r2 } 800396e: 0018 movs r0, r3 8003970: 46bd mov sp, r7 8003972: bd80 pop {r7, pc} 8003974: 40021000 .word 0x40021000 08003978 : * supported by this function. User should request a transition to LSE Off * first and then to LSE On or LSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8003978: b580 push {r7, lr} 800397a: b088 sub sp, #32 800397c: af00 add r7, sp, #0 800397e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8003980: 687b ldr r3, [r7, #4] 8003982: 2b00 cmp r3, #0 8003984: d101 bne.n 800398a { return HAL_ERROR; 8003986: 2301 movs r3, #1 8003988: e2f3 b.n 8003f72 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800398a: 687b ldr r3, [r7, #4] 800398c: 681b ldr r3, [r3, #0] 800398e: 2201 movs r2, #1 8003990: 4013 ands r3, r2 8003992: d100 bne.n 8003996 8003994: e07c b.n 8003a90 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003996: 4bc3 ldr r3, [pc, #780] @ (8003ca4 ) 8003998: 689b ldr r3, [r3, #8] 800399a: 2238 movs r2, #56 @ 0x38 800399c: 4013 ands r3, r2 800399e: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 80039a0: 4bc0 ldr r3, [pc, #768] @ (8003ca4 ) 80039a2: 68db ldr r3, [r3, #12] 80039a4: 2203 movs r2, #3 80039a6: 4013 ands r3, r2 80039a8: 617b str r3, [r7, #20] /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) 80039aa: 69bb ldr r3, [r7, #24] 80039ac: 2b10 cmp r3, #16 80039ae: d102 bne.n 80039b6 80039b0: 697b ldr r3, [r7, #20] 80039b2: 2b03 cmp r3, #3 80039b4: d002 beq.n 80039bc || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) 80039b6: 69bb ldr r3, [r7, #24] 80039b8: 2b08 cmp r3, #8 80039ba: d10b bne.n 80039d4 { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80039bc: 4bb9 ldr r3, [pc, #740] @ (8003ca4 ) 80039be: 681a ldr r2, [r3, #0] 80039c0: 2380 movs r3, #128 @ 0x80 80039c2: 029b lsls r3, r3, #10 80039c4: 4013 ands r3, r2 80039c6: d062 beq.n 8003a8e 80039c8: 687b ldr r3, [r7, #4] 80039ca: 685b ldr r3, [r3, #4] 80039cc: 2b00 cmp r3, #0 80039ce: d15e bne.n 8003a8e { return HAL_ERROR; 80039d0: 2301 movs r3, #1 80039d2: e2ce b.n 8003f72 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80039d4: 687b ldr r3, [r7, #4] 80039d6: 685a ldr r2, [r3, #4] 80039d8: 2380 movs r3, #128 @ 0x80 80039da: 025b lsls r3, r3, #9 80039dc: 429a cmp r2, r3 80039de: d107 bne.n 80039f0 80039e0: 4bb0 ldr r3, [pc, #704] @ (8003ca4 ) 80039e2: 681a ldr r2, [r3, #0] 80039e4: 4baf ldr r3, [pc, #700] @ (8003ca4 ) 80039e6: 2180 movs r1, #128 @ 0x80 80039e8: 0249 lsls r1, r1, #9 80039ea: 430a orrs r2, r1 80039ec: 601a str r2, [r3, #0] 80039ee: e020 b.n 8003a32 80039f0: 687b ldr r3, [r7, #4] 80039f2: 685a ldr r2, [r3, #4] 80039f4: 23a0 movs r3, #160 @ 0xa0 80039f6: 02db lsls r3, r3, #11 80039f8: 429a cmp r2, r3 80039fa: d10e bne.n 8003a1a 80039fc: 4ba9 ldr r3, [pc, #676] @ (8003ca4 ) 80039fe: 681a ldr r2, [r3, #0] 8003a00: 4ba8 ldr r3, [pc, #672] @ (8003ca4 ) 8003a02: 2180 movs r1, #128 @ 0x80 8003a04: 02c9 lsls r1, r1, #11 8003a06: 430a orrs r2, r1 8003a08: 601a str r2, [r3, #0] 8003a0a: 4ba6 ldr r3, [pc, #664] @ (8003ca4 ) 8003a0c: 681a ldr r2, [r3, #0] 8003a0e: 4ba5 ldr r3, [pc, #660] @ (8003ca4 ) 8003a10: 2180 movs r1, #128 @ 0x80 8003a12: 0249 lsls r1, r1, #9 8003a14: 430a orrs r2, r1 8003a16: 601a str r2, [r3, #0] 8003a18: e00b b.n 8003a32 8003a1a: 4ba2 ldr r3, [pc, #648] @ (8003ca4 ) 8003a1c: 681a ldr r2, [r3, #0] 8003a1e: 4ba1 ldr r3, [pc, #644] @ (8003ca4 ) 8003a20: 49a1 ldr r1, [pc, #644] @ (8003ca8 ) 8003a22: 400a ands r2, r1 8003a24: 601a str r2, [r3, #0] 8003a26: 4b9f ldr r3, [pc, #636] @ (8003ca4 ) 8003a28: 681a ldr r2, [r3, #0] 8003a2a: 4b9e ldr r3, [pc, #632] @ (8003ca4 ) 8003a2c: 499f ldr r1, [pc, #636] @ (8003cac ) 8003a2e: 400a ands r2, r1 8003a30: 601a str r2, [r3, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8003a32: 687b ldr r3, [r7, #4] 8003a34: 685b ldr r3, [r3, #4] 8003a36: 2b00 cmp r3, #0 8003a38: d014 beq.n 8003a64 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003a3a: f7fd ff15 bl 8001868 8003a3e: 0003 movs r3, r0 8003a40: 613b str r3, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8003a42: e008 b.n 8003a56 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003a44: f7fd ff10 bl 8001868 8003a48: 0002 movs r2, r0 8003a4a: 693b ldr r3, [r7, #16] 8003a4c: 1ad3 subs r3, r2, r3 8003a4e: 2b64 cmp r3, #100 @ 0x64 8003a50: d901 bls.n 8003a56 { return HAL_TIMEOUT; 8003a52: 2303 movs r3, #3 8003a54: e28d b.n 8003f72 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8003a56: 4b93 ldr r3, [pc, #588] @ (8003ca4 ) 8003a58: 681a ldr r2, [r3, #0] 8003a5a: 2380 movs r3, #128 @ 0x80 8003a5c: 029b lsls r3, r3, #10 8003a5e: 4013 ands r3, r2 8003a60: d0f0 beq.n 8003a44 8003a62: e015 b.n 8003a90 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003a64: f7fd ff00 bl 8001868 8003a68: 0003 movs r3, r0 8003a6a: 613b str r3, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8003a6c: e008 b.n 8003a80 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003a6e: f7fd fefb bl 8001868 8003a72: 0002 movs r2, r0 8003a74: 693b ldr r3, [r7, #16] 8003a76: 1ad3 subs r3, r2, r3 8003a78: 2b64 cmp r3, #100 @ 0x64 8003a7a: d901 bls.n 8003a80 { return HAL_TIMEOUT; 8003a7c: 2303 movs r3, #3 8003a7e: e278 b.n 8003f72 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8003a80: 4b88 ldr r3, [pc, #544] @ (8003ca4 ) 8003a82: 681a ldr r2, [r3, #0] 8003a84: 2380 movs r3, #128 @ 0x80 8003a86: 029b lsls r3, r3, #10 8003a88: 4013 ands r3, r2 8003a8a: d1f0 bne.n 8003a6e 8003a8c: e000 b.n 8003a90 if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003a8e: 46c0 nop @ (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8003a90: 687b ldr r3, [r7, #4] 8003a92: 681b ldr r3, [r3, #0] 8003a94: 2202 movs r2, #2 8003a96: 4013 ands r3, r2 8003a98: d100 bne.n 8003a9c 8003a9a: e099 b.n 8003bd0 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003a9c: 4b81 ldr r3, [pc, #516] @ (8003ca4 ) 8003a9e: 689b ldr r3, [r3, #8] 8003aa0: 2238 movs r2, #56 @ 0x38 8003aa2: 4013 ands r3, r2 8003aa4: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8003aa6: 4b7f ldr r3, [pc, #508] @ (8003ca4 ) 8003aa8: 68db ldr r3, [r3, #12] 8003aaa: 2203 movs r2, #3 8003aac: 4013 ands r3, r2 8003aae: 617b str r3, [r7, #20] if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) 8003ab0: 69bb ldr r3, [r7, #24] 8003ab2: 2b10 cmp r3, #16 8003ab4: d102 bne.n 8003abc 8003ab6: 697b ldr r3, [r7, #20] 8003ab8: 2b02 cmp r3, #2 8003aba: d002 beq.n 8003ac2 || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) 8003abc: 69bb ldr r3, [r7, #24] 8003abe: 2b00 cmp r3, #0 8003ac0: d135 bne.n 8003b2e { /* When HSI is used as system clock or as PLL input clock it can not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8003ac2: 4b78 ldr r3, [pc, #480] @ (8003ca4 ) 8003ac4: 681a ldr r2, [r3, #0] 8003ac6: 2380 movs r3, #128 @ 0x80 8003ac8: 00db lsls r3, r3, #3 8003aca: 4013 ands r3, r2 8003acc: d005 beq.n 8003ada 8003ace: 687b ldr r3, [r7, #4] 8003ad0: 68db ldr r3, [r3, #12] 8003ad2: 2b00 cmp r3, #0 8003ad4: d101 bne.n 8003ada { return HAL_ERROR; 8003ad6: 2301 movs r3, #1 8003ad8: e24b b.n 8003f72 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003ada: 4b72 ldr r3, [pc, #456] @ (8003ca4 ) 8003adc: 685b ldr r3, [r3, #4] 8003ade: 4a74 ldr r2, [pc, #464] @ (8003cb0 ) 8003ae0: 4013 ands r3, r2 8003ae2: 0019 movs r1, r3 8003ae4: 687b ldr r3, [r7, #4] 8003ae6: 695b ldr r3, [r3, #20] 8003ae8: 021a lsls r2, r3, #8 8003aea: 4b6e ldr r3, [pc, #440] @ (8003ca4 ) 8003aec: 430a orrs r2, r1 8003aee: 605a str r2, [r3, #4] if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) 8003af0: 69bb ldr r3, [r7, #24] 8003af2: 2b00 cmp r3, #0 8003af4: d112 bne.n 8003b1c { /* Adjust the HSI16 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 8003af6: 4b6b ldr r3, [pc, #428] @ (8003ca4 ) 8003af8: 681b ldr r3, [r3, #0] 8003afa: 4a6e ldr r2, [pc, #440] @ (8003cb4 ) 8003afc: 4013 ands r3, r2 8003afe: 0019 movs r1, r3 8003b00: 687b ldr r3, [r7, #4] 8003b02: 691a ldr r2, [r3, #16] 8003b04: 4b67 ldr r3, [pc, #412] @ (8003ca4 ) 8003b06: 430a orrs r2, r1 8003b08: 601a str r2, [r3, #0] /* Update the SystemCoreClock global variable with HSISYS value */ SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); 8003b0a: 4b66 ldr r3, [pc, #408] @ (8003ca4 ) 8003b0c: 681b ldr r3, [r3, #0] 8003b0e: 0adb lsrs r3, r3, #11 8003b10: 2207 movs r2, #7 8003b12: 4013 ands r3, r2 8003b14: 4a68 ldr r2, [pc, #416] @ (8003cb8 ) 8003b16: 40da lsrs r2, r3 8003b18: 4b68 ldr r3, [pc, #416] @ (8003cbc ) 8003b1a: 601a str r2, [r3, #0] } /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8003b1c: 4b68 ldr r3, [pc, #416] @ (8003cc0 ) 8003b1e: 681b ldr r3, [r3, #0] 8003b20: 0018 movs r0, r3 8003b22: f7fd fe45 bl 80017b0 8003b26: 1e03 subs r3, r0, #0 8003b28: d051 beq.n 8003bce { return HAL_ERROR; 8003b2a: 2301 movs r3, #1 8003b2c: e221 b.n 8003f72 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8003b2e: 687b ldr r3, [r7, #4] 8003b30: 68db ldr r3, [r3, #12] 8003b32: 2b00 cmp r3, #0 8003b34: d030 beq.n 8003b98 { /* Configure the HSI16 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 8003b36: 4b5b ldr r3, [pc, #364] @ (8003ca4 ) 8003b38: 681b ldr r3, [r3, #0] 8003b3a: 4a5e ldr r2, [pc, #376] @ (8003cb4 ) 8003b3c: 4013 ands r3, r2 8003b3e: 0019 movs r1, r3 8003b40: 687b ldr r3, [r7, #4] 8003b42: 691a ldr r2, [r3, #16] 8003b44: 4b57 ldr r3, [pc, #348] @ (8003ca4 ) 8003b46: 430a orrs r2, r1 8003b48: 601a str r2, [r3, #0] /* Enable the Internal High Speed oscillator (HSI16). */ __HAL_RCC_HSI_ENABLE(); 8003b4a: 4b56 ldr r3, [pc, #344] @ (8003ca4 ) 8003b4c: 681a ldr r2, [r3, #0] 8003b4e: 4b55 ldr r3, [pc, #340] @ (8003ca4 ) 8003b50: 2180 movs r1, #128 @ 0x80 8003b52: 0049 lsls r1, r1, #1 8003b54: 430a orrs r2, r1 8003b56: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003b58: f7fd fe86 bl 8001868 8003b5c: 0003 movs r3, r0 8003b5e: 613b str r3, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003b60: e008 b.n 8003b74 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003b62: f7fd fe81 bl 8001868 8003b66: 0002 movs r2, r0 8003b68: 693b ldr r3, [r7, #16] 8003b6a: 1ad3 subs r3, r2, r3 8003b6c: 2b02 cmp r3, #2 8003b6e: d901 bls.n 8003b74 { return HAL_TIMEOUT; 8003b70: 2303 movs r3, #3 8003b72: e1fe b.n 8003f72 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003b74: 4b4b ldr r3, [pc, #300] @ (8003ca4 ) 8003b76: 681a ldr r2, [r3, #0] 8003b78: 2380 movs r3, #128 @ 0x80 8003b7a: 00db lsls r3, r3, #3 8003b7c: 4013 ands r3, r2 8003b7e: d0f0 beq.n 8003b62 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003b80: 4b48 ldr r3, [pc, #288] @ (8003ca4 ) 8003b82: 685b ldr r3, [r3, #4] 8003b84: 4a4a ldr r2, [pc, #296] @ (8003cb0 ) 8003b86: 4013 ands r3, r2 8003b88: 0019 movs r1, r3 8003b8a: 687b ldr r3, [r7, #4] 8003b8c: 695b ldr r3, [r3, #20] 8003b8e: 021a lsls r2, r3, #8 8003b90: 4b44 ldr r3, [pc, #272] @ (8003ca4 ) 8003b92: 430a orrs r2, r1 8003b94: 605a str r2, [r3, #4] 8003b96: e01b b.n 8003bd0 } else { /* Disable the Internal High Speed oscillator (HSI16). */ __HAL_RCC_HSI_DISABLE(); 8003b98: 4b42 ldr r3, [pc, #264] @ (8003ca4 ) 8003b9a: 681a ldr r2, [r3, #0] 8003b9c: 4b41 ldr r3, [pc, #260] @ (8003ca4 ) 8003b9e: 4949 ldr r1, [pc, #292] @ (8003cc4 ) 8003ba0: 400a ands r2, r1 8003ba2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003ba4: f7fd fe60 bl 8001868 8003ba8: 0003 movs r3, r0 8003baa: 613b str r3, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8003bac: e008 b.n 8003bc0 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003bae: f7fd fe5b bl 8001868 8003bb2: 0002 movs r2, r0 8003bb4: 693b ldr r3, [r7, #16] 8003bb6: 1ad3 subs r3, r2, r3 8003bb8: 2b02 cmp r3, #2 8003bba: d901 bls.n 8003bc0 { return HAL_TIMEOUT; 8003bbc: 2303 movs r3, #3 8003bbe: e1d8 b.n 8003f72 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8003bc0: 4b38 ldr r3, [pc, #224] @ (8003ca4 ) 8003bc2: 681a ldr r2, [r3, #0] 8003bc4: 2380 movs r3, #128 @ 0x80 8003bc6: 00db lsls r3, r3, #3 8003bc8: 4013 ands r3, r2 8003bca: d1f0 bne.n 8003bae 8003bcc: e000 b.n 8003bd0 if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8003bce: 46c0 nop @ (mov r8, r8) } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8003bd0: 687b ldr r3, [r7, #4] 8003bd2: 681b ldr r3, [r3, #0] 8003bd4: 2208 movs r2, #8 8003bd6: 4013 ands r3, r2 8003bd8: d047 beq.n 8003c6a { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check if LSI is used as system clock */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) 8003bda: 4b32 ldr r3, [pc, #200] @ (8003ca4 ) 8003bdc: 689b ldr r3, [r3, #8] 8003bde: 2238 movs r2, #56 @ 0x38 8003be0: 4013 ands r3, r2 8003be2: 2b18 cmp r3, #24 8003be4: d10a bne.n 8003bfc { /* When LSI is used as system clock it will not be disabled */ if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)) 8003be6: 4b2f ldr r3, [pc, #188] @ (8003ca4 ) 8003be8: 6e1b ldr r3, [r3, #96] @ 0x60 8003bea: 2202 movs r2, #2 8003bec: 4013 ands r3, r2 8003bee: d03c beq.n 8003c6a 8003bf0: 687b ldr r3, [r7, #4] 8003bf2: 699b ldr r3, [r3, #24] 8003bf4: 2b00 cmp r3, #0 8003bf6: d138 bne.n 8003c6a { return HAL_ERROR; 8003bf8: 2301 movs r3, #1 8003bfa: e1ba b.n 8003f72 } } else { /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8003bfc: 687b ldr r3, [r7, #4] 8003bfe: 699b ldr r3, [r3, #24] 8003c00: 2b00 cmp r3, #0 8003c02: d019 beq.n 8003c38 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003c04: 4b27 ldr r3, [pc, #156] @ (8003ca4 ) 8003c06: 6e1a ldr r2, [r3, #96] @ 0x60 8003c08: 4b26 ldr r3, [pc, #152] @ (8003ca4 ) 8003c0a: 2101 movs r1, #1 8003c0c: 430a orrs r2, r1 8003c0e: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003c10: f7fd fe2a bl 8001868 8003c14: 0003 movs r3, r0 8003c16: 613b str r3, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8003c18: e008 b.n 8003c2c { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003c1a: f7fd fe25 bl 8001868 8003c1e: 0002 movs r2, r0 8003c20: 693b ldr r3, [r7, #16] 8003c22: 1ad3 subs r3, r2, r3 8003c24: 2b02 cmp r3, #2 8003c26: d901 bls.n 8003c2c { return HAL_TIMEOUT; 8003c28: 2303 movs r3, #3 8003c2a: e1a2 b.n 8003f72 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8003c2c: 4b1d ldr r3, [pc, #116] @ (8003ca4 ) 8003c2e: 6e1b ldr r3, [r3, #96] @ 0x60 8003c30: 2202 movs r2, #2 8003c32: 4013 ands r3, r2 8003c34: d0f1 beq.n 8003c1a 8003c36: e018 b.n 8003c6a } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8003c38: 4b1a ldr r3, [pc, #104] @ (8003ca4 ) 8003c3a: 6e1a ldr r2, [r3, #96] @ 0x60 8003c3c: 4b19 ldr r3, [pc, #100] @ (8003ca4 ) 8003c3e: 2101 movs r1, #1 8003c40: 438a bics r2, r1 8003c42: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003c44: f7fd fe10 bl 8001868 8003c48: 0003 movs r3, r0 8003c4a: 613b str r3, [r7, #16] /* Wait till LSI is disabled */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8003c4c: e008 b.n 8003c60 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003c4e: f7fd fe0b bl 8001868 8003c52: 0002 movs r2, r0 8003c54: 693b ldr r3, [r7, #16] 8003c56: 1ad3 subs r3, r2, r3 8003c58: 2b02 cmp r3, #2 8003c5a: d901 bls.n 8003c60 { return HAL_TIMEOUT; 8003c5c: 2303 movs r3, #3 8003c5e: e188 b.n 8003f72 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8003c60: 4b10 ldr r3, [pc, #64] @ (8003ca4 ) 8003c62: 6e1b ldr r3, [r3, #96] @ 0x60 8003c64: 2202 movs r2, #2 8003c66: 4013 ands r3, r2 8003c68: d1f1 bne.n 8003c4e } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8003c6a: 687b ldr r3, [r7, #4] 8003c6c: 681b ldr r3, [r3, #0] 8003c6e: 2204 movs r2, #4 8003c70: 4013 ands r3, r2 8003c72: d100 bne.n 8003c76 8003c74: e0c6 b.n 8003e04 { FlagStatus pwrclkchanged = RESET; 8003c76: 231f movs r3, #31 8003c78: 18fb adds r3, r7, r3 8003c7a: 2200 movs r2, #0 8003c7c: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* When the LSE is used as system clock, it is not allowed disable it */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) 8003c7e: 4b09 ldr r3, [pc, #36] @ (8003ca4 ) 8003c80: 689b ldr r3, [r3, #8] 8003c82: 2238 movs r2, #56 @ 0x38 8003c84: 4013 ands r3, r2 8003c86: 2b20 cmp r3, #32 8003c88: d11e bne.n 8003cc8 { if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)) 8003c8a: 4b06 ldr r3, [pc, #24] @ (8003ca4 ) 8003c8c: 6ddb ldr r3, [r3, #92] @ 0x5c 8003c8e: 2202 movs r2, #2 8003c90: 4013 ands r3, r2 8003c92: d100 bne.n 8003c96 8003c94: e0b6 b.n 8003e04 8003c96: 687b ldr r3, [r7, #4] 8003c98: 689b ldr r3, [r3, #8] 8003c9a: 2b00 cmp r3, #0 8003c9c: d000 beq.n 8003ca0 8003c9e: e0b1 b.n 8003e04 { return HAL_ERROR; 8003ca0: 2301 movs r3, #1 8003ca2: e166 b.n 8003f72 8003ca4: 40021000 .word 0x40021000 8003ca8: fffeffff .word 0xfffeffff 8003cac: fffbffff .word 0xfffbffff 8003cb0: ffff80ff .word 0xffff80ff 8003cb4: ffffc7ff .word 0xffffc7ff 8003cb8: 00f42400 .word 0x00f42400 8003cbc: 20000000 .word 0x20000000 8003cc0: 20000104 .word 0x20000104 8003cc4: fffffeff .word 0xfffffeff } else { /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 8003cc8: 4bac ldr r3, [pc, #688] @ (8003f7c ) 8003cca: 6bda ldr r2, [r3, #60] @ 0x3c 8003ccc: 2380 movs r3, #128 @ 0x80 8003cce: 055b lsls r3, r3, #21 8003cd0: 4013 ands r3, r2 8003cd2: d101 bne.n 8003cd8 8003cd4: 2301 movs r3, #1 8003cd6: e000 b.n 8003cda 8003cd8: 2300 movs r3, #0 8003cda: 2b00 cmp r3, #0 8003cdc: d011 beq.n 8003d02 { __HAL_RCC_PWR_CLK_ENABLE(); 8003cde: 4ba7 ldr r3, [pc, #668] @ (8003f7c ) 8003ce0: 6bda ldr r2, [r3, #60] @ 0x3c 8003ce2: 4ba6 ldr r3, [pc, #664] @ (8003f7c ) 8003ce4: 2180 movs r1, #128 @ 0x80 8003ce6: 0549 lsls r1, r1, #21 8003ce8: 430a orrs r2, r1 8003cea: 63da str r2, [r3, #60] @ 0x3c 8003cec: 4ba3 ldr r3, [pc, #652] @ (8003f7c ) 8003cee: 6bda ldr r2, [r3, #60] @ 0x3c 8003cf0: 2380 movs r3, #128 @ 0x80 8003cf2: 055b lsls r3, r3, #21 8003cf4: 4013 ands r3, r2 8003cf6: 60fb str r3, [r7, #12] 8003cf8: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8003cfa: 231f movs r3, #31 8003cfc: 18fb adds r3, r7, r3 8003cfe: 2201 movs r2, #1 8003d00: 701a strb r2, [r3, #0] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003d02: 4b9f ldr r3, [pc, #636] @ (8003f80 ) 8003d04: 681a ldr r2, [r3, #0] 8003d06: 2380 movs r3, #128 @ 0x80 8003d08: 005b lsls r3, r3, #1 8003d0a: 4013 ands r3, r2 8003d0c: d11a bne.n 8003d44 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8003d0e: 4b9c ldr r3, [pc, #624] @ (8003f80 ) 8003d10: 681a ldr r2, [r3, #0] 8003d12: 4b9b ldr r3, [pc, #620] @ (8003f80 ) 8003d14: 2180 movs r1, #128 @ 0x80 8003d16: 0049 lsls r1, r1, #1 8003d18: 430a orrs r2, r1 8003d1a: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003d1c: f7fd fda4 bl 8001868 8003d20: 0003 movs r3, r0 8003d22: 613b str r3, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003d24: e008 b.n 8003d38 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003d26: f7fd fd9f bl 8001868 8003d2a: 0002 movs r2, r0 8003d2c: 693b ldr r3, [r7, #16] 8003d2e: 1ad3 subs r3, r2, r3 8003d30: 2b02 cmp r3, #2 8003d32: d901 bls.n 8003d38 { return HAL_TIMEOUT; 8003d34: 2303 movs r3, #3 8003d36: e11c b.n 8003f72 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003d38: 4b91 ldr r3, [pc, #580] @ (8003f80 ) 8003d3a: 681a ldr r2, [r3, #0] 8003d3c: 2380 movs r3, #128 @ 0x80 8003d3e: 005b lsls r3, r3, #1 8003d40: 4013 ands r3, r2 8003d42: d0f0 beq.n 8003d26 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8003d44: 687b ldr r3, [r7, #4] 8003d46: 689b ldr r3, [r3, #8] 8003d48: 2b01 cmp r3, #1 8003d4a: d106 bne.n 8003d5a 8003d4c: 4b8b ldr r3, [pc, #556] @ (8003f7c ) 8003d4e: 6dda ldr r2, [r3, #92] @ 0x5c 8003d50: 4b8a ldr r3, [pc, #552] @ (8003f7c ) 8003d52: 2101 movs r1, #1 8003d54: 430a orrs r2, r1 8003d56: 65da str r2, [r3, #92] @ 0x5c 8003d58: e01c b.n 8003d94 8003d5a: 687b ldr r3, [r7, #4] 8003d5c: 689b ldr r3, [r3, #8] 8003d5e: 2b05 cmp r3, #5 8003d60: d10c bne.n 8003d7c 8003d62: 4b86 ldr r3, [pc, #536] @ (8003f7c ) 8003d64: 6dda ldr r2, [r3, #92] @ 0x5c 8003d66: 4b85 ldr r3, [pc, #532] @ (8003f7c ) 8003d68: 2104 movs r1, #4 8003d6a: 430a orrs r2, r1 8003d6c: 65da str r2, [r3, #92] @ 0x5c 8003d6e: 4b83 ldr r3, [pc, #524] @ (8003f7c ) 8003d70: 6dda ldr r2, [r3, #92] @ 0x5c 8003d72: 4b82 ldr r3, [pc, #520] @ (8003f7c ) 8003d74: 2101 movs r1, #1 8003d76: 430a orrs r2, r1 8003d78: 65da str r2, [r3, #92] @ 0x5c 8003d7a: e00b b.n 8003d94 8003d7c: 4b7f ldr r3, [pc, #508] @ (8003f7c ) 8003d7e: 6dda ldr r2, [r3, #92] @ 0x5c 8003d80: 4b7e ldr r3, [pc, #504] @ (8003f7c ) 8003d82: 2101 movs r1, #1 8003d84: 438a bics r2, r1 8003d86: 65da str r2, [r3, #92] @ 0x5c 8003d88: 4b7c ldr r3, [pc, #496] @ (8003f7c ) 8003d8a: 6dda ldr r2, [r3, #92] @ 0x5c 8003d8c: 4b7b ldr r3, [pc, #492] @ (8003f7c ) 8003d8e: 2104 movs r1, #4 8003d90: 438a bics r2, r1 8003d92: 65da str r2, [r3, #92] @ 0x5c /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8003d94: 687b ldr r3, [r7, #4] 8003d96: 689b ldr r3, [r3, #8] 8003d98: 2b00 cmp r3, #0 8003d9a: d014 beq.n 8003dc6 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003d9c: f7fd fd64 bl 8001868 8003da0: 0003 movs r3, r0 8003da2: 613b str r3, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003da4: e009 b.n 8003dba { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003da6: f7fd fd5f bl 8001868 8003daa: 0002 movs r2, r0 8003dac: 693b ldr r3, [r7, #16] 8003dae: 1ad3 subs r3, r2, r3 8003db0: 4a74 ldr r2, [pc, #464] @ (8003f84 ) 8003db2: 4293 cmp r3, r2 8003db4: d901 bls.n 8003dba { return HAL_TIMEOUT; 8003db6: 2303 movs r3, #3 8003db8: e0db b.n 8003f72 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003dba: 4b70 ldr r3, [pc, #448] @ (8003f7c ) 8003dbc: 6ddb ldr r3, [r3, #92] @ 0x5c 8003dbe: 2202 movs r2, #2 8003dc0: 4013 ands r3, r2 8003dc2: d0f0 beq.n 8003da6 8003dc4: e013 b.n 8003dee } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003dc6: f7fd fd4f bl 8001868 8003dca: 0003 movs r3, r0 8003dcc: 613b str r3, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8003dce: e009 b.n 8003de4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003dd0: f7fd fd4a bl 8001868 8003dd4: 0002 movs r2, r0 8003dd6: 693b ldr r3, [r7, #16] 8003dd8: 1ad3 subs r3, r2, r3 8003dda: 4a6a ldr r2, [pc, #424] @ (8003f84 ) 8003ddc: 4293 cmp r3, r2 8003dde: d901 bls.n 8003de4 { return HAL_TIMEOUT; 8003de0: 2303 movs r3, #3 8003de2: e0c6 b.n 8003f72 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8003de4: 4b65 ldr r3, [pc, #404] @ (8003f7c ) 8003de6: 6ddb ldr r3, [r3, #92] @ 0x5c 8003de8: 2202 movs r2, #2 8003dea: 4013 ands r3, r2 8003dec: d1f0 bne.n 8003dd0 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8003dee: 231f movs r3, #31 8003df0: 18fb adds r3, r7, r3 8003df2: 781b ldrb r3, [r3, #0] 8003df4: 2b01 cmp r3, #1 8003df6: d105 bne.n 8003e04 { __HAL_RCC_PWR_CLK_DISABLE(); 8003df8: 4b60 ldr r3, [pc, #384] @ (8003f7c ) 8003dfa: 6bda ldr r2, [r3, #60] @ 0x3c 8003dfc: 4b5f ldr r3, [pc, #380] @ (8003f7c ) 8003dfe: 4962 ldr r1, [pc, #392] @ (8003f88 ) 8003e00: 400a ands r2, r1 8003e02: 63da str r2, [r3, #60] @ 0x3c #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 8003e04: 687b ldr r3, [r7, #4] 8003e06: 69db ldr r3, [r3, #28] 8003e08: 2b00 cmp r3, #0 8003e0a: d100 bne.n 8003e0e 8003e0c: e0b0 b.n 8003f70 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8003e0e: 4b5b ldr r3, [pc, #364] @ (8003f7c ) 8003e10: 689b ldr r3, [r3, #8] 8003e12: 2238 movs r2, #56 @ 0x38 8003e14: 4013 ands r3, r2 8003e16: 2b10 cmp r3, #16 8003e18: d100 bne.n 8003e1c 8003e1a: e078 b.n 8003f0e { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 8003e1c: 687b ldr r3, [r7, #4] 8003e1e: 69db ldr r3, [r3, #28] 8003e20: 2b02 cmp r3, #2 8003e22: d153 bne.n 8003ecc assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); #endif /* RCC_PLLQ_SUPPORT */ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003e24: 4b55 ldr r3, [pc, #340] @ (8003f7c ) 8003e26: 681a ldr r2, [r3, #0] 8003e28: 4b54 ldr r3, [pc, #336] @ (8003f7c ) 8003e2a: 4958 ldr r1, [pc, #352] @ (8003f8c ) 8003e2c: 400a ands r2, r1 8003e2e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003e30: f7fd fd1a bl 8001868 8003e34: 0003 movs r3, r0 8003e36: 613b str r3, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003e38: e008 b.n 8003e4c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003e3a: f7fd fd15 bl 8001868 8003e3e: 0002 movs r2, r0 8003e40: 693b ldr r3, [r7, #16] 8003e42: 1ad3 subs r3, r2, r3 8003e44: 2b02 cmp r3, #2 8003e46: d901 bls.n 8003e4c { return HAL_TIMEOUT; 8003e48: 2303 movs r3, #3 8003e4a: e092 b.n 8003f72 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003e4c: 4b4b ldr r3, [pc, #300] @ (8003f7c ) 8003e4e: 681a ldr r2, [r3, #0] 8003e50: 2380 movs r3, #128 @ 0x80 8003e52: 049b lsls r3, r3, #18 8003e54: 4013 ands r3, r2 8003e56: d1f0 bne.n 8003e3a RCC_OscInitStruct->PLL.PLLN, RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); #else /* !RCC_PLLQ_SUPPORT */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8003e58: 4b48 ldr r3, [pc, #288] @ (8003f7c ) 8003e5a: 68db ldr r3, [r3, #12] 8003e5c: 4a4c ldr r2, [pc, #304] @ (8003f90 ) 8003e5e: 4013 ands r3, r2 8003e60: 0019 movs r1, r3 8003e62: 687b ldr r3, [r7, #4] 8003e64: 6a1a ldr r2, [r3, #32] 8003e66: 687b ldr r3, [r7, #4] 8003e68: 6a5b ldr r3, [r3, #36] @ 0x24 8003e6a: 431a orrs r2, r3 8003e6c: 687b ldr r3, [r7, #4] 8003e6e: 6a9b ldr r3, [r3, #40] @ 0x28 8003e70: 021b lsls r3, r3, #8 8003e72: 431a orrs r2, r3 8003e74: 687b ldr r3, [r7, #4] 8003e76: 6adb ldr r3, [r3, #44] @ 0x2c 8003e78: 431a orrs r2, r3 8003e7a: 687b ldr r3, [r7, #4] 8003e7c: 6b1b ldr r3, [r3, #48] @ 0x30 8003e7e: 431a orrs r2, r3 8003e80: 4b3e ldr r3, [pc, #248] @ (8003f7c ) 8003e82: 430a orrs r2, r1 8003e84: 60da str r2, [r3, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLR); #endif /* RCC_PLLQ_SUPPORT */ /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8003e86: 4b3d ldr r3, [pc, #244] @ (8003f7c ) 8003e88: 681a ldr r2, [r3, #0] 8003e8a: 4b3c ldr r3, [pc, #240] @ (8003f7c ) 8003e8c: 2180 movs r1, #128 @ 0x80 8003e8e: 0449 lsls r1, r1, #17 8003e90: 430a orrs r2, r1 8003e92: 601a str r2, [r3, #0] /* Enable PLLR Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK); 8003e94: 4b39 ldr r3, [pc, #228] @ (8003f7c ) 8003e96: 68da ldr r2, [r3, #12] 8003e98: 4b38 ldr r3, [pc, #224] @ (8003f7c ) 8003e9a: 2180 movs r1, #128 @ 0x80 8003e9c: 0549 lsls r1, r1, #21 8003e9e: 430a orrs r2, r1 8003ea0: 60da str r2, [r3, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003ea2: f7fd fce1 bl 8001868 8003ea6: 0003 movs r3, r0 8003ea8: 613b str r3, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8003eaa: e008 b.n 8003ebe { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003eac: f7fd fcdc bl 8001868 8003eb0: 0002 movs r2, r0 8003eb2: 693b ldr r3, [r7, #16] 8003eb4: 1ad3 subs r3, r2, r3 8003eb6: 2b02 cmp r3, #2 8003eb8: d901 bls.n 8003ebe { return HAL_TIMEOUT; 8003eba: 2303 movs r3, #3 8003ebc: e059 b.n 8003f72 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8003ebe: 4b2f ldr r3, [pc, #188] @ (8003f7c ) 8003ec0: 681a ldr r2, [r3, #0] 8003ec2: 2380 movs r3, #128 @ 0x80 8003ec4: 049b lsls r3, r3, #18 8003ec6: 4013 ands r3, r2 8003ec8: d0f0 beq.n 8003eac 8003eca: e051 b.n 8003f70 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003ecc: 4b2b ldr r3, [pc, #172] @ (8003f7c ) 8003ece: 681a ldr r2, [r3, #0] 8003ed0: 4b2a ldr r3, [pc, #168] @ (8003f7c ) 8003ed2: 492e ldr r1, [pc, #184] @ (8003f8c ) 8003ed4: 400a ands r2, r1 8003ed6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003ed8: f7fd fcc6 bl 8001868 8003edc: 0003 movs r3, r0 8003ede: 613b str r3, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003ee0: e008 b.n 8003ef4 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003ee2: f7fd fcc1 bl 8001868 8003ee6: 0002 movs r2, r0 8003ee8: 693b ldr r3, [r7, #16] 8003eea: 1ad3 subs r3, r2, r3 8003eec: 2b02 cmp r3, #2 8003eee: d901 bls.n 8003ef4 { return HAL_TIMEOUT; 8003ef0: 2303 movs r3, #3 8003ef2: e03e b.n 8003f72 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003ef4: 4b21 ldr r3, [pc, #132] @ (8003f7c ) 8003ef6: 681a ldr r2, [r3, #0] 8003ef8: 2380 movs r3, #128 @ 0x80 8003efa: 049b lsls r3, r3, #18 8003efc: 4013 ands r3, r2 8003efe: d1f0 bne.n 8003ee2 } /* Unselect main PLL clock source and disable main PLL outputs to save power */ #if defined(RCC_PLLQ_SUPPORT) RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN); #else RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN); 8003f00: 4b1e ldr r3, [pc, #120] @ (8003f7c ) 8003f02: 68da ldr r2, [r3, #12] 8003f04: 4b1d ldr r3, [pc, #116] @ (8003f7c ) 8003f06: 4923 ldr r1, [pc, #140] @ (8003f94 ) 8003f08: 400a ands r2, r1 8003f0a: 60da str r2, [r3, #12] 8003f0c: e030 b.n 8003f70 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8003f0e: 687b ldr r3, [r7, #4] 8003f10: 69db ldr r3, [r3, #28] 8003f12: 2b01 cmp r3, #1 8003f14: d101 bne.n 8003f1a { return HAL_ERROR; 8003f16: 2301 movs r3, #1 8003f18: e02b b.n 8003f72 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; 8003f1a: 4b18 ldr r3, [pc, #96] @ (8003f7c ) 8003f1c: 68db ldr r3, [r3, #12] 8003f1e: 617b str r3, [r7, #20] if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003f20: 697b ldr r3, [r7, #20] 8003f22: 2203 movs r2, #3 8003f24: 401a ands r2, r3 8003f26: 687b ldr r3, [r7, #4] 8003f28: 6a1b ldr r3, [r3, #32] 8003f2a: 429a cmp r2, r3 8003f2c: d11e bne.n 8003f6c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 8003f2e: 697b ldr r3, [r7, #20] 8003f30: 2270 movs r2, #112 @ 0x70 8003f32: 401a ands r2, r3 8003f34: 687b ldr r3, [r7, #4] 8003f36: 6a5b ldr r3, [r3, #36] @ 0x24 if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003f38: 429a cmp r2, r3 8003f3a: d117 bne.n 8003f6c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 8003f3c: 697a ldr r2, [r7, #20] 8003f3e: 23fe movs r3, #254 @ 0xfe 8003f40: 01db lsls r3, r3, #7 8003f42: 401a ands r2, r3 8003f44: 687b ldr r3, [r7, #4] 8003f46: 6a9b ldr r3, [r3, #40] @ 0x28 8003f48: 021b lsls r3, r3, #8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 8003f4a: 429a cmp r2, r3 8003f4c: d10e bne.n 8003f6c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 8003f4e: 697a ldr r2, [r7, #20] 8003f50: 23f8 movs r3, #248 @ 0xf8 8003f52: 039b lsls r3, r3, #14 8003f54: 401a ands r2, r3 8003f56: 687b ldr r3, [r7, #4] 8003f58: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 8003f5a: 429a cmp r2, r3 8003f5c: d106 bne.n 8003f6c #if defined (RCC_PLLQ_SUPPORT) (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || #endif /* RCC_PLLQ_SUPPORT */ (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) 8003f5e: 697b ldr r3, [r7, #20] 8003f60: 0f5b lsrs r3, r3, #29 8003f62: 075a lsls r2, r3, #29 8003f64: 687b ldr r3, [r7, #4] 8003f66: 6b1b ldr r3, [r3, #48] @ 0x30 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 8003f68: 429a cmp r2, r3 8003f6a: d001 beq.n 8003f70 { return HAL_ERROR; 8003f6c: 2301 movs r3, #1 8003f6e: e000 b.n 8003f72 } } } } return HAL_OK; 8003f70: 2300 movs r3, #0 } 8003f72: 0018 movs r0, r3 8003f74: 46bd mov sp, r7 8003f76: b008 add sp, #32 8003f78: bd80 pop {r7, pc} 8003f7a: 46c0 nop @ (mov r8, r8) 8003f7c: 40021000 .word 0x40021000 8003f80: 40007000 .word 0x40007000 8003f84: 00001388 .word 0x00001388 8003f88: efffffff .word 0xefffffff 8003f8c: feffffff .word 0xfeffffff 8003f90: 1fc1808c .word 0x1fc1808c 8003f94: effefffc .word 0xeffefffc 08003f98 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003f98: b580 push {r7, lr} 8003f9a: b084 sub sp, #16 8003f9c: af00 add r7, sp, #0 8003f9e: 6078 str r0, [r7, #4] 8003fa0: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8003fa2: 687b ldr r3, [r7, #4] 8003fa4: 2b00 cmp r3, #0 8003fa6: d101 bne.n 8003fac { return HAL_ERROR; 8003fa8: 2301 movs r3, #1 8003faa: e0e9 b.n 8004180 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8003fac: 4b76 ldr r3, [pc, #472] @ (8004188 ) 8003fae: 681b ldr r3, [r3, #0] 8003fb0: 2207 movs r2, #7 8003fb2: 4013 ands r3, r2 8003fb4: 683a ldr r2, [r7, #0] 8003fb6: 429a cmp r2, r3 8003fb8: d91e bls.n 8003ff8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003fba: 4b73 ldr r3, [pc, #460] @ (8004188 ) 8003fbc: 681b ldr r3, [r3, #0] 8003fbe: 2207 movs r2, #7 8003fc0: 4393 bics r3, r2 8003fc2: 0019 movs r1, r3 8003fc4: 4b70 ldr r3, [pc, #448] @ (8004188 ) 8003fc6: 683a ldr r2, [r7, #0] 8003fc8: 430a orrs r2, r1 8003fca: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 8003fcc: f7fd fc4c bl 8001868 8003fd0: 0003 movs r3, r0 8003fd2: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8003fd4: e009 b.n 8003fea { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003fd6: f7fd fc47 bl 8001868 8003fda: 0002 movs r2, r0 8003fdc: 68fb ldr r3, [r7, #12] 8003fde: 1ad3 subs r3, r2, r3 8003fe0: 4a6a ldr r2, [pc, #424] @ (800418c ) 8003fe2: 4293 cmp r3, r2 8003fe4: d901 bls.n 8003fea { return HAL_TIMEOUT; 8003fe6: 2303 movs r3, #3 8003fe8: e0ca b.n 8004180 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8003fea: 4b67 ldr r3, [pc, #412] @ (8004188 ) 8003fec: 681b ldr r3, [r3, #0] 8003fee: 2207 movs r2, #7 8003ff0: 4013 ands r3, r2 8003ff2: 683a ldr r2, [r7, #0] 8003ff4: 429a cmp r2, r3 8003ff6: d1ee bne.n 8003fd6 } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003ff8: 687b ldr r3, [r7, #4] 8003ffa: 681b ldr r3, [r3, #0] 8003ffc: 2202 movs r2, #2 8003ffe: 4013 ands r3, r2 8004000: d015 beq.n 800402e { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004002: 687b ldr r3, [r7, #4] 8004004: 681b ldr r3, [r3, #0] 8004006: 2204 movs r2, #4 8004008: 4013 ands r3, r2 800400a: d006 beq.n 800401a { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 800400c: 4b60 ldr r3, [pc, #384] @ (8004190 ) 800400e: 689a ldr r2, [r3, #8] 8004010: 4b5f ldr r3, [pc, #380] @ (8004190 ) 8004012: 21e0 movs r1, #224 @ 0xe0 8004014: 01c9 lsls r1, r1, #7 8004016: 430a orrs r2, r1 8004018: 609a str r2, [r3, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800401a: 4b5d ldr r3, [pc, #372] @ (8004190 ) 800401c: 689b ldr r3, [r3, #8] 800401e: 4a5d ldr r2, [pc, #372] @ (8004194 ) 8004020: 4013 ands r3, r2 8004022: 0019 movs r1, r3 8004024: 687b ldr r3, [r7, #4] 8004026: 689a ldr r2, [r3, #8] 8004028: 4b59 ldr r3, [pc, #356] @ (8004190 ) 800402a: 430a orrs r2, r1 800402c: 609a str r2, [r3, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800402e: 687b ldr r3, [r7, #4] 8004030: 681b ldr r3, [r3, #0] 8004032: 2201 movs r2, #1 8004034: 4013 ands r3, r2 8004036: d057 beq.n 80040e8 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004038: 687b ldr r3, [r7, #4] 800403a: 685b ldr r3, [r3, #4] 800403c: 2b01 cmp r3, #1 800403e: d107 bne.n 8004050 { /* Check the HSE ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8004040: 4b53 ldr r3, [pc, #332] @ (8004190 ) 8004042: 681a ldr r2, [r3, #0] 8004044: 2380 movs r3, #128 @ 0x80 8004046: 029b lsls r3, r3, #10 8004048: 4013 ands r3, r2 800404a: d12b bne.n 80040a4 { return HAL_ERROR; 800404c: 2301 movs r3, #1 800404e: e097 b.n 8004180 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8004050: 687b ldr r3, [r7, #4] 8004052: 685b ldr r3, [r3, #4] 8004054: 2b02 cmp r3, #2 8004056: d107 bne.n 8004068 { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8004058: 4b4d ldr r3, [pc, #308] @ (8004190 ) 800405a: 681a ldr r2, [r3, #0] 800405c: 2380 movs r3, #128 @ 0x80 800405e: 049b lsls r3, r3, #18 8004060: 4013 ands r3, r2 8004062: d11f bne.n 80040a4 { return HAL_ERROR; 8004064: 2301 movs r3, #1 8004066: e08b b.n 8004180 } } /* HSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) 8004068: 687b ldr r3, [r7, #4] 800406a: 685b ldr r3, [r3, #4] 800406c: 2b00 cmp r3, #0 800406e: d107 bne.n 8004080 { /* Check the HSI ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8004070: 4b47 ldr r3, [pc, #284] @ (8004190 ) 8004072: 681a ldr r2, [r3, #0] 8004074: 2380 movs r3, #128 @ 0x80 8004076: 00db lsls r3, r3, #3 8004078: 4013 ands r3, r2 800407a: d113 bne.n 80040a4 { return HAL_ERROR; 800407c: 2301 movs r3, #1 800407e: e07f b.n 8004180 } } /* LSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) 8004080: 687b ldr r3, [r7, #4] 8004082: 685b ldr r3, [r3, #4] 8004084: 2b03 cmp r3, #3 8004086: d106 bne.n 8004096 { /* Check the LSI ready flag */ if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8004088: 4b41 ldr r3, [pc, #260] @ (8004190 ) 800408a: 6e1b ldr r3, [r3, #96] @ 0x60 800408c: 2202 movs r2, #2 800408e: 4013 ands r3, r2 8004090: d108 bne.n 80040a4 { return HAL_ERROR; 8004092: 2301 movs r3, #1 8004094: e074 b.n 8004180 } /* LSE is selected as System Clock Source */ else { /* Check the LSE ready flag */ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8004096: 4b3e ldr r3, [pc, #248] @ (8004190 ) 8004098: 6ddb ldr r3, [r3, #92] @ 0x5c 800409a: 2202 movs r2, #2 800409c: 4013 ands r3, r2 800409e: d101 bne.n 80040a4 { return HAL_ERROR; 80040a0: 2301 movs r3, #1 80040a2: e06d b.n 8004180 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 80040a4: 4b3a ldr r3, [pc, #232] @ (8004190 ) 80040a6: 689b ldr r3, [r3, #8] 80040a8: 2207 movs r2, #7 80040aa: 4393 bics r3, r2 80040ac: 0019 movs r1, r3 80040ae: 687b ldr r3, [r7, #4] 80040b0: 685a ldr r2, [r3, #4] 80040b2: 4b37 ldr r3, [pc, #220] @ (8004190 ) 80040b4: 430a orrs r2, r1 80040b6: 609a str r2, [r3, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80040b8: f7fd fbd6 bl 8001868 80040bc: 0003 movs r3, r0 80040be: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80040c0: e009 b.n 80040d6 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80040c2: f7fd fbd1 bl 8001868 80040c6: 0002 movs r2, r0 80040c8: 68fb ldr r3, [r7, #12] 80040ca: 1ad3 subs r3, r2, r3 80040cc: 4a2f ldr r2, [pc, #188] @ (800418c ) 80040ce: 4293 cmp r3, r2 80040d0: d901 bls.n 80040d6 { return HAL_TIMEOUT; 80040d2: 2303 movs r3, #3 80040d4: e054 b.n 8004180 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80040d6: 4b2e ldr r3, [pc, #184] @ (8004190 ) 80040d8: 689b ldr r3, [r3, #8] 80040da: 2238 movs r2, #56 @ 0x38 80040dc: 401a ands r2, r3 80040de: 687b ldr r3, [r7, #4] 80040e0: 685b ldr r3, [r3, #4] 80040e2: 00db lsls r3, r3, #3 80040e4: 429a cmp r2, r3 80040e6: d1ec bne.n 80040c2 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80040e8: 4b27 ldr r3, [pc, #156] @ (8004188 ) 80040ea: 681b ldr r3, [r3, #0] 80040ec: 2207 movs r2, #7 80040ee: 4013 ands r3, r2 80040f0: 683a ldr r2, [r7, #0] 80040f2: 429a cmp r2, r3 80040f4: d21e bcs.n 8004134 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80040f6: 4b24 ldr r3, [pc, #144] @ (8004188 ) 80040f8: 681b ldr r3, [r3, #0] 80040fa: 2207 movs r2, #7 80040fc: 4393 bics r3, r2 80040fe: 0019 movs r1, r3 8004100: 4b21 ldr r3, [pc, #132] @ (8004188 ) 8004102: 683a ldr r2, [r7, #0] 8004104: 430a orrs r2, r1 8004106: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 8004108: f7fd fbae bl 8001868 800410c: 0003 movs r3, r0 800410e: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8004110: e009 b.n 8004126 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8004112: f7fd fba9 bl 8001868 8004116: 0002 movs r2, r0 8004118: 68fb ldr r3, [r7, #12] 800411a: 1ad3 subs r3, r2, r3 800411c: 4a1b ldr r2, [pc, #108] @ (800418c ) 800411e: 4293 cmp r3, r2 8004120: d901 bls.n 8004126 { return HAL_TIMEOUT; 8004122: 2303 movs r3, #3 8004124: e02c b.n 8004180 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8004126: 4b18 ldr r3, [pc, #96] @ (8004188 ) 8004128: 681b ldr r3, [r3, #0] 800412a: 2207 movs r2, #7 800412c: 4013 ands r3, r2 800412e: 683a ldr r2, [r7, #0] 8004130: 429a cmp r2, r3 8004132: d1ee bne.n 8004112 } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004134: 687b ldr r3, [r7, #4] 8004136: 681b ldr r3, [r3, #0] 8004138: 2204 movs r2, #4 800413a: 4013 ands r3, r2 800413c: d009 beq.n 8004152 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 800413e: 4b14 ldr r3, [pc, #80] @ (8004190 ) 8004140: 689b ldr r3, [r3, #8] 8004142: 4a15 ldr r2, [pc, #84] @ (8004198 ) 8004144: 4013 ands r3, r2 8004146: 0019 movs r1, r3 8004148: 687b ldr r3, [r7, #4] 800414a: 68da ldr r2, [r3, #12] 800414c: 4b10 ldr r3, [pc, #64] @ (8004190 ) 800414e: 430a orrs r2, r1 8004150: 609a str r2, [r3, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); 8004152: f000 f829 bl 80041a8 8004156: 0001 movs r1, r0 8004158: 4b0d ldr r3, [pc, #52] @ (8004190 ) 800415a: 689b ldr r3, [r3, #8] 800415c: 0a1b lsrs r3, r3, #8 800415e: 220f movs r2, #15 8004160: 401a ands r2, r3 8004162: 4b0e ldr r3, [pc, #56] @ (800419c ) 8004164: 0092 lsls r2, r2, #2 8004166: 58d3 ldr r3, [r2, r3] 8004168: 221f movs r2, #31 800416a: 4013 ands r3, r2 800416c: 000a movs r2, r1 800416e: 40da lsrs r2, r3 8004170: 4b0b ldr r3, [pc, #44] @ (80041a0 ) 8004172: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); 8004174: 4b0b ldr r3, [pc, #44] @ (80041a4 ) 8004176: 681b ldr r3, [r3, #0] 8004178: 0018 movs r0, r3 800417a: f7fd fb19 bl 80017b0 800417e: 0003 movs r3, r0 } 8004180: 0018 movs r0, r3 8004182: 46bd mov sp, r7 8004184: b004 add sp, #16 8004186: bd80 pop {r7, pc} 8004188: 40022000 .word 0x40022000 800418c: 00001388 .word 0x00001388 8004190: 40021000 .word 0x40021000 8004194: fffff0ff .word 0xfffff0ff 8004198: ffff8fff .word 0xffff8fff 800419c: 08006060 .word 0x08006060 80041a0: 20000000 .word 0x20000000 80041a4: 20000104 .word 0x20000104 080041a8 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80041a8: b580 push {r7, lr} 80041aa: b086 sub sp, #24 80041ac: af00 add r7, sp, #0 uint32_t pllvco, pllsource, pllr, pllm, hsidiv; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80041ae: 4b3c ldr r3, [pc, #240] @ (80042a0 ) 80041b0: 689b ldr r3, [r3, #8] 80041b2: 2238 movs r2, #56 @ 0x38 80041b4: 4013 ands r3, r2 80041b6: d10f bne.n 80041d8 { /* HSISYS can be derived for HSI16 */ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); 80041b8: 4b39 ldr r3, [pc, #228] @ (80042a0 ) 80041ba: 681b ldr r3, [r3, #0] 80041bc: 0adb lsrs r3, r3, #11 80041be: 2207 movs r2, #7 80041c0: 4013 ands r3, r2 80041c2: 2201 movs r2, #1 80041c4: 409a lsls r2, r3 80041c6: 0013 movs r3, r2 80041c8: 603b str r3, [r7, #0] /* HSI used as system clock source */ sysclockfreq = (HSI_VALUE / hsidiv); 80041ca: 6839 ldr r1, [r7, #0] 80041cc: 4835 ldr r0, [pc, #212] @ (80042a4 ) 80041ce: f7fb ff97 bl 8000100 <__udivsi3> 80041d2: 0003 movs r3, r0 80041d4: 613b str r3, [r7, #16] 80041d6: e05d b.n 8004294 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80041d8: 4b31 ldr r3, [pc, #196] @ (80042a0 ) 80041da: 689b ldr r3, [r3, #8] 80041dc: 2238 movs r2, #56 @ 0x38 80041de: 4013 ands r3, r2 80041e0: 2b08 cmp r3, #8 80041e2: d102 bne.n 80041ea { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 80041e4: 4b30 ldr r3, [pc, #192] @ (80042a8 ) 80041e6: 613b str r3, [r7, #16] 80041e8: e054 b.n 8004294 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80041ea: 4b2d ldr r3, [pc, #180] @ (80042a0 ) 80041ec: 689b ldr r3, [r3, #8] 80041ee: 2238 movs r2, #56 @ 0x38 80041f0: 4013 ands r3, r2 80041f2: 2b10 cmp r3, #16 80041f4: d138 bne.n 8004268 /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 80041f6: 4b2a ldr r3, [pc, #168] @ (80042a0 ) 80041f8: 68db ldr r3, [r3, #12] 80041fa: 2203 movs r2, #3 80041fc: 4013 ands r3, r2 80041fe: 60fb str r3, [r7, #12] pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8004200: 4b27 ldr r3, [pc, #156] @ (80042a0 ) 8004202: 68db ldr r3, [r3, #12] 8004204: 091b lsrs r3, r3, #4 8004206: 2207 movs r2, #7 8004208: 4013 ands r3, r2 800420a: 3301 adds r3, #1 800420c: 60bb str r3, [r7, #8] switch (pllsource) 800420e: 68fb ldr r3, [r7, #12] 8004210: 2b03 cmp r3, #3 8004212: d10d bne.n 8004230 { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8004214: 68b9 ldr r1, [r7, #8] 8004216: 4824 ldr r0, [pc, #144] @ (80042a8 ) 8004218: f7fb ff72 bl 8000100 <__udivsi3> 800421c: 0003 movs r3, r0 800421e: 0019 movs r1, r3 8004220: 4b1f ldr r3, [pc, #124] @ (80042a0 ) 8004222: 68db ldr r3, [r3, #12] 8004224: 0a1b lsrs r3, r3, #8 8004226: 227f movs r2, #127 @ 0x7f 8004228: 4013 ands r3, r2 800422a: 434b muls r3, r1 800422c: 617b str r3, [r7, #20] break; 800422e: e00d b.n 800424c case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */ default: /* HSI16 used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ; 8004230: 68b9 ldr r1, [r7, #8] 8004232: 481c ldr r0, [pc, #112] @ (80042a4 ) 8004234: f7fb ff64 bl 8000100 <__udivsi3> 8004238: 0003 movs r3, r0 800423a: 0019 movs r1, r3 800423c: 4b18 ldr r3, [pc, #96] @ (80042a0 ) 800423e: 68db ldr r3, [r3, #12] 8004240: 0a1b lsrs r3, r3, #8 8004242: 227f movs r2, #127 @ 0x7f 8004244: 4013 ands r3, r2 8004246: 434b muls r3, r1 8004248: 617b str r3, [r7, #20] break; 800424a: 46c0 nop @ (mov r8, r8) } pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U); 800424c: 4b14 ldr r3, [pc, #80] @ (80042a0 ) 800424e: 68db ldr r3, [r3, #12] 8004250: 0f5b lsrs r3, r3, #29 8004252: 2207 movs r2, #7 8004254: 4013 ands r3, r2 8004256: 3301 adds r3, #1 8004258: 607b str r3, [r7, #4] sysclockfreq = pllvco / pllr; 800425a: 6879 ldr r1, [r7, #4] 800425c: 6978 ldr r0, [r7, #20] 800425e: f7fb ff4f bl 8000100 <__udivsi3> 8004262: 0003 movs r3, r0 8004264: 613b str r3, [r7, #16] 8004266: e015 b.n 8004294 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) 8004268: 4b0d ldr r3, [pc, #52] @ (80042a0 ) 800426a: 689b ldr r3, [r3, #8] 800426c: 2238 movs r2, #56 @ 0x38 800426e: 4013 ands r3, r2 8004270: 2b20 cmp r3, #32 8004272: d103 bne.n 800427c { /* LSE used as system clock source */ sysclockfreq = LSE_VALUE; 8004274: 2380 movs r3, #128 @ 0x80 8004276: 021b lsls r3, r3, #8 8004278: 613b str r3, [r7, #16] 800427a: e00b b.n 8004294 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) 800427c: 4b08 ldr r3, [pc, #32] @ (80042a0 ) 800427e: 689b ldr r3, [r3, #8] 8004280: 2238 movs r2, #56 @ 0x38 8004282: 4013 ands r3, r2 8004284: 2b18 cmp r3, #24 8004286: d103 bne.n 8004290 { /* LSI used as system clock source */ sysclockfreq = LSI_VALUE; 8004288: 23fa movs r3, #250 @ 0xfa 800428a: 01db lsls r3, r3, #7 800428c: 613b str r3, [r7, #16] 800428e: e001 b.n 8004294 } else { sysclockfreq = 0U; 8004290: 2300 movs r3, #0 8004292: 613b str r3, [r7, #16] } return sysclockfreq; 8004294: 693b ldr r3, [r7, #16] } 8004296: 0018 movs r0, r3 8004298: 46bd mov sp, r7 800429a: b006 add sp, #24 800429c: bd80 pop {r7, pc} 800429e: 46c0 nop @ (mov r8, r8) 80042a0: 40021000 .word 0x40021000 80042a4: 00f42400 .word 0x00f42400 80042a8: 007a1200 .word 0x007a1200 080042ac : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80042ac: b580 push {r7, lr} 80042ae: af00 add r7, sp, #0 return SystemCoreClock; 80042b0: 4b02 ldr r3, [pc, #8] @ (80042bc ) 80042b2: 681b ldr r3, [r3, #0] } 80042b4: 0018 movs r0, r3 80042b6: 46bd mov sp, r7 80042b8: bd80 pop {r7, pc} 80042ba: 46c0 nop @ (mov r8, r8) 80042bc: 20000000 .word 0x20000000 080042c0 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80042c0: b5b0 push {r4, r5, r7, lr} 80042c2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); 80042c4: f7ff fff2 bl 80042ac 80042c8: 0004 movs r4, r0 80042ca: f7ff fb49 bl 8003960 80042ce: 0003 movs r3, r0 80042d0: 0b1a lsrs r2, r3, #12 80042d2: 4b05 ldr r3, [pc, #20] @ (80042e8 ) 80042d4: 0092 lsls r2, r2, #2 80042d6: 58d3 ldr r3, [r2, r3] 80042d8: 221f movs r2, #31 80042da: 4013 ands r3, r2 80042dc: 40dc lsrs r4, r3 80042de: 0023 movs r3, r4 } 80042e0: 0018 movs r0, r3 80042e2: 46bd mov sp, r7 80042e4: bdb0 pop {r4, r5, r7, pc} 80042e6: 46c0 nop @ (mov r8, r8) 80042e8: 080060a0 .word 0x080060a0 080042ec : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80042ec: b580 push {r7, lr} 80042ee: b086 sub sp, #24 80042f0: af00 add r7, sp, #0 80042f2: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 80042f4: 2313 movs r3, #19 80042f6: 18fb adds r3, r7, r3 80042f8: 2200 movs r2, #0 80042fa: 701a strb r2, [r3, #0] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 80042fc: 2312 movs r3, #18 80042fe: 18fb adds r3, r7, r3 8004300: 2200 movs r2, #0 8004302: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8004304: 687b ldr r3, [r7, #4] 8004306: 681a ldr r2, [r3, #0] 8004308: 2380 movs r3, #128 @ 0x80 800430a: 029b lsls r3, r3, #10 800430c: 4013 ands r3, r2 800430e: d100 bne.n 8004312 8004310: e0a3 b.n 800445a { FlagStatus pwrclkchanged = RESET; 8004312: 2011 movs r0, #17 8004314: 183b adds r3, r7, r0 8004316: 2200 movs r2, #0 8004318: 701a strb r2, [r3, #0] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 800431a: 4b7f ldr r3, [pc, #508] @ (8004518 ) 800431c: 6bda ldr r2, [r3, #60] @ 0x3c 800431e: 2380 movs r3, #128 @ 0x80 8004320: 055b lsls r3, r3, #21 8004322: 4013 ands r3, r2 8004324: d110 bne.n 8004348 { __HAL_RCC_PWR_CLK_ENABLE(); 8004326: 4b7c ldr r3, [pc, #496] @ (8004518 ) 8004328: 6bda ldr r2, [r3, #60] @ 0x3c 800432a: 4b7b ldr r3, [pc, #492] @ (8004518 ) 800432c: 2180 movs r1, #128 @ 0x80 800432e: 0549 lsls r1, r1, #21 8004330: 430a orrs r2, r1 8004332: 63da str r2, [r3, #60] @ 0x3c 8004334: 4b78 ldr r3, [pc, #480] @ (8004518 ) 8004336: 6bda ldr r2, [r3, #60] @ 0x3c 8004338: 2380 movs r3, #128 @ 0x80 800433a: 055b lsls r3, r3, #21 800433c: 4013 ands r3, r2 800433e: 60bb str r3, [r7, #8] 8004340: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8004342: 183b adds r3, r7, r0 8004344: 2201 movs r2, #1 8004346: 701a strb r2, [r3, #0] } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8004348: 4b74 ldr r3, [pc, #464] @ (800451c ) 800434a: 681a ldr r2, [r3, #0] 800434c: 4b73 ldr r3, [pc, #460] @ (800451c ) 800434e: 2180 movs r1, #128 @ 0x80 8004350: 0049 lsls r1, r1, #1 8004352: 430a orrs r2, r1 8004354: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004356: f7fd fa87 bl 8001868 800435a: 0003 movs r3, r0 800435c: 60fb str r3, [r7, #12] while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800435e: e00b b.n 8004378 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004360: f7fd fa82 bl 8001868 8004364: 0002 movs r2, r0 8004366: 68fb ldr r3, [r7, #12] 8004368: 1ad3 subs r3, r2, r3 800436a: 2b02 cmp r3, #2 800436c: d904 bls.n 8004378 { ret = HAL_TIMEOUT; 800436e: 2313 movs r3, #19 8004370: 18fb adds r3, r7, r3 8004372: 2203 movs r2, #3 8004374: 701a strb r2, [r3, #0] break; 8004376: e005 b.n 8004384 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8004378: 4b68 ldr r3, [pc, #416] @ (800451c ) 800437a: 681a ldr r2, [r3, #0] 800437c: 2380 movs r3, #128 @ 0x80 800437e: 005b lsls r3, r3, #1 8004380: 4013 ands r3, r2 8004382: d0ed beq.n 8004360 } } if (ret == HAL_OK) 8004384: 2313 movs r3, #19 8004386: 18fb adds r3, r7, r3 8004388: 781b ldrb r3, [r3, #0] 800438a: 2b00 cmp r3, #0 800438c: d154 bne.n 8004438 { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 800438e: 4b62 ldr r3, [pc, #392] @ (8004518 ) 8004390: 6dda ldr r2, [r3, #92] @ 0x5c 8004392: 23c0 movs r3, #192 @ 0xc0 8004394: 009b lsls r3, r3, #2 8004396: 4013 ands r3, r2 8004398: 617b str r3, [r7, #20] /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 800439a: 697b ldr r3, [r7, #20] 800439c: 2b00 cmp r3, #0 800439e: d019 beq.n 80043d4 80043a0: 687b ldr r3, [r7, #4] 80043a2: 695b ldr r3, [r3, #20] 80043a4: 697a ldr r2, [r7, #20] 80043a6: 429a cmp r2, r3 80043a8: d014 beq.n 80043d4 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 80043aa: 4b5b ldr r3, [pc, #364] @ (8004518 ) 80043ac: 6ddb ldr r3, [r3, #92] @ 0x5c 80043ae: 4a5c ldr r2, [pc, #368] @ (8004520 ) 80043b0: 4013 ands r3, r2 80043b2: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80043b4: 4b58 ldr r3, [pc, #352] @ (8004518 ) 80043b6: 6dda ldr r2, [r3, #92] @ 0x5c 80043b8: 4b57 ldr r3, [pc, #348] @ (8004518 ) 80043ba: 2180 movs r1, #128 @ 0x80 80043bc: 0249 lsls r1, r1, #9 80043be: 430a orrs r2, r1 80043c0: 65da str r2, [r3, #92] @ 0x5c __HAL_RCC_BACKUPRESET_RELEASE(); 80043c2: 4b55 ldr r3, [pc, #340] @ (8004518 ) 80043c4: 6dda ldr r2, [r3, #92] @ 0x5c 80043c6: 4b54 ldr r3, [pc, #336] @ (8004518 ) 80043c8: 4956 ldr r1, [pc, #344] @ (8004524 ) 80043ca: 400a ands r2, r1 80043cc: 65da str r2, [r3, #92] @ 0x5c /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; 80043ce: 4b52 ldr r3, [pc, #328] @ (8004518 ) 80043d0: 697a ldr r2, [r7, #20] 80043d2: 65da str r2, [r3, #92] @ 0x5c } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 80043d4: 697b ldr r3, [r7, #20] 80043d6: 2201 movs r2, #1 80043d8: 4013 ands r3, r2 80043da: d016 beq.n 800440a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80043dc: f7fd fa44 bl 8001868 80043e0: 0003 movs r3, r0 80043e2: 60fb str r3, [r7, #12] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80043e4: e00c b.n 8004400 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80043e6: f7fd fa3f bl 8001868 80043ea: 0002 movs r2, r0 80043ec: 68fb ldr r3, [r7, #12] 80043ee: 1ad3 subs r3, r2, r3 80043f0: 4a4d ldr r2, [pc, #308] @ (8004528 ) 80043f2: 4293 cmp r3, r2 80043f4: d904 bls.n 8004400 { ret = HAL_TIMEOUT; 80043f6: 2313 movs r3, #19 80043f8: 18fb adds r3, r7, r3 80043fa: 2203 movs r2, #3 80043fc: 701a strb r2, [r3, #0] break; 80043fe: e004 b.n 800440a while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8004400: 4b45 ldr r3, [pc, #276] @ (8004518 ) 8004402: 6ddb ldr r3, [r3, #92] @ 0x5c 8004404: 2202 movs r2, #2 8004406: 4013 ands r3, r2 8004408: d0ed beq.n 80043e6 } } } if (ret == HAL_OK) 800440a: 2313 movs r3, #19 800440c: 18fb adds r3, r7, r3 800440e: 781b ldrb r3, [r3, #0] 8004410: 2b00 cmp r3, #0 8004412: d10a bne.n 800442a { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8004414: 4b40 ldr r3, [pc, #256] @ (8004518 ) 8004416: 6ddb ldr r3, [r3, #92] @ 0x5c 8004418: 4a41 ldr r2, [pc, #260] @ (8004520 ) 800441a: 4013 ands r3, r2 800441c: 0019 movs r1, r3 800441e: 687b ldr r3, [r7, #4] 8004420: 695a ldr r2, [r3, #20] 8004422: 4b3d ldr r3, [pc, #244] @ (8004518 ) 8004424: 430a orrs r2, r1 8004426: 65da str r2, [r3, #92] @ 0x5c 8004428: e00c b.n 8004444 } else { /* set overall return value */ status = ret; 800442a: 2312 movs r3, #18 800442c: 18fb adds r3, r7, r3 800442e: 2213 movs r2, #19 8004430: 18ba adds r2, r7, r2 8004432: 7812 ldrb r2, [r2, #0] 8004434: 701a strb r2, [r3, #0] 8004436: e005 b.n 8004444 } } else { /* set overall return value */ status = ret; 8004438: 2312 movs r3, #18 800443a: 18fb adds r3, r7, r3 800443c: 2213 movs r2, #19 800443e: 18ba adds r2, r7, r2 8004440: 7812 ldrb r2, [r2, #0] 8004442: 701a strb r2, [r3, #0] } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8004444: 2311 movs r3, #17 8004446: 18fb adds r3, r7, r3 8004448: 781b ldrb r3, [r3, #0] 800444a: 2b01 cmp r3, #1 800444c: d105 bne.n 800445a { __HAL_RCC_PWR_CLK_DISABLE(); 800444e: 4b32 ldr r3, [pc, #200] @ (8004518 ) 8004450: 6bda ldr r2, [r3, #60] @ 0x3c 8004452: 4b31 ldr r3, [pc, #196] @ (8004518 ) 8004454: 4935 ldr r1, [pc, #212] @ (800452c ) 8004456: 400a ands r2, r1 8004458: 63da str r2, [r3, #60] @ 0x3c } } /*-------------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 800445a: 687b ldr r3, [r7, #4] 800445c: 681b ldr r3, [r3, #0] 800445e: 2201 movs r2, #1 8004460: 4013 ands r3, r2 8004462: d009 beq.n 8004478 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8004464: 4b2c ldr r3, [pc, #176] @ (8004518 ) 8004466: 6d5b ldr r3, [r3, #84] @ 0x54 8004468: 2203 movs r2, #3 800446a: 4393 bics r3, r2 800446c: 0019 movs r1, r3 800446e: 687b ldr r3, [r7, #4] 8004470: 685a ldr r2, [r3, #4] 8004472: 4b29 ldr r3, [pc, #164] @ (8004518 ) 8004474: 430a orrs r2, r1 8004476: 655a str r2, [r3, #84] @ 0x54 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); } #endif /* RCC_CCIPR_LPTIM2SEL */ /*-------------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8004478: 687b ldr r3, [r7, #4] 800447a: 681b ldr r3, [r3, #0] 800447c: 2220 movs r2, #32 800447e: 4013 ands r3, r2 8004480: d009 beq.n 8004496 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8004482: 4b25 ldr r3, [pc, #148] @ (8004518 ) 8004484: 6d5b ldr r3, [r3, #84] @ 0x54 8004486: 4a2a ldr r2, [pc, #168] @ (8004530 ) 8004488: 4013 ands r3, r2 800448a: 0019 movs r1, r3 800448c: 687b ldr r3, [r7, #4] 800448e: 689a ldr r2, [r3, #8] 8004490: 4b21 ldr r3, [pc, #132] @ (8004518 ) 8004492: 430a orrs r2, r1 8004494: 655a str r2, [r3, #84] @ 0x54 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); } } #endif /* RNG */ /*-------------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8004496: 687b ldr r3, [r7, #4] 8004498: 681a ldr r2, [r3, #0] 800449a: 2380 movs r3, #128 @ 0x80 800449c: 01db lsls r3, r3, #7 800449e: 4013 ands r3, r2 80044a0: d015 beq.n 80044ce { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80044a2: 4b1d ldr r3, [pc, #116] @ (8004518 ) 80044a4: 6d5b ldr r3, [r3, #84] @ 0x54 80044a6: 009b lsls r3, r3, #2 80044a8: 0899 lsrs r1, r3, #2 80044aa: 687b ldr r3, [r7, #4] 80044ac: 691a ldr r2, [r3, #16] 80044ae: 4b1a ldr r3, [pc, #104] @ (8004518 ) 80044b0: 430a orrs r2, r1 80044b2: 655a str r2, [r3, #84] @ 0x54 if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC) 80044b4: 687b ldr r3, [r7, #4] 80044b6: 691a ldr r2, [r3, #16] 80044b8: 2380 movs r3, #128 @ 0x80 80044ba: 05db lsls r3, r3, #23 80044bc: 429a cmp r2, r3 80044be: d106 bne.n 80044ce { /* Enable PLLPCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); 80044c0: 4b15 ldr r3, [pc, #84] @ (8004518 ) 80044c2: 68da ldr r2, [r3, #12] 80044c4: 4b14 ldr r3, [pc, #80] @ (8004518 ) 80044c6: 2180 movs r1, #128 @ 0x80 80044c8: 0249 lsls r1, r1, #9 80044ca: 430a orrs r2, r1 80044cc: 60da str r2, [r3, #12] } } #endif /* RCC_CCIPR_TIM15SEL */ /*-------------------------- I2S1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) 80044ce: 687b ldr r3, [r7, #4] 80044d0: 681a ldr r2, [r3, #0] 80044d2: 2380 movs r3, #128 @ 0x80 80044d4: 011b lsls r3, r3, #4 80044d6: 4013 ands r3, r2 80044d8: d016 beq.n 8004508 { /* Check the parameters */ assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); /* Configure the I2S1 clock source */ __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); 80044da: 4b0f ldr r3, [pc, #60] @ (8004518 ) 80044dc: 6d5b ldr r3, [r3, #84] @ 0x54 80044de: 4a15 ldr r2, [pc, #84] @ (8004534 ) 80044e0: 4013 ands r3, r2 80044e2: 0019 movs r1, r3 80044e4: 687b ldr r3, [r7, #4] 80044e6: 68da ldr r2, [r3, #12] 80044e8: 4b0b ldr r3, [pc, #44] @ (8004518 ) 80044ea: 430a orrs r2, r1 80044ec: 655a str r2, [r3, #84] @ 0x54 if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL) 80044ee: 687b ldr r3, [r7, #4] 80044f0: 68da ldr r2, [r3, #12] 80044f2: 2380 movs r3, #128 @ 0x80 80044f4: 01db lsls r3, r3, #7 80044f6: 429a cmp r2, r3 80044f8: d106 bne.n 8004508 { /* Enable PLLPCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); 80044fa: 4b07 ldr r3, [pc, #28] @ (8004518 ) 80044fc: 68da ldr r2, [r3, #12] 80044fe: 4b06 ldr r3, [pc, #24] @ (8004518 ) 8004500: 2180 movs r1, #128 @ 0x80 8004502: 0249 lsls r1, r1, #9 8004504: 430a orrs r2, r1 8004506: 60da str r2, [r3, #12] __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); } } #endif /* FDCAN1 || FDCAN2 */ return status; 8004508: 2312 movs r3, #18 800450a: 18fb adds r3, r7, r3 800450c: 781b ldrb r3, [r3, #0] } 800450e: 0018 movs r0, r3 8004510: 46bd mov sp, r7 8004512: b006 add sp, #24 8004514: bd80 pop {r7, pc} 8004516: 46c0 nop @ (mov r8, r8) 8004518: 40021000 .word 0x40021000 800451c: 40007000 .word 0x40007000 8004520: fffffcff .word 0xfffffcff 8004524: fffeffff .word 0xfffeffff 8004528: 00001388 .word 0x00001388 800452c: efffffff .word 0xefffffff 8004530: ffffcfff .word 0xffffcfff 8004534: ffff3fff .word 0xffff3fff 08004538 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8004538: b580 push {r7, lr} 800453a: b082 sub sp, #8 800453c: af00 add r7, sp, #0 800453e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8004540: 687b ldr r3, [r7, #4] 8004542: 2b00 cmp r3, #0 8004544: d101 bne.n 800454a { return HAL_ERROR; 8004546: 2301 movs r3, #1 8004548: e04a b.n 80045e0 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800454a: 687b ldr r3, [r7, #4] 800454c: 223d movs r2, #61 @ 0x3d 800454e: 5c9b ldrb r3, [r3, r2] 8004550: b2db uxtb r3, r3 8004552: 2b00 cmp r3, #0 8004554: d107 bne.n 8004566 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8004556: 687b ldr r3, [r7, #4] 8004558: 223c movs r2, #60 @ 0x3c 800455a: 2100 movs r1, #0 800455c: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800455e: 687b ldr r3, [r7, #4] 8004560: 0018 movs r0, r3 8004562: f7fc fab5 bl 8000ad0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8004566: 687b ldr r3, [r7, #4] 8004568: 223d movs r2, #61 @ 0x3d 800456a: 2102 movs r1, #2 800456c: 5499 strb r1, [r3, r2] /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800456e: 687b ldr r3, [r7, #4] 8004570: 681a ldr r2, [r3, #0] 8004572: 687b ldr r3, [r7, #4] 8004574: 3304 adds r3, #4 8004576: 0019 movs r1, r3 8004578: 0010 movs r0, r2 800457a: f000 f935 bl 80047e8 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800457e: 687b ldr r3, [r7, #4] 8004580: 2248 movs r2, #72 @ 0x48 8004582: 2101 movs r1, #1 8004584: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004586: 687b ldr r3, [r7, #4] 8004588: 223e movs r2, #62 @ 0x3e 800458a: 2101 movs r1, #1 800458c: 5499 strb r1, [r3, r2] 800458e: 687b ldr r3, [r7, #4] 8004590: 223f movs r2, #63 @ 0x3f 8004592: 2101 movs r1, #1 8004594: 5499 strb r1, [r3, r2] 8004596: 687b ldr r3, [r7, #4] 8004598: 2240 movs r2, #64 @ 0x40 800459a: 2101 movs r1, #1 800459c: 5499 strb r1, [r3, r2] 800459e: 687b ldr r3, [r7, #4] 80045a0: 2241 movs r2, #65 @ 0x41 80045a2: 2101 movs r1, #1 80045a4: 5499 strb r1, [r3, r2] 80045a6: 687b ldr r3, [r7, #4] 80045a8: 2242 movs r2, #66 @ 0x42 80045aa: 2101 movs r1, #1 80045ac: 5499 strb r1, [r3, r2] 80045ae: 687b ldr r3, [r7, #4] 80045b0: 2243 movs r2, #67 @ 0x43 80045b2: 2101 movs r1, #1 80045b4: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80045b6: 687b ldr r3, [r7, #4] 80045b8: 2244 movs r2, #68 @ 0x44 80045ba: 2101 movs r1, #1 80045bc: 5499 strb r1, [r3, r2] 80045be: 687b ldr r3, [r7, #4] 80045c0: 2245 movs r2, #69 @ 0x45 80045c2: 2101 movs r1, #1 80045c4: 5499 strb r1, [r3, r2] 80045c6: 687b ldr r3, [r7, #4] 80045c8: 2246 movs r2, #70 @ 0x46 80045ca: 2101 movs r1, #1 80045cc: 5499 strb r1, [r3, r2] 80045ce: 687b ldr r3, [r7, #4] 80045d0: 2247 movs r2, #71 @ 0x47 80045d2: 2101 movs r1, #1 80045d4: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80045d6: 687b ldr r3, [r7, #4] 80045d8: 223d movs r2, #61 @ 0x3d 80045da: 2101 movs r1, #1 80045dc: 5499 strb r1, [r3, r2] return HAL_OK; 80045de: 2300 movs r3, #0 } 80045e0: 0018 movs r0, r3 80045e2: 46bd mov sp, r7 80045e4: b002 add sp, #8 80045e6: bd80 pop {r7, pc} 080045e8 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80045e8: b580 push {r7, lr} 80045ea: b086 sub sp, #24 80045ec: af00 add r7, sp, #0 80045ee: 60f8 str r0, [r7, #12] 80045f0: 60b9 str r1, [r7, #8] 80045f2: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80045f4: 2317 movs r3, #23 80045f6: 18fb adds r3, r7, r3 80045f8: 2200 movs r2, #0 80045fa: 701a strb r2, [r3, #0] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 80045fc: 68fb ldr r3, [r7, #12] 80045fe: 223c movs r2, #60 @ 0x3c 8004600: 5c9b ldrb r3, [r3, r2] 8004602: 2b01 cmp r3, #1 8004604: d101 bne.n 800460a 8004606: 2302 movs r3, #2 8004608: e0e5 b.n 80047d6 800460a: 68fb ldr r3, [r7, #12] 800460c: 223c movs r2, #60 @ 0x3c 800460e: 2101 movs r1, #1 8004610: 5499 strb r1, [r3, r2] switch (Channel) 8004612: 687b ldr r3, [r7, #4] 8004614: 2b14 cmp r3, #20 8004616: d900 bls.n 800461a 8004618: e0d1 b.n 80047be 800461a: 687b ldr r3, [r7, #4] 800461c: 009a lsls r2, r3, #2 800461e: 4b70 ldr r3, [pc, #448] @ (80047e0 ) 8004620: 18d3 adds r3, r2, r3 8004622: 681b ldr r3, [r3, #0] 8004624: 469f mov pc, r3 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8004626: 68fb ldr r3, [r7, #12] 8004628: 681b ldr r3, [r3, #0] 800462a: 68ba ldr r2, [r7, #8] 800462c: 0011 movs r1, r2 800462e: 0018 movs r0, r3 8004630: f000 f954 bl 80048dc /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8004634: 68fb ldr r3, [r7, #12] 8004636: 681b ldr r3, [r3, #0] 8004638: 699a ldr r2, [r3, #24] 800463a: 68fb ldr r3, [r7, #12] 800463c: 681b ldr r3, [r3, #0] 800463e: 2108 movs r1, #8 8004640: 430a orrs r2, r1 8004642: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8004644: 68fb ldr r3, [r7, #12] 8004646: 681b ldr r3, [r3, #0] 8004648: 699a ldr r2, [r3, #24] 800464a: 68fb ldr r3, [r7, #12] 800464c: 681b ldr r3, [r3, #0] 800464e: 2104 movs r1, #4 8004650: 438a bics r2, r1 8004652: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8004654: 68fb ldr r3, [r7, #12] 8004656: 681b ldr r3, [r3, #0] 8004658: 6999 ldr r1, [r3, #24] 800465a: 68bb ldr r3, [r7, #8] 800465c: 691a ldr r2, [r3, #16] 800465e: 68fb ldr r3, [r7, #12] 8004660: 681b ldr r3, [r3, #0] 8004662: 430a orrs r2, r1 8004664: 619a str r2, [r3, #24] break; 8004666: e0af b.n 80047c8 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8004668: 68fb ldr r3, [r7, #12] 800466a: 681b ldr r3, [r3, #0] 800466c: 68ba ldr r2, [r7, #8] 800466e: 0011 movs r1, r2 8004670: 0018 movs r0, r3 8004672: f000 f9b3 bl 80049dc /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8004676: 68fb ldr r3, [r7, #12] 8004678: 681b ldr r3, [r3, #0] 800467a: 699a ldr r2, [r3, #24] 800467c: 68fb ldr r3, [r7, #12] 800467e: 681b ldr r3, [r3, #0] 8004680: 2180 movs r1, #128 @ 0x80 8004682: 0109 lsls r1, r1, #4 8004684: 430a orrs r2, r1 8004686: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8004688: 68fb ldr r3, [r7, #12] 800468a: 681b ldr r3, [r3, #0] 800468c: 699a ldr r2, [r3, #24] 800468e: 68fb ldr r3, [r7, #12] 8004690: 681b ldr r3, [r3, #0] 8004692: 4954 ldr r1, [pc, #336] @ (80047e4 ) 8004694: 400a ands r2, r1 8004696: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8004698: 68fb ldr r3, [r7, #12] 800469a: 681b ldr r3, [r3, #0] 800469c: 6999 ldr r1, [r3, #24] 800469e: 68bb ldr r3, [r7, #8] 80046a0: 691b ldr r3, [r3, #16] 80046a2: 021a lsls r2, r3, #8 80046a4: 68fb ldr r3, [r7, #12] 80046a6: 681b ldr r3, [r3, #0] 80046a8: 430a orrs r2, r1 80046aa: 619a str r2, [r3, #24] break; 80046ac: e08c b.n 80047c8 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 80046ae: 68fb ldr r3, [r7, #12] 80046b0: 681b ldr r3, [r3, #0] 80046b2: 68ba ldr r2, [r7, #8] 80046b4: 0011 movs r1, r2 80046b6: 0018 movs r0, r3 80046b8: f000 fa0e bl 8004ad8 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 80046bc: 68fb ldr r3, [r7, #12] 80046be: 681b ldr r3, [r3, #0] 80046c0: 69da ldr r2, [r3, #28] 80046c2: 68fb ldr r3, [r7, #12] 80046c4: 681b ldr r3, [r3, #0] 80046c6: 2108 movs r1, #8 80046c8: 430a orrs r2, r1 80046ca: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 80046cc: 68fb ldr r3, [r7, #12] 80046ce: 681b ldr r3, [r3, #0] 80046d0: 69da ldr r2, [r3, #28] 80046d2: 68fb ldr r3, [r7, #12] 80046d4: 681b ldr r3, [r3, #0] 80046d6: 2104 movs r1, #4 80046d8: 438a bics r2, r1 80046da: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 80046dc: 68fb ldr r3, [r7, #12] 80046de: 681b ldr r3, [r3, #0] 80046e0: 69d9 ldr r1, [r3, #28] 80046e2: 68bb ldr r3, [r7, #8] 80046e4: 691a ldr r2, [r3, #16] 80046e6: 68fb ldr r3, [r7, #12] 80046e8: 681b ldr r3, [r3, #0] 80046ea: 430a orrs r2, r1 80046ec: 61da str r2, [r3, #28] break; 80046ee: e06b b.n 80047c8 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80046f0: 68fb ldr r3, [r7, #12] 80046f2: 681b ldr r3, [r3, #0] 80046f4: 68ba ldr r2, [r7, #8] 80046f6: 0011 movs r1, r2 80046f8: 0018 movs r0, r3 80046fa: f000 fa6f bl 8004bdc /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80046fe: 68fb ldr r3, [r7, #12] 8004700: 681b ldr r3, [r3, #0] 8004702: 69da ldr r2, [r3, #28] 8004704: 68fb ldr r3, [r7, #12] 8004706: 681b ldr r3, [r3, #0] 8004708: 2180 movs r1, #128 @ 0x80 800470a: 0109 lsls r1, r1, #4 800470c: 430a orrs r2, r1 800470e: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 8004710: 68fb ldr r3, [r7, #12] 8004712: 681b ldr r3, [r3, #0] 8004714: 69da ldr r2, [r3, #28] 8004716: 68fb ldr r3, [r7, #12] 8004718: 681b ldr r3, [r3, #0] 800471a: 4932 ldr r1, [pc, #200] @ (80047e4 ) 800471c: 400a ands r2, r1 800471e: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 8004720: 68fb ldr r3, [r7, #12] 8004722: 681b ldr r3, [r3, #0] 8004724: 69d9 ldr r1, [r3, #28] 8004726: 68bb ldr r3, [r7, #8] 8004728: 691b ldr r3, [r3, #16] 800472a: 021a lsls r2, r3, #8 800472c: 68fb ldr r3, [r7, #12] 800472e: 681b ldr r3, [r3, #0] 8004730: 430a orrs r2, r1 8004732: 61da str r2, [r3, #28] break; 8004734: e048 b.n 80047c8 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 8004736: 68fb ldr r3, [r7, #12] 8004738: 681b ldr r3, [r3, #0] 800473a: 68ba ldr r2, [r7, #8] 800473c: 0011 movs r1, r2 800473e: 0018 movs r0, r3 8004740: f000 fab0 bl 8004ca4 /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 8004744: 68fb ldr r3, [r7, #12] 8004746: 681b ldr r3, [r3, #0] 8004748: 6d5a ldr r2, [r3, #84] @ 0x54 800474a: 68fb ldr r3, [r7, #12] 800474c: 681b ldr r3, [r3, #0] 800474e: 2108 movs r1, #8 8004750: 430a orrs r2, r1 8004752: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 8004754: 68fb ldr r3, [r7, #12] 8004756: 681b ldr r3, [r3, #0] 8004758: 6d5a ldr r2, [r3, #84] @ 0x54 800475a: 68fb ldr r3, [r7, #12] 800475c: 681b ldr r3, [r3, #0] 800475e: 2104 movs r1, #4 8004760: 438a bics r2, r1 8004762: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 8004764: 68fb ldr r3, [r7, #12] 8004766: 681b ldr r3, [r3, #0] 8004768: 6d59 ldr r1, [r3, #84] @ 0x54 800476a: 68bb ldr r3, [r7, #8] 800476c: 691a ldr r2, [r3, #16] 800476e: 68fb ldr r3, [r7, #12] 8004770: 681b ldr r3, [r3, #0] 8004772: 430a orrs r2, r1 8004774: 655a str r2, [r3, #84] @ 0x54 break; 8004776: e027 b.n 80047c8 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 8004778: 68fb ldr r3, [r7, #12] 800477a: 681b ldr r3, [r3, #0] 800477c: 68ba ldr r2, [r7, #8] 800477e: 0011 movs r1, r2 8004780: 0018 movs r0, r3 8004782: f000 fae9 bl 8004d58 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 8004786: 68fb ldr r3, [r7, #12] 8004788: 681b ldr r3, [r3, #0] 800478a: 6d5a ldr r2, [r3, #84] @ 0x54 800478c: 68fb ldr r3, [r7, #12] 800478e: 681b ldr r3, [r3, #0] 8004790: 2180 movs r1, #128 @ 0x80 8004792: 0109 lsls r1, r1, #4 8004794: 430a orrs r2, r1 8004796: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 8004798: 68fb ldr r3, [r7, #12] 800479a: 681b ldr r3, [r3, #0] 800479c: 6d5a ldr r2, [r3, #84] @ 0x54 800479e: 68fb ldr r3, [r7, #12] 80047a0: 681b ldr r3, [r3, #0] 80047a2: 4910 ldr r1, [pc, #64] @ (80047e4 ) 80047a4: 400a ands r2, r1 80047a6: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 80047a8: 68fb ldr r3, [r7, #12] 80047aa: 681b ldr r3, [r3, #0] 80047ac: 6d59 ldr r1, [r3, #84] @ 0x54 80047ae: 68bb ldr r3, [r7, #8] 80047b0: 691b ldr r3, [r3, #16] 80047b2: 021a lsls r2, r3, #8 80047b4: 68fb ldr r3, [r7, #12] 80047b6: 681b ldr r3, [r3, #0] 80047b8: 430a orrs r2, r1 80047ba: 655a str r2, [r3, #84] @ 0x54 break; 80047bc: e004 b.n 80047c8 } default: status = HAL_ERROR; 80047be: 2317 movs r3, #23 80047c0: 18fb adds r3, r7, r3 80047c2: 2201 movs r2, #1 80047c4: 701a strb r2, [r3, #0] break; 80047c6: 46c0 nop @ (mov r8, r8) } __HAL_UNLOCK(htim); 80047c8: 68fb ldr r3, [r7, #12] 80047ca: 223c movs r2, #60 @ 0x3c 80047cc: 2100 movs r1, #0 80047ce: 5499 strb r1, [r3, r2] return status; 80047d0: 2317 movs r3, #23 80047d2: 18fb adds r3, r7, r3 80047d4: 781b ldrb r3, [r3, #0] } 80047d6: 0018 movs r0, r3 80047d8: 46bd mov sp, r7 80047da: b006 add sp, #24 80047dc: bd80 pop {r7, pc} 80047de: 46c0 nop @ (mov r8, r8) 80047e0: 080060d4 .word 0x080060d4 80047e4: fffffbff .word 0xfffffbff 080047e8 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80047e8: b580 push {r7, lr} 80047ea: b084 sub sp, #16 80047ec: af00 add r7, sp, #0 80047ee: 6078 str r0, [r7, #4] 80047f0: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80047f2: 687b ldr r3, [r7, #4] 80047f4: 681b ldr r3, [r3, #0] 80047f6: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80047f8: 687b ldr r3, [r7, #4] 80047fa: 4a32 ldr r2, [pc, #200] @ (80048c4 ) 80047fc: 4293 cmp r3, r2 80047fe: d003 beq.n 8004808 8004800: 687b ldr r3, [r7, #4] 8004802: 4a31 ldr r2, [pc, #196] @ (80048c8 ) 8004804: 4293 cmp r3, r2 8004806: d108 bne.n 800481a { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8004808: 68fb ldr r3, [r7, #12] 800480a: 2270 movs r2, #112 @ 0x70 800480c: 4393 bics r3, r2 800480e: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8004810: 683b ldr r3, [r7, #0] 8004812: 685b ldr r3, [r3, #4] 8004814: 68fa ldr r2, [r7, #12] 8004816: 4313 orrs r3, r2 8004818: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800481a: 687b ldr r3, [r7, #4] 800481c: 4a29 ldr r2, [pc, #164] @ (80048c4 ) 800481e: 4293 cmp r3, r2 8004820: d00f beq.n 8004842 8004822: 687b ldr r3, [r7, #4] 8004824: 4a28 ldr r2, [pc, #160] @ (80048c8 ) 8004826: 4293 cmp r3, r2 8004828: d00b beq.n 8004842 800482a: 687b ldr r3, [r7, #4] 800482c: 4a27 ldr r2, [pc, #156] @ (80048cc ) 800482e: 4293 cmp r3, r2 8004830: d007 beq.n 8004842 8004832: 687b ldr r3, [r7, #4] 8004834: 4a26 ldr r2, [pc, #152] @ (80048d0 ) 8004836: 4293 cmp r3, r2 8004838: d003 beq.n 8004842 800483a: 687b ldr r3, [r7, #4] 800483c: 4a25 ldr r2, [pc, #148] @ (80048d4 ) 800483e: 4293 cmp r3, r2 8004840: d108 bne.n 8004854 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8004842: 68fb ldr r3, [r7, #12] 8004844: 4a24 ldr r2, [pc, #144] @ (80048d8 ) 8004846: 4013 ands r3, r2 8004848: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800484a: 683b ldr r3, [r7, #0] 800484c: 68db ldr r3, [r3, #12] 800484e: 68fa ldr r2, [r7, #12] 8004850: 4313 orrs r3, r2 8004852: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004854: 68fb ldr r3, [r7, #12] 8004856: 2280 movs r2, #128 @ 0x80 8004858: 4393 bics r3, r2 800485a: 001a movs r2, r3 800485c: 683b ldr r3, [r7, #0] 800485e: 695b ldr r3, [r3, #20] 8004860: 4313 orrs r3, r2 8004862: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8004864: 687b ldr r3, [r7, #4] 8004866: 68fa ldr r2, [r7, #12] 8004868: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800486a: 683b ldr r3, [r7, #0] 800486c: 689a ldr r2, [r3, #8] 800486e: 687b ldr r3, [r7, #4] 8004870: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8004872: 683b ldr r3, [r7, #0] 8004874: 681a ldr r2, [r3, #0] 8004876: 687b ldr r3, [r7, #4] 8004878: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800487a: 687b ldr r3, [r7, #4] 800487c: 4a11 ldr r2, [pc, #68] @ (80048c4 ) 800487e: 4293 cmp r3, r2 8004880: d007 beq.n 8004892 8004882: 687b ldr r3, [r7, #4] 8004884: 4a12 ldr r2, [pc, #72] @ (80048d0 ) 8004886: 4293 cmp r3, r2 8004888: d003 beq.n 8004892 800488a: 687b ldr r3, [r7, #4] 800488c: 4a11 ldr r2, [pc, #68] @ (80048d4 ) 800488e: 4293 cmp r3, r2 8004890: d103 bne.n 800489a { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8004892: 683b ldr r3, [r7, #0] 8004894: 691a ldr r2, [r3, #16] 8004896: 687b ldr r3, [r7, #4] 8004898: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800489a: 687b ldr r3, [r7, #4] 800489c: 2201 movs r2, #1 800489e: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 80048a0: 687b ldr r3, [r7, #4] 80048a2: 691b ldr r3, [r3, #16] 80048a4: 2201 movs r2, #1 80048a6: 4013 ands r3, r2 80048a8: 2b01 cmp r3, #1 80048aa: d106 bne.n 80048ba { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 80048ac: 687b ldr r3, [r7, #4] 80048ae: 691b ldr r3, [r3, #16] 80048b0: 2201 movs r2, #1 80048b2: 4393 bics r3, r2 80048b4: 001a movs r2, r3 80048b6: 687b ldr r3, [r7, #4] 80048b8: 611a str r2, [r3, #16] } } 80048ba: 46c0 nop @ (mov r8, r8) 80048bc: 46bd mov sp, r7 80048be: b004 add sp, #16 80048c0: bd80 pop {r7, pc} 80048c2: 46c0 nop @ (mov r8, r8) 80048c4: 40012c00 .word 0x40012c00 80048c8: 40000400 .word 0x40000400 80048cc: 40002000 .word 0x40002000 80048d0: 40014400 .word 0x40014400 80048d4: 40014800 .word 0x40014800 80048d8: fffffcff .word 0xfffffcff 080048dc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80048dc: b580 push {r7, lr} 80048de: b086 sub sp, #24 80048e0: af00 add r7, sp, #0 80048e2: 6078 str r0, [r7, #4] 80048e4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80048e6: 687b ldr r3, [r7, #4] 80048e8: 6a1b ldr r3, [r3, #32] 80048ea: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80048ec: 687b ldr r3, [r7, #4] 80048ee: 6a1b ldr r3, [r3, #32] 80048f0: 2201 movs r2, #1 80048f2: 4393 bics r3, r2 80048f4: 001a movs r2, r3 80048f6: 687b ldr r3, [r7, #4] 80048f8: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80048fa: 687b ldr r3, [r7, #4] 80048fc: 685b ldr r3, [r3, #4] 80048fe: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8004900: 687b ldr r3, [r7, #4] 8004902: 699b ldr r3, [r3, #24] 8004904: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8004906: 68fb ldr r3, [r7, #12] 8004908: 4a2e ldr r2, [pc, #184] @ (80049c4 ) 800490a: 4013 ands r3, r2 800490c: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 800490e: 68fb ldr r3, [r7, #12] 8004910: 2203 movs r2, #3 8004912: 4393 bics r3, r2 8004914: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8004916: 683b ldr r3, [r7, #0] 8004918: 681b ldr r3, [r3, #0] 800491a: 68fa ldr r2, [r7, #12] 800491c: 4313 orrs r3, r2 800491e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8004920: 697b ldr r3, [r7, #20] 8004922: 2202 movs r2, #2 8004924: 4393 bics r3, r2 8004926: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8004928: 683b ldr r3, [r7, #0] 800492a: 689b ldr r3, [r3, #8] 800492c: 697a ldr r2, [r7, #20] 800492e: 4313 orrs r3, r2 8004930: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8004932: 687b ldr r3, [r7, #4] 8004934: 4a24 ldr r2, [pc, #144] @ (80049c8 ) 8004936: 4293 cmp r3, r2 8004938: d007 beq.n 800494a 800493a: 687b ldr r3, [r7, #4] 800493c: 4a23 ldr r2, [pc, #140] @ (80049cc ) 800493e: 4293 cmp r3, r2 8004940: d003 beq.n 800494a 8004942: 687b ldr r3, [r7, #4] 8004944: 4a22 ldr r2, [pc, #136] @ (80049d0 ) 8004946: 4293 cmp r3, r2 8004948: d10c bne.n 8004964 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 800494a: 697b ldr r3, [r7, #20] 800494c: 2208 movs r2, #8 800494e: 4393 bics r3, r2 8004950: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8004952: 683b ldr r3, [r7, #0] 8004954: 68db ldr r3, [r3, #12] 8004956: 697a ldr r2, [r7, #20] 8004958: 4313 orrs r3, r2 800495a: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 800495c: 697b ldr r3, [r7, #20] 800495e: 2204 movs r2, #4 8004960: 4393 bics r3, r2 8004962: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8004964: 687b ldr r3, [r7, #4] 8004966: 4a18 ldr r2, [pc, #96] @ (80049c8 ) 8004968: 4293 cmp r3, r2 800496a: d007 beq.n 800497c 800496c: 687b ldr r3, [r7, #4] 800496e: 4a17 ldr r2, [pc, #92] @ (80049cc ) 8004970: 4293 cmp r3, r2 8004972: d003 beq.n 800497c 8004974: 687b ldr r3, [r7, #4] 8004976: 4a16 ldr r2, [pc, #88] @ (80049d0 ) 8004978: 4293 cmp r3, r2 800497a: d111 bne.n 80049a0 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 800497c: 693b ldr r3, [r7, #16] 800497e: 4a15 ldr r2, [pc, #84] @ (80049d4 ) 8004980: 4013 ands r3, r2 8004982: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8004984: 693b ldr r3, [r7, #16] 8004986: 4a14 ldr r2, [pc, #80] @ (80049d8 ) 8004988: 4013 ands r3, r2 800498a: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 800498c: 683b ldr r3, [r7, #0] 800498e: 695b ldr r3, [r3, #20] 8004990: 693a ldr r2, [r7, #16] 8004992: 4313 orrs r3, r2 8004994: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8004996: 683b ldr r3, [r7, #0] 8004998: 699b ldr r3, [r3, #24] 800499a: 693a ldr r2, [r7, #16] 800499c: 4313 orrs r3, r2 800499e: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80049a0: 687b ldr r3, [r7, #4] 80049a2: 693a ldr r2, [r7, #16] 80049a4: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80049a6: 687b ldr r3, [r7, #4] 80049a8: 68fa ldr r2, [r7, #12] 80049aa: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80049ac: 683b ldr r3, [r7, #0] 80049ae: 685a ldr r2, [r3, #4] 80049b0: 687b ldr r3, [r7, #4] 80049b2: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80049b4: 687b ldr r3, [r7, #4] 80049b6: 697a ldr r2, [r7, #20] 80049b8: 621a str r2, [r3, #32] } 80049ba: 46c0 nop @ (mov r8, r8) 80049bc: 46bd mov sp, r7 80049be: b006 add sp, #24 80049c0: bd80 pop {r7, pc} 80049c2: 46c0 nop @ (mov r8, r8) 80049c4: fffeff8f .word 0xfffeff8f 80049c8: 40012c00 .word 0x40012c00 80049cc: 40014400 .word 0x40014400 80049d0: 40014800 .word 0x40014800 80049d4: fffffeff .word 0xfffffeff 80049d8: fffffdff .word 0xfffffdff 080049dc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80049dc: b580 push {r7, lr} 80049de: b086 sub sp, #24 80049e0: af00 add r7, sp, #0 80049e2: 6078 str r0, [r7, #4] 80049e4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80049e6: 687b ldr r3, [r7, #4] 80049e8: 6a1b ldr r3, [r3, #32] 80049ea: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80049ec: 687b ldr r3, [r7, #4] 80049ee: 6a1b ldr r3, [r3, #32] 80049f0: 2210 movs r2, #16 80049f2: 4393 bics r3, r2 80049f4: 001a movs r2, r3 80049f6: 687b ldr r3, [r7, #4] 80049f8: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80049fa: 687b ldr r3, [r7, #4] 80049fc: 685b ldr r3, [r3, #4] 80049fe: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8004a00: 687b ldr r3, [r7, #4] 8004a02: 699b ldr r3, [r3, #24] 8004a04: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8004a06: 68fb ldr r3, [r7, #12] 8004a08: 4a2c ldr r2, [pc, #176] @ (8004abc ) 8004a0a: 4013 ands r3, r2 8004a0c: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8004a0e: 68fb ldr r3, [r7, #12] 8004a10: 4a2b ldr r2, [pc, #172] @ (8004ac0 ) 8004a12: 4013 ands r3, r2 8004a14: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8004a16: 683b ldr r3, [r7, #0] 8004a18: 681b ldr r3, [r3, #0] 8004a1a: 021b lsls r3, r3, #8 8004a1c: 68fa ldr r2, [r7, #12] 8004a1e: 4313 orrs r3, r2 8004a20: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8004a22: 697b ldr r3, [r7, #20] 8004a24: 2220 movs r2, #32 8004a26: 4393 bics r3, r2 8004a28: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8004a2a: 683b ldr r3, [r7, #0] 8004a2c: 689b ldr r3, [r3, #8] 8004a2e: 011b lsls r3, r3, #4 8004a30: 697a ldr r2, [r7, #20] 8004a32: 4313 orrs r3, r2 8004a34: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8004a36: 687b ldr r3, [r7, #4] 8004a38: 4a22 ldr r2, [pc, #136] @ (8004ac4 ) 8004a3a: 4293 cmp r3, r2 8004a3c: d10d bne.n 8004a5a { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8004a3e: 697b ldr r3, [r7, #20] 8004a40: 2280 movs r2, #128 @ 0x80 8004a42: 4393 bics r3, r2 8004a44: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8004a46: 683b ldr r3, [r7, #0] 8004a48: 68db ldr r3, [r3, #12] 8004a4a: 011b lsls r3, r3, #4 8004a4c: 697a ldr r2, [r7, #20] 8004a4e: 4313 orrs r3, r2 8004a50: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8004a52: 697b ldr r3, [r7, #20] 8004a54: 2240 movs r2, #64 @ 0x40 8004a56: 4393 bics r3, r2 8004a58: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8004a5a: 687b ldr r3, [r7, #4] 8004a5c: 4a19 ldr r2, [pc, #100] @ (8004ac4 ) 8004a5e: 4293 cmp r3, r2 8004a60: d007 beq.n 8004a72 8004a62: 687b ldr r3, [r7, #4] 8004a64: 4a18 ldr r2, [pc, #96] @ (8004ac8 ) 8004a66: 4293 cmp r3, r2 8004a68: d003 beq.n 8004a72 8004a6a: 687b ldr r3, [r7, #4] 8004a6c: 4a17 ldr r2, [pc, #92] @ (8004acc ) 8004a6e: 4293 cmp r3, r2 8004a70: d113 bne.n 8004a9a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8004a72: 693b ldr r3, [r7, #16] 8004a74: 4a16 ldr r2, [pc, #88] @ (8004ad0 ) 8004a76: 4013 ands r3, r2 8004a78: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8004a7a: 693b ldr r3, [r7, #16] 8004a7c: 4a15 ldr r2, [pc, #84] @ (8004ad4 ) 8004a7e: 4013 ands r3, r2 8004a80: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8004a82: 683b ldr r3, [r7, #0] 8004a84: 695b ldr r3, [r3, #20] 8004a86: 009b lsls r3, r3, #2 8004a88: 693a ldr r2, [r7, #16] 8004a8a: 4313 orrs r3, r2 8004a8c: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8004a8e: 683b ldr r3, [r7, #0] 8004a90: 699b ldr r3, [r3, #24] 8004a92: 009b lsls r3, r3, #2 8004a94: 693a ldr r2, [r7, #16] 8004a96: 4313 orrs r3, r2 8004a98: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8004a9a: 687b ldr r3, [r7, #4] 8004a9c: 693a ldr r2, [r7, #16] 8004a9e: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8004aa0: 687b ldr r3, [r7, #4] 8004aa2: 68fa ldr r2, [r7, #12] 8004aa4: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8004aa6: 683b ldr r3, [r7, #0] 8004aa8: 685a ldr r2, [r3, #4] 8004aaa: 687b ldr r3, [r7, #4] 8004aac: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8004aae: 687b ldr r3, [r7, #4] 8004ab0: 697a ldr r2, [r7, #20] 8004ab2: 621a str r2, [r3, #32] } 8004ab4: 46c0 nop @ (mov r8, r8) 8004ab6: 46bd mov sp, r7 8004ab8: b006 add sp, #24 8004aba: bd80 pop {r7, pc} 8004abc: feff8fff .word 0xfeff8fff 8004ac0: fffffcff .word 0xfffffcff 8004ac4: 40012c00 .word 0x40012c00 8004ac8: 40014400 .word 0x40014400 8004acc: 40014800 .word 0x40014800 8004ad0: fffffbff .word 0xfffffbff 8004ad4: fffff7ff .word 0xfffff7ff 08004ad8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8004ad8: b580 push {r7, lr} 8004ada: b086 sub sp, #24 8004adc: af00 add r7, sp, #0 8004ade: 6078 str r0, [r7, #4] 8004ae0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8004ae2: 687b ldr r3, [r7, #4] 8004ae4: 6a1b ldr r3, [r3, #32] 8004ae6: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8004ae8: 687b ldr r3, [r7, #4] 8004aea: 6a1b ldr r3, [r3, #32] 8004aec: 4a31 ldr r2, [pc, #196] @ (8004bb4 ) 8004aee: 401a ands r2, r3 8004af0: 687b ldr r3, [r7, #4] 8004af2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8004af4: 687b ldr r3, [r7, #4] 8004af6: 685b ldr r3, [r3, #4] 8004af8: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8004afa: 687b ldr r3, [r7, #4] 8004afc: 69db ldr r3, [r3, #28] 8004afe: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8004b00: 68fb ldr r3, [r7, #12] 8004b02: 4a2d ldr r2, [pc, #180] @ (8004bb8 ) 8004b04: 4013 ands r3, r2 8004b06: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8004b08: 68fb ldr r3, [r7, #12] 8004b0a: 2203 movs r2, #3 8004b0c: 4393 bics r3, r2 8004b0e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8004b10: 683b ldr r3, [r7, #0] 8004b12: 681b ldr r3, [r3, #0] 8004b14: 68fa ldr r2, [r7, #12] 8004b16: 4313 orrs r3, r2 8004b18: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8004b1a: 697b ldr r3, [r7, #20] 8004b1c: 4a27 ldr r2, [pc, #156] @ (8004bbc ) 8004b1e: 4013 ands r3, r2 8004b20: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8004b22: 683b ldr r3, [r7, #0] 8004b24: 689b ldr r3, [r3, #8] 8004b26: 021b lsls r3, r3, #8 8004b28: 697a ldr r2, [r7, #20] 8004b2a: 4313 orrs r3, r2 8004b2c: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8004b2e: 687b ldr r3, [r7, #4] 8004b30: 4a23 ldr r2, [pc, #140] @ (8004bc0 ) 8004b32: 4293 cmp r3, r2 8004b34: d10d bne.n 8004b52 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8004b36: 697b ldr r3, [r7, #20] 8004b38: 4a22 ldr r2, [pc, #136] @ (8004bc4 ) 8004b3a: 4013 ands r3, r2 8004b3c: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8004b3e: 683b ldr r3, [r7, #0] 8004b40: 68db ldr r3, [r3, #12] 8004b42: 021b lsls r3, r3, #8 8004b44: 697a ldr r2, [r7, #20] 8004b46: 4313 orrs r3, r2 8004b48: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8004b4a: 697b ldr r3, [r7, #20] 8004b4c: 4a1e ldr r2, [pc, #120] @ (8004bc8 ) 8004b4e: 4013 ands r3, r2 8004b50: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8004b52: 687b ldr r3, [r7, #4] 8004b54: 4a1a ldr r2, [pc, #104] @ (8004bc0 ) 8004b56: 4293 cmp r3, r2 8004b58: d007 beq.n 8004b6a 8004b5a: 687b ldr r3, [r7, #4] 8004b5c: 4a1b ldr r2, [pc, #108] @ (8004bcc ) 8004b5e: 4293 cmp r3, r2 8004b60: d003 beq.n 8004b6a 8004b62: 687b ldr r3, [r7, #4] 8004b64: 4a1a ldr r2, [pc, #104] @ (8004bd0 ) 8004b66: 4293 cmp r3, r2 8004b68: d113 bne.n 8004b92 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8004b6a: 693b ldr r3, [r7, #16] 8004b6c: 4a19 ldr r2, [pc, #100] @ (8004bd4 ) 8004b6e: 4013 ands r3, r2 8004b70: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8004b72: 693b ldr r3, [r7, #16] 8004b74: 4a18 ldr r2, [pc, #96] @ (8004bd8 ) 8004b76: 4013 ands r3, r2 8004b78: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8004b7a: 683b ldr r3, [r7, #0] 8004b7c: 695b ldr r3, [r3, #20] 8004b7e: 011b lsls r3, r3, #4 8004b80: 693a ldr r2, [r7, #16] 8004b82: 4313 orrs r3, r2 8004b84: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8004b86: 683b ldr r3, [r7, #0] 8004b88: 699b ldr r3, [r3, #24] 8004b8a: 011b lsls r3, r3, #4 8004b8c: 693a ldr r2, [r7, #16] 8004b8e: 4313 orrs r3, r2 8004b90: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8004b92: 687b ldr r3, [r7, #4] 8004b94: 693a ldr r2, [r7, #16] 8004b96: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8004b98: 687b ldr r3, [r7, #4] 8004b9a: 68fa ldr r2, [r7, #12] 8004b9c: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8004b9e: 683b ldr r3, [r7, #0] 8004ba0: 685a ldr r2, [r3, #4] 8004ba2: 687b ldr r3, [r7, #4] 8004ba4: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8004ba6: 687b ldr r3, [r7, #4] 8004ba8: 697a ldr r2, [r7, #20] 8004baa: 621a str r2, [r3, #32] } 8004bac: 46c0 nop @ (mov r8, r8) 8004bae: 46bd mov sp, r7 8004bb0: b006 add sp, #24 8004bb2: bd80 pop {r7, pc} 8004bb4: fffffeff .word 0xfffffeff 8004bb8: fffeff8f .word 0xfffeff8f 8004bbc: fffffdff .word 0xfffffdff 8004bc0: 40012c00 .word 0x40012c00 8004bc4: fffff7ff .word 0xfffff7ff 8004bc8: fffffbff .word 0xfffffbff 8004bcc: 40014400 .word 0x40014400 8004bd0: 40014800 .word 0x40014800 8004bd4: ffffefff .word 0xffffefff 8004bd8: ffffdfff .word 0xffffdfff 08004bdc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8004bdc: b580 push {r7, lr} 8004bde: b086 sub sp, #24 8004be0: af00 add r7, sp, #0 8004be2: 6078 str r0, [r7, #4] 8004be4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8004be6: 687b ldr r3, [r7, #4] 8004be8: 6a1b ldr r3, [r3, #32] 8004bea: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8004bec: 687b ldr r3, [r7, #4] 8004bee: 6a1b ldr r3, [r3, #32] 8004bf0: 4a24 ldr r2, [pc, #144] @ (8004c84 ) 8004bf2: 401a ands r2, r3 8004bf4: 687b ldr r3, [r7, #4] 8004bf6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8004bf8: 687b ldr r3, [r7, #4] 8004bfa: 685b ldr r3, [r3, #4] 8004bfc: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8004bfe: 687b ldr r3, [r7, #4] 8004c00: 69db ldr r3, [r3, #28] 8004c02: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8004c04: 68fb ldr r3, [r7, #12] 8004c06: 4a20 ldr r2, [pc, #128] @ (8004c88 ) 8004c08: 4013 ands r3, r2 8004c0a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8004c0c: 68fb ldr r3, [r7, #12] 8004c0e: 4a1f ldr r2, [pc, #124] @ (8004c8c ) 8004c10: 4013 ands r3, r2 8004c12: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8004c14: 683b ldr r3, [r7, #0] 8004c16: 681b ldr r3, [r3, #0] 8004c18: 021b lsls r3, r3, #8 8004c1a: 68fa ldr r2, [r7, #12] 8004c1c: 4313 orrs r3, r2 8004c1e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8004c20: 693b ldr r3, [r7, #16] 8004c22: 4a1b ldr r2, [pc, #108] @ (8004c90 ) 8004c24: 4013 ands r3, r2 8004c26: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8004c28: 683b ldr r3, [r7, #0] 8004c2a: 689b ldr r3, [r3, #8] 8004c2c: 031b lsls r3, r3, #12 8004c2e: 693a ldr r2, [r7, #16] 8004c30: 4313 orrs r3, r2 8004c32: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8004c34: 687b ldr r3, [r7, #4] 8004c36: 4a17 ldr r2, [pc, #92] @ (8004c94 ) 8004c38: 4293 cmp r3, r2 8004c3a: d007 beq.n 8004c4c 8004c3c: 687b ldr r3, [r7, #4] 8004c3e: 4a16 ldr r2, [pc, #88] @ (8004c98 ) 8004c40: 4293 cmp r3, r2 8004c42: d003 beq.n 8004c4c 8004c44: 687b ldr r3, [r7, #4] 8004c46: 4a15 ldr r2, [pc, #84] @ (8004c9c ) 8004c48: 4293 cmp r3, r2 8004c4a: d109 bne.n 8004c60 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8004c4c: 697b ldr r3, [r7, #20] 8004c4e: 4a14 ldr r2, [pc, #80] @ (8004ca0 ) 8004c50: 4013 ands r3, r2 8004c52: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8004c54: 683b ldr r3, [r7, #0] 8004c56: 695b ldr r3, [r3, #20] 8004c58: 019b lsls r3, r3, #6 8004c5a: 697a ldr r2, [r7, #20] 8004c5c: 4313 orrs r3, r2 8004c5e: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8004c60: 687b ldr r3, [r7, #4] 8004c62: 697a ldr r2, [r7, #20] 8004c64: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8004c66: 687b ldr r3, [r7, #4] 8004c68: 68fa ldr r2, [r7, #12] 8004c6a: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8004c6c: 683b ldr r3, [r7, #0] 8004c6e: 685a ldr r2, [r3, #4] 8004c70: 687b ldr r3, [r7, #4] 8004c72: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8004c74: 687b ldr r3, [r7, #4] 8004c76: 693a ldr r2, [r7, #16] 8004c78: 621a str r2, [r3, #32] } 8004c7a: 46c0 nop @ (mov r8, r8) 8004c7c: 46bd mov sp, r7 8004c7e: b006 add sp, #24 8004c80: bd80 pop {r7, pc} 8004c82: 46c0 nop @ (mov r8, r8) 8004c84: ffffefff .word 0xffffefff 8004c88: feff8fff .word 0xfeff8fff 8004c8c: fffffcff .word 0xfffffcff 8004c90: ffffdfff .word 0xffffdfff 8004c94: 40012c00 .word 0x40012c00 8004c98: 40014400 .word 0x40014400 8004c9c: 40014800 .word 0x40014800 8004ca0: ffffbfff .word 0xffffbfff 08004ca4 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8004ca4: b580 push {r7, lr} 8004ca6: b086 sub sp, #24 8004ca8: af00 add r7, sp, #0 8004caa: 6078 str r0, [r7, #4] 8004cac: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8004cae: 687b ldr r3, [r7, #4] 8004cb0: 6a1b ldr r3, [r3, #32] 8004cb2: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 8004cb4: 687b ldr r3, [r7, #4] 8004cb6: 6a1b ldr r3, [r3, #32] 8004cb8: 4a21 ldr r2, [pc, #132] @ (8004d40 ) 8004cba: 401a ands r2, r3 8004cbc: 687b ldr r3, [r7, #4] 8004cbe: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8004cc0: 687b ldr r3, [r7, #4] 8004cc2: 685b ldr r3, [r3, #4] 8004cc4: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8004cc6: 687b ldr r3, [r7, #4] 8004cc8: 6d5b ldr r3, [r3, #84] @ 0x54 8004cca: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 8004ccc: 68fb ldr r3, [r7, #12] 8004cce: 4a1d ldr r2, [pc, #116] @ (8004d44 ) 8004cd0: 4013 ands r3, r2 8004cd2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8004cd4: 683b ldr r3, [r7, #0] 8004cd6: 681b ldr r3, [r3, #0] 8004cd8: 68fa ldr r2, [r7, #12] 8004cda: 4313 orrs r3, r2 8004cdc: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 8004cde: 693b ldr r3, [r7, #16] 8004ce0: 4a19 ldr r2, [pc, #100] @ (8004d48 ) 8004ce2: 4013 ands r3, r2 8004ce4: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 8004ce6: 683b ldr r3, [r7, #0] 8004ce8: 689b ldr r3, [r3, #8] 8004cea: 041b lsls r3, r3, #16 8004cec: 693a ldr r2, [r7, #16] 8004cee: 4313 orrs r3, r2 8004cf0: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8004cf2: 687b ldr r3, [r7, #4] 8004cf4: 4a15 ldr r2, [pc, #84] @ (8004d4c ) 8004cf6: 4293 cmp r3, r2 8004cf8: d007 beq.n 8004d0a 8004cfa: 687b ldr r3, [r7, #4] 8004cfc: 4a14 ldr r2, [pc, #80] @ (8004d50 ) 8004cfe: 4293 cmp r3, r2 8004d00: d003 beq.n 8004d0a 8004d02: 687b ldr r3, [r7, #4] 8004d04: 4a13 ldr r2, [pc, #76] @ (8004d54 ) 8004d06: 4293 cmp r3, r2 8004d08: d109 bne.n 8004d1e { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 8004d0a: 697b ldr r3, [r7, #20] 8004d0c: 4a0c ldr r2, [pc, #48] @ (8004d40 ) 8004d0e: 4013 ands r3, r2 8004d10: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 8004d12: 683b ldr r3, [r7, #0] 8004d14: 695b ldr r3, [r3, #20] 8004d16: 021b lsls r3, r3, #8 8004d18: 697a ldr r2, [r7, #20] 8004d1a: 4313 orrs r3, r2 8004d1c: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8004d1e: 687b ldr r3, [r7, #4] 8004d20: 697a ldr r2, [r7, #20] 8004d22: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8004d24: 687b ldr r3, [r7, #4] 8004d26: 68fa ldr r2, [r7, #12] 8004d28: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 8004d2a: 683b ldr r3, [r7, #0] 8004d2c: 685a ldr r2, [r3, #4] 8004d2e: 687b ldr r3, [r7, #4] 8004d30: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8004d32: 687b ldr r3, [r7, #4] 8004d34: 693a ldr r2, [r7, #16] 8004d36: 621a str r2, [r3, #32] } 8004d38: 46c0 nop @ (mov r8, r8) 8004d3a: 46bd mov sp, r7 8004d3c: b006 add sp, #24 8004d3e: bd80 pop {r7, pc} 8004d40: fffeffff .word 0xfffeffff 8004d44: fffeff8f .word 0xfffeff8f 8004d48: fffdffff .word 0xfffdffff 8004d4c: 40012c00 .word 0x40012c00 8004d50: 40014400 .word 0x40014400 8004d54: 40014800 .word 0x40014800 08004d58 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8004d58: b580 push {r7, lr} 8004d5a: b086 sub sp, #24 8004d5c: af00 add r7, sp, #0 8004d5e: 6078 str r0, [r7, #4] 8004d60: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8004d62: 687b ldr r3, [r7, #4] 8004d64: 6a1b ldr r3, [r3, #32] 8004d66: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 8004d68: 687b ldr r3, [r7, #4] 8004d6a: 6a1b ldr r3, [r3, #32] 8004d6c: 4a22 ldr r2, [pc, #136] @ (8004df8 ) 8004d6e: 401a ands r2, r3 8004d70: 687b ldr r3, [r7, #4] 8004d72: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8004d74: 687b ldr r3, [r7, #4] 8004d76: 685b ldr r3, [r3, #4] 8004d78: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8004d7a: 687b ldr r3, [r7, #4] 8004d7c: 6d5b ldr r3, [r3, #84] @ 0x54 8004d7e: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 8004d80: 68fb ldr r3, [r7, #12] 8004d82: 4a1e ldr r2, [pc, #120] @ (8004dfc ) 8004d84: 4013 ands r3, r2 8004d86: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8004d88: 683b ldr r3, [r7, #0] 8004d8a: 681b ldr r3, [r3, #0] 8004d8c: 021b lsls r3, r3, #8 8004d8e: 68fa ldr r2, [r7, #12] 8004d90: 4313 orrs r3, r2 8004d92: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 8004d94: 693b ldr r3, [r7, #16] 8004d96: 4a1a ldr r2, [pc, #104] @ (8004e00 ) 8004d98: 4013 ands r3, r2 8004d9a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 8004d9c: 683b ldr r3, [r7, #0] 8004d9e: 689b ldr r3, [r3, #8] 8004da0: 051b lsls r3, r3, #20 8004da2: 693a ldr r2, [r7, #16] 8004da4: 4313 orrs r3, r2 8004da6: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8004da8: 687b ldr r3, [r7, #4] 8004daa: 4a16 ldr r2, [pc, #88] @ (8004e04 ) 8004dac: 4293 cmp r3, r2 8004dae: d007 beq.n 8004dc0 8004db0: 687b ldr r3, [r7, #4] 8004db2: 4a15 ldr r2, [pc, #84] @ (8004e08 ) 8004db4: 4293 cmp r3, r2 8004db6: d003 beq.n 8004dc0 8004db8: 687b ldr r3, [r7, #4] 8004dba: 4a14 ldr r2, [pc, #80] @ (8004e0c ) 8004dbc: 4293 cmp r3, r2 8004dbe: d109 bne.n 8004dd4 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 8004dc0: 697b ldr r3, [r7, #20] 8004dc2: 4a13 ldr r2, [pc, #76] @ (8004e10 ) 8004dc4: 4013 ands r3, r2 8004dc6: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 8004dc8: 683b ldr r3, [r7, #0] 8004dca: 695b ldr r3, [r3, #20] 8004dcc: 029b lsls r3, r3, #10 8004dce: 697a ldr r2, [r7, #20] 8004dd0: 4313 orrs r3, r2 8004dd2: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8004dd4: 687b ldr r3, [r7, #4] 8004dd6: 697a ldr r2, [r7, #20] 8004dd8: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8004dda: 687b ldr r3, [r7, #4] 8004ddc: 68fa ldr r2, [r7, #12] 8004dde: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 8004de0: 683b ldr r3, [r7, #0] 8004de2: 685a ldr r2, [r3, #4] 8004de4: 687b ldr r3, [r7, #4] 8004de6: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8004de8: 687b ldr r3, [r7, #4] 8004dea: 693a ldr r2, [r7, #16] 8004dec: 621a str r2, [r3, #32] } 8004dee: 46c0 nop @ (mov r8, r8) 8004df0: 46bd mov sp, r7 8004df2: b006 add sp, #24 8004df4: bd80 pop {r7, pc} 8004df6: 46c0 nop @ (mov r8, r8) 8004df8: ffefffff .word 0xffefffff 8004dfc: feff8fff .word 0xfeff8fff 8004e00: ffdfffff .word 0xffdfffff 8004e04: 40012c00 .word 0x40012c00 8004e08: 40014400 .word 0x40014400 8004e0c: 40014800 .word 0x40014800 8004e10: fffbffff .word 0xfffbffff 08004e14 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8004e14: b580 push {r7, lr} 8004e16: b084 sub sp, #16 8004e18: af00 add r7, sp, #0 8004e1a: 6078 str r0, [r7, #4] 8004e1c: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8004e1e: 687b ldr r3, [r7, #4] 8004e20: 223c movs r2, #60 @ 0x3c 8004e22: 5c9b ldrb r3, [r3, r2] 8004e24: 2b01 cmp r3, #1 8004e26: d101 bne.n 8004e2c 8004e28: 2302 movs r3, #2 8004e2a: e04a b.n 8004ec2 8004e2c: 687b ldr r3, [r7, #4] 8004e2e: 223c movs r2, #60 @ 0x3c 8004e30: 2101 movs r1, #1 8004e32: 5499 strb r1, [r3, r2] /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8004e34: 687b ldr r3, [r7, #4] 8004e36: 223d movs r2, #61 @ 0x3d 8004e38: 2102 movs r1, #2 8004e3a: 5499 strb r1, [r3, r2] /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8004e3c: 687b ldr r3, [r7, #4] 8004e3e: 681b ldr r3, [r3, #0] 8004e40: 685b ldr r3, [r3, #4] 8004e42: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8004e44: 687b ldr r3, [r7, #4] 8004e46: 681b ldr r3, [r3, #0] 8004e48: 689b ldr r3, [r3, #8] 8004e4a: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8004e4c: 687b ldr r3, [r7, #4] 8004e4e: 681b ldr r3, [r3, #0] 8004e50: 4a1e ldr r2, [pc, #120] @ (8004ecc ) 8004e52: 4293 cmp r3, r2 8004e54: d108 bne.n 8004e68 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 8004e56: 68fb ldr r3, [r7, #12] 8004e58: 4a1d ldr r2, [pc, #116] @ (8004ed0 ) 8004e5a: 4013 ands r3, r2 8004e5c: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 8004e5e: 683b ldr r3, [r7, #0] 8004e60: 685b ldr r3, [r3, #4] 8004e62: 68fa ldr r2, [r7, #12] 8004e64: 4313 orrs r3, r2 8004e66: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8004e68: 68fb ldr r3, [r7, #12] 8004e6a: 2270 movs r2, #112 @ 0x70 8004e6c: 4393 bics r3, r2 8004e6e: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8004e70: 683b ldr r3, [r7, #0] 8004e72: 681b ldr r3, [r3, #0] 8004e74: 68fa ldr r2, [r7, #12] 8004e76: 4313 orrs r3, r2 8004e78: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8004e7a: 687b ldr r3, [r7, #4] 8004e7c: 681b ldr r3, [r3, #0] 8004e7e: 68fa ldr r2, [r7, #12] 8004e80: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8004e82: 687b ldr r3, [r7, #4] 8004e84: 681b ldr r3, [r3, #0] 8004e86: 4a11 ldr r2, [pc, #68] @ (8004ecc ) 8004e88: 4293 cmp r3, r2 8004e8a: d004 beq.n 8004e96 8004e8c: 687b ldr r3, [r7, #4] 8004e8e: 681b ldr r3, [r3, #0] 8004e90: 4a10 ldr r2, [pc, #64] @ (8004ed4 ) 8004e92: 4293 cmp r3, r2 8004e94: d10c bne.n 8004eb0 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8004e96: 68bb ldr r3, [r7, #8] 8004e98: 2280 movs r2, #128 @ 0x80 8004e9a: 4393 bics r3, r2 8004e9c: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8004e9e: 683b ldr r3, [r7, #0] 8004ea0: 689b ldr r3, [r3, #8] 8004ea2: 68ba ldr r2, [r7, #8] 8004ea4: 4313 orrs r3, r2 8004ea6: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8004ea8: 687b ldr r3, [r7, #4] 8004eaa: 681b ldr r3, [r3, #0] 8004eac: 68ba ldr r2, [r7, #8] 8004eae: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8004eb0: 687b ldr r3, [r7, #4] 8004eb2: 223d movs r2, #61 @ 0x3d 8004eb4: 2101 movs r1, #1 8004eb6: 5499 strb r1, [r3, r2] __HAL_UNLOCK(htim); 8004eb8: 687b ldr r3, [r7, #4] 8004eba: 223c movs r2, #60 @ 0x3c 8004ebc: 2100 movs r1, #0 8004ebe: 5499 strb r1, [r3, r2] return HAL_OK; 8004ec0: 2300 movs r3, #0 } 8004ec2: 0018 movs r0, r3 8004ec4: 46bd mov sp, r7 8004ec6: b004 add sp, #16 8004ec8: bd80 pop {r7, pc} 8004eca: 46c0 nop @ (mov r8, r8) 8004ecc: 40012c00 .word 0x40012c00 8004ed0: ff0fffff .word 0xff0fffff 8004ed4: 40000400 .word 0x40000400 08004ed8 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 8004ed8: b580 push {r7, lr} 8004eda: b084 sub sp, #16 8004edc: af00 add r7, sp, #0 8004ede: 6078 str r0, [r7, #4] 8004ee0: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 8004ee2: 2300 movs r3, #0 8004ee4: 60fb str r3, [r7, #12] assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); 8004ee6: 687b ldr r3, [r7, #4] 8004ee8: 223c movs r2, #60 @ 0x3c 8004eea: 5c9b ldrb r3, [r3, r2] 8004eec: 2b01 cmp r3, #1 8004eee: d101 bne.n 8004ef4 8004ef0: 2302 movs r3, #2 8004ef2: e06f b.n 8004fd4 8004ef4: 687b ldr r3, [r7, #4] 8004ef6: 223c movs r2, #60 @ 0x3c 8004ef8: 2101 movs r1, #1 8004efa: 5499 strb r1, [r3, r2] /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 8004efc: 68fb ldr r3, [r7, #12] 8004efe: 22ff movs r2, #255 @ 0xff 8004f00: 4393 bics r3, r2 8004f02: 001a movs r2, r3 8004f04: 683b ldr r3, [r7, #0] 8004f06: 68db ldr r3, [r3, #12] 8004f08: 4313 orrs r3, r2 8004f0a: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 8004f0c: 68fb ldr r3, [r7, #12] 8004f0e: 4a33 ldr r2, [pc, #204] @ (8004fdc ) 8004f10: 401a ands r2, r3 8004f12: 683b ldr r3, [r7, #0] 8004f14: 689b ldr r3, [r3, #8] 8004f16: 4313 orrs r3, r2 8004f18: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 8004f1a: 68fb ldr r3, [r7, #12] 8004f1c: 4a30 ldr r2, [pc, #192] @ (8004fe0 ) 8004f1e: 401a ands r2, r3 8004f20: 683b ldr r3, [r7, #0] 8004f22: 685b ldr r3, [r3, #4] 8004f24: 4313 orrs r3, r2 8004f26: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 8004f28: 68fb ldr r3, [r7, #12] 8004f2a: 4a2e ldr r2, [pc, #184] @ (8004fe4 ) 8004f2c: 401a ands r2, r3 8004f2e: 683b ldr r3, [r7, #0] 8004f30: 681b ldr r3, [r3, #0] 8004f32: 4313 orrs r3, r2 8004f34: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 8004f36: 68fb ldr r3, [r7, #12] 8004f38: 4a2b ldr r2, [pc, #172] @ (8004fe8 ) 8004f3a: 401a ands r2, r3 8004f3c: 683b ldr r3, [r7, #0] 8004f3e: 691b ldr r3, [r3, #16] 8004f40: 4313 orrs r3, r2 8004f42: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 8004f44: 68fb ldr r3, [r7, #12] 8004f46: 4a29 ldr r2, [pc, #164] @ (8004fec ) 8004f48: 401a ands r2, r3 8004f4a: 683b ldr r3, [r7, #0] 8004f4c: 695b ldr r3, [r3, #20] 8004f4e: 4313 orrs r3, r2 8004f50: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 8004f52: 68fb ldr r3, [r7, #12] 8004f54: 4a26 ldr r2, [pc, #152] @ (8004ff0 ) 8004f56: 401a ands r2, r3 8004f58: 683b ldr r3, [r7, #0] 8004f5a: 6b1b ldr r3, [r3, #48] @ 0x30 8004f5c: 4313 orrs r3, r2 8004f5e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 8004f60: 68fb ldr r3, [r7, #12] 8004f62: 4a24 ldr r2, [pc, #144] @ (8004ff4 ) 8004f64: 401a ands r2, r3 8004f66: 683b ldr r3, [r7, #0] 8004f68: 699b ldr r3, [r3, #24] 8004f6a: 041b lsls r3, r3, #16 8004f6c: 4313 orrs r3, r2 8004f6e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); 8004f70: 68fb ldr r3, [r7, #12] 8004f72: 4a21 ldr r2, [pc, #132] @ (8004ff8 ) 8004f74: 401a ands r2, r3 8004f76: 683b ldr r3, [r7, #0] 8004f78: 69db ldr r3, [r3, #28] 8004f7a: 4313 orrs r3, r2 8004f7c: 60fb str r3, [r7, #12] if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 8004f7e: 687b ldr r3, [r7, #4] 8004f80: 681b ldr r3, [r3, #0] 8004f82: 4a1e ldr r2, [pc, #120] @ (8004ffc ) 8004f84: 4293 cmp r3, r2 8004f86: d11c bne.n 8004fc2 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 8004f88: 68fb ldr r3, [r7, #12] 8004f8a: 4a1d ldr r2, [pc, #116] @ (8005000 ) 8004f8c: 401a ands r2, r3 8004f8e: 683b ldr r3, [r7, #0] 8004f90: 6a9b ldr r3, [r3, #40] @ 0x28 8004f92: 051b lsls r3, r3, #20 8004f94: 4313 orrs r3, r2 8004f96: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 8004f98: 68fb ldr r3, [r7, #12] 8004f9a: 4a1a ldr r2, [pc, #104] @ (8005004 ) 8004f9c: 401a ands r2, r3 8004f9e: 683b ldr r3, [r7, #0] 8004fa0: 6a1b ldr r3, [r3, #32] 8004fa2: 4313 orrs r3, r2 8004fa4: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 8004fa6: 68fb ldr r3, [r7, #12] 8004fa8: 4a17 ldr r2, [pc, #92] @ (8005008 ) 8004faa: 401a ands r2, r3 8004fac: 683b ldr r3, [r7, #0] 8004fae: 6a5b ldr r3, [r3, #36] @ 0x24 8004fb0: 4313 orrs r3, r2 8004fb2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); 8004fb4: 68fb ldr r3, [r7, #12] 8004fb6: 4a15 ldr r2, [pc, #84] @ (800500c ) 8004fb8: 401a ands r2, r3 8004fba: 683b ldr r3, [r7, #0] 8004fbc: 6adb ldr r3, [r3, #44] @ 0x2c 8004fbe: 4313 orrs r3, r2 8004fc0: 60fb str r3, [r7, #12] } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 8004fc2: 687b ldr r3, [r7, #4] 8004fc4: 681b ldr r3, [r3, #0] 8004fc6: 68fa ldr r2, [r7, #12] 8004fc8: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 8004fca: 687b ldr r3, [r7, #4] 8004fcc: 223c movs r2, #60 @ 0x3c 8004fce: 2100 movs r1, #0 8004fd0: 5499 strb r1, [r3, r2] return HAL_OK; 8004fd2: 2300 movs r3, #0 } 8004fd4: 0018 movs r0, r3 8004fd6: 46bd mov sp, r7 8004fd8: b004 add sp, #16 8004fda: bd80 pop {r7, pc} 8004fdc: fffffcff .word 0xfffffcff 8004fe0: fffffbff .word 0xfffffbff 8004fe4: fffff7ff .word 0xfffff7ff 8004fe8: ffffefff .word 0xffffefff 8004fec: ffffdfff .word 0xffffdfff 8004ff0: ffffbfff .word 0xffffbfff 8004ff4: fff0ffff .word 0xfff0ffff 8004ff8: efffffff .word 0xefffffff 8004ffc: 40012c00 .word 0x40012c00 8005000: ff0fffff .word 0xff0fffff 8005004: feffffff .word 0xfeffffff 8005008: fdffffff .word 0xfdffffff 800500c: dfffffff .word 0xdfffffff 08005010 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8005010: b580 push {r7, lr} 8005012: b082 sub sp, #8 8005014: af00 add r7, sp, #0 8005016: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8005018: 687b ldr r3, [r7, #4] 800501a: 2b00 cmp r3, #0 800501c: d101 bne.n 8005022 { return HAL_ERROR; 800501e: 2301 movs r3, #1 8005020: e046 b.n 80050b0 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 8005022: 687b ldr r3, [r7, #4] 8005024: 2288 movs r2, #136 @ 0x88 8005026: 589b ldr r3, [r3, r2] 8005028: 2b00 cmp r3, #0 800502a: d107 bne.n 800503c { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800502c: 687b ldr r3, [r7, #4] 800502e: 2284 movs r2, #132 @ 0x84 8005030: 2100 movs r1, #0 8005032: 5499 strb r1, [r3, r2] /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005034: 687b ldr r3, [r7, #4] 8005036: 0018 movs r0, r3 8005038: f7fb fe0a bl 8000c50 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 800503c: 687b ldr r3, [r7, #4] 800503e: 2288 movs r2, #136 @ 0x88 8005040: 2124 movs r1, #36 @ 0x24 8005042: 5099 str r1, [r3, r2] __HAL_UART_DISABLE(huart); 8005044: 687b ldr r3, [r7, #4] 8005046: 681b ldr r3, [r3, #0] 8005048: 681a ldr r2, [r3, #0] 800504a: 687b ldr r3, [r7, #4] 800504c: 681b ldr r3, [r3, #0] 800504e: 2101 movs r1, #1 8005050: 438a bics r2, r1 8005052: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 8005054: 687b ldr r3, [r7, #4] 8005056: 6a9b ldr r3, [r3, #40] @ 0x28 8005058: 2b00 cmp r3, #0 800505a: d003 beq.n 8005064 { UART_AdvFeatureConfig(huart); 800505c: 687b ldr r3, [r7, #4] 800505e: 0018 movs r0, r3 8005060: f000 fae4 bl 800562c } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 8005064: 687b ldr r3, [r7, #4] 8005066: 0018 movs r0, r3 8005068: f000 f976 bl 8005358 800506c: 0003 movs r3, r0 800506e: 2b01 cmp r3, #1 8005070: d101 bne.n 8005076 { return HAL_ERROR; 8005072: 2301 movs r3, #1 8005074: e01c b.n 80050b0 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005076: 687b ldr r3, [r7, #4] 8005078: 681b ldr r3, [r3, #0] 800507a: 685a ldr r2, [r3, #4] 800507c: 687b ldr r3, [r7, #4] 800507e: 681b ldr r3, [r3, #0] 8005080: 490d ldr r1, [pc, #52] @ (80050b8 ) 8005082: 400a ands r2, r1 8005084: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005086: 687b ldr r3, [r7, #4] 8005088: 681b ldr r3, [r3, #0] 800508a: 689a ldr r2, [r3, #8] 800508c: 687b ldr r3, [r7, #4] 800508e: 681b ldr r3, [r3, #0] 8005090: 212a movs r1, #42 @ 0x2a 8005092: 438a bics r2, r1 8005094: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 8005096: 687b ldr r3, [r7, #4] 8005098: 681b ldr r3, [r3, #0] 800509a: 681a ldr r2, [r3, #0] 800509c: 687b ldr r3, [r7, #4] 800509e: 681b ldr r3, [r3, #0] 80050a0: 2101 movs r1, #1 80050a2: 430a orrs r2, r1 80050a4: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 80050a6: 687b ldr r3, [r7, #4] 80050a8: 0018 movs r0, r3 80050aa: f000 fb73 bl 8005794 80050ae: 0003 movs r3, r0 } 80050b0: 0018 movs r0, r3 80050b2: 46bd mov sp, r7 80050b4: b002 add sp, #8 80050b6: bd80 pop {r7, pc} 80050b8: ffffb7ff .word 0xffffb7ff 080050bc : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 80050bc: b580 push {r7, lr} 80050be: b088 sub sp, #32 80050c0: af00 add r7, sp, #0 80050c2: 60f8 str r0, [r7, #12] 80050c4: 60b9 str r1, [r7, #8] 80050c6: 1dbb adds r3, r7, #6 80050c8: 801a strh r2, [r3, #0] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80050ca: 68fb ldr r3, [r7, #12] 80050cc: 2288 movs r2, #136 @ 0x88 80050ce: 589b ldr r3, [r3, r2] 80050d0: 2b20 cmp r3, #32 80050d2: d000 beq.n 80050d6 80050d4: e079 b.n 80051ca { if ((pData == NULL) || (Size == 0U)) 80050d6: 68bb ldr r3, [r7, #8] 80050d8: 2b00 cmp r3, #0 80050da: d003 beq.n 80050e4 80050dc: 1dbb adds r3, r7, #6 80050de: 881b ldrh r3, [r3, #0] 80050e0: 2b00 cmp r3, #0 80050e2: d101 bne.n 80050e8 { return HAL_ERROR; 80050e4: 2301 movs r3, #1 80050e6: e071 b.n 80051cc } /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter should be aligned on a u16 frontier, as data copy into TDR will be handled by DMA from a u16 frontier. */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80050e8: 68fb ldr r3, [r7, #12] 80050ea: 689a ldr r2, [r3, #8] 80050ec: 2380 movs r3, #128 @ 0x80 80050ee: 015b lsls r3, r3, #5 80050f0: 429a cmp r2, r3 80050f2: d109 bne.n 8005108 80050f4: 68fb ldr r3, [r7, #12] 80050f6: 691b ldr r3, [r3, #16] 80050f8: 2b00 cmp r3, #0 80050fa: d105 bne.n 8005108 { if ((((uint32_t)pData) & 1U) != 0U) 80050fc: 68bb ldr r3, [r7, #8] 80050fe: 2201 movs r2, #1 8005100: 4013 ands r3, r2 8005102: d001 beq.n 8005108 { return HAL_ERROR; 8005104: 2301 movs r3, #1 8005106: e061 b.n 80051cc } } huart->pTxBuffPtr = pData; 8005108: 68fb ldr r3, [r7, #12] 800510a: 68ba ldr r2, [r7, #8] 800510c: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 800510e: 68fb ldr r3, [r7, #12] 8005110: 1dba adds r2, r7, #6 8005112: 2154 movs r1, #84 @ 0x54 8005114: 8812 ldrh r2, [r2, #0] 8005116: 525a strh r2, [r3, r1] huart->TxXferCount = Size; 8005118: 68fb ldr r3, [r7, #12] 800511a: 1dba adds r2, r7, #6 800511c: 2156 movs r1, #86 @ 0x56 800511e: 8812 ldrh r2, [r2, #0] 8005120: 525a strh r2, [r3, r1] huart->ErrorCode = HAL_UART_ERROR_NONE; 8005122: 68fb ldr r3, [r7, #12] 8005124: 2290 movs r2, #144 @ 0x90 8005126: 2100 movs r1, #0 8005128: 5099 str r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY_TX; 800512a: 68fb ldr r3, [r7, #12] 800512c: 2288 movs r2, #136 @ 0x88 800512e: 2121 movs r1, #33 @ 0x21 8005130: 5099 str r1, [r3, r2] if (huart->hdmatx != NULL) 8005132: 68fb ldr r3, [r7, #12] 8005134: 6fdb ldr r3, [r3, #124] @ 0x7c 8005136: 2b00 cmp r3, #0 8005138: d028 beq.n 800518c { /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 800513a: 68fb ldr r3, [r7, #12] 800513c: 6fdb ldr r3, [r3, #124] @ 0x7c 800513e: 4a25 ldr r2, [pc, #148] @ (80051d4 ) 8005140: 62da str r2, [r3, #44] @ 0x2c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8005142: 68fb ldr r3, [r7, #12] 8005144: 6fdb ldr r3, [r3, #124] @ 0x7c 8005146: 4a24 ldr r2, [pc, #144] @ (80051d8 ) 8005148: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 800514a: 68fb ldr r3, [r7, #12] 800514c: 6fdb ldr r3, [r3, #124] @ 0x7c 800514e: 4a23 ldr r2, [pc, #140] @ (80051dc ) 8005150: 635a str r2, [r3, #52] @ 0x34 /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8005152: 68fb ldr r3, [r7, #12] 8005154: 6fdb ldr r3, [r3, #124] @ 0x7c 8005156: 2200 movs r2, #0 8005158: 639a str r2, [r3, #56] @ 0x38 /* Enable the UART transmit DMA channel */ if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) 800515a: 68fb ldr r3, [r7, #12] 800515c: 6fd8 ldr r0, [r3, #124] @ 0x7c 800515e: 68fb ldr r3, [r7, #12] 8005160: 6d1b ldr r3, [r3, #80] @ 0x50 8005162: 0019 movs r1, r3 8005164: 68fb ldr r3, [r7, #12] 8005166: 681b ldr r3, [r3, #0] 8005168: 3328 adds r3, #40 @ 0x28 800516a: 001a movs r2, r3 800516c: 1dbb adds r3, r7, #6 800516e: 881b ldrh r3, [r3, #0] 8005170: f7fd fe5a bl 8002e28 8005174: 1e03 subs r3, r0, #0 8005176: d009 beq.n 800518c { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8005178: 68fb ldr r3, [r7, #12] 800517a: 2290 movs r2, #144 @ 0x90 800517c: 2110 movs r1, #16 800517e: 5099 str r1, [r3, r2] /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 8005180: 68fb ldr r3, [r7, #12] 8005182: 2288 movs r2, #136 @ 0x88 8005184: 2120 movs r1, #32 8005186: 5099 str r1, [r3, r2] return HAL_ERROR; 8005188: 2301 movs r3, #1 800518a: e01f b.n 80051cc } } /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); 800518c: 68fb ldr r3, [r7, #12] 800518e: 681b ldr r3, [r3, #0] 8005190: 2240 movs r2, #64 @ 0x40 8005192: 621a str r2, [r3, #32] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005194: f3ef 8310 mrs r3, PRIMASK 8005198: 613b str r3, [r7, #16] return(result); 800519a: 693b ldr r3, [r7, #16] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 800519c: 61fb str r3, [r7, #28] 800519e: 2301 movs r3, #1 80051a0: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80051a2: 697b ldr r3, [r7, #20] 80051a4: f383 8810 msr PRIMASK, r3 } 80051a8: 46c0 nop @ (mov r8, r8) 80051aa: 68fb ldr r3, [r7, #12] 80051ac: 681b ldr r3, [r3, #0] 80051ae: 689a ldr r2, [r3, #8] 80051b0: 68fb ldr r3, [r7, #12] 80051b2: 681b ldr r3, [r3, #0] 80051b4: 2180 movs r1, #128 @ 0x80 80051b6: 430a orrs r2, r1 80051b8: 609a str r2, [r3, #8] 80051ba: 69fb ldr r3, [r7, #28] 80051bc: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80051be: 69bb ldr r3, [r7, #24] 80051c0: f383 8810 msr PRIMASK, r3 } 80051c4: 46c0 nop @ (mov r8, r8) return HAL_OK; 80051c6: 2300 movs r3, #0 80051c8: e000 b.n 80051cc } else { return HAL_BUSY; 80051ca: 2302 movs r3, #2 } } 80051cc: 0018 movs r0, r3 80051ce: 46bd mov sp, r7 80051d0: b008 add sp, #32 80051d2: bd80 pop {r7, pc} 80051d4: 08005c61 .word 0x08005c61 80051d8: 08005cf9 .word 0x08005cf9 80051dc: 08005e8b .word 0x08005e8b 080051e0 : * @brief Stop the DMA Transfer. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { 80051e0: b580 push {r7, lr} 80051e2: b08c sub sp, #48 @ 0x30 80051e4: af00 add r7, sp, #0 80051e6: 6078 str r0, [r7, #4] HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of the stream and the corresponding call back is executed. */ const HAL_UART_StateTypeDef gstate = huart->gState; 80051e8: 687b ldr r3, [r7, #4] 80051ea: 2288 movs r2, #136 @ 0x88 80051ec: 589b ldr r3, [r3, r2] 80051ee: 62fb str r3, [r7, #44] @ 0x2c const HAL_UART_StateTypeDef rxstate = huart->RxState; 80051f0: 687b ldr r3, [r7, #4] 80051f2: 228c movs r2, #140 @ 0x8c 80051f4: 589b ldr r3, [r3, r2] 80051f6: 62bb str r3, [r7, #40] @ 0x28 /* Stop UART DMA Tx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && 80051f8: 687b ldr r3, [r7, #4] 80051fa: 681b ldr r3, [r3, #0] 80051fc: 689b ldr r3, [r3, #8] 80051fe: 2280 movs r2, #128 @ 0x80 8005200: 4013 ands r3, r2 8005202: 2b80 cmp r3, #128 @ 0x80 8005204: d138 bne.n 8005278 8005206: 6afb ldr r3, [r7, #44] @ 0x2c 8005208: 2b21 cmp r3, #33 @ 0x21 800520a: d135 bne.n 8005278 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800520c: f3ef 8310 mrs r3, PRIMASK 8005210: 617b str r3, [r7, #20] return(result); 8005212: 697b ldr r3, [r7, #20] (gstate == HAL_UART_STATE_BUSY_TX)) { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8005214: 627b str r3, [r7, #36] @ 0x24 8005216: 2301 movs r3, #1 8005218: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800521a: 69bb ldr r3, [r7, #24] 800521c: f383 8810 msr PRIMASK, r3 } 8005220: 46c0 nop @ (mov r8, r8) 8005222: 687b ldr r3, [r7, #4] 8005224: 681b ldr r3, [r3, #0] 8005226: 689a ldr r2, [r3, #8] 8005228: 687b ldr r3, [r7, #4] 800522a: 681b ldr r3, [r3, #0] 800522c: 2180 movs r1, #128 @ 0x80 800522e: 438a bics r2, r1 8005230: 609a str r2, [r3, #8] 8005232: 6a7b ldr r3, [r7, #36] @ 0x24 8005234: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005236: 69fb ldr r3, [r7, #28] 8005238: f383 8810 msr PRIMASK, r3 } 800523c: 46c0 nop @ (mov r8, r8) /* Abort the UART DMA Tx channel */ if (huart->hdmatx != NULL) 800523e: 687b ldr r3, [r7, #4] 8005240: 6fdb ldr r3, [r3, #124] @ 0x7c 8005242: 2b00 cmp r3, #0 8005244: d014 beq.n 8005270 { if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) 8005246: 687b ldr r3, [r7, #4] 8005248: 6fdb ldr r3, [r3, #124] @ 0x7c 800524a: 0018 movs r0, r3 800524c: f7fd fe72 bl 8002f34 8005250: 1e03 subs r3, r0, #0 8005252: d00d beq.n 8005270 { if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) 8005254: 687b ldr r3, [r7, #4] 8005256: 6fdb ldr r3, [r3, #124] @ 0x7c 8005258: 0018 movs r0, r3 800525a: f7fd ff7f bl 800315c 800525e: 0003 movs r3, r0 8005260: 2b20 cmp r3, #32 8005262: d105 bne.n 8005270 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8005264: 687b ldr r3, [r7, #4] 8005266: 2290 movs r2, #144 @ 0x90 8005268: 2110 movs r1, #16 800526a: 5099 str r1, [r3, r2] return HAL_TIMEOUT; 800526c: 2303 movs r3, #3 800526e: e047 b.n 8005300 } } } UART_EndTxTransfer(huart); 8005270: 687b ldr r3, [r7, #4] 8005272: 0018 movs r0, r3 8005274: f000 fc4e bl 8005b14 } /* Stop UART DMA Rx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && 8005278: 687b ldr r3, [r7, #4] 800527a: 681b ldr r3, [r3, #0] 800527c: 689b ldr r3, [r3, #8] 800527e: 2240 movs r2, #64 @ 0x40 8005280: 4013 ands r3, r2 8005282: 2b40 cmp r3, #64 @ 0x40 8005284: d13b bne.n 80052fe 8005286: 6abb ldr r3, [r7, #40] @ 0x28 8005288: 2b22 cmp r3, #34 @ 0x22 800528a: d138 bne.n 80052fe __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800528c: f3ef 8310 mrs r3, PRIMASK 8005290: 60bb str r3, [r7, #8] return(result); 8005292: 68bb ldr r3, [r7, #8] (rxstate == HAL_UART_STATE_BUSY_RX)) { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005294: 623b str r3, [r7, #32] 8005296: 2301 movs r3, #1 8005298: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800529a: 68fb ldr r3, [r7, #12] 800529c: f383 8810 msr PRIMASK, r3 } 80052a0: 46c0 nop @ (mov r8, r8) 80052a2: 687b ldr r3, [r7, #4] 80052a4: 681b ldr r3, [r3, #0] 80052a6: 689a ldr r2, [r3, #8] 80052a8: 687b ldr r3, [r7, #4] 80052aa: 681b ldr r3, [r3, #0] 80052ac: 2140 movs r1, #64 @ 0x40 80052ae: 438a bics r2, r1 80052b0: 609a str r2, [r3, #8] 80052b2: 6a3b ldr r3, [r7, #32] 80052b4: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80052b6: 693b ldr r3, [r7, #16] 80052b8: f383 8810 msr PRIMASK, r3 } 80052bc: 46c0 nop @ (mov r8, r8) /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80052be: 687b ldr r3, [r7, #4] 80052c0: 2280 movs r2, #128 @ 0x80 80052c2: 589b ldr r3, [r3, r2] 80052c4: 2b00 cmp r3, #0 80052c6: d016 beq.n 80052f6 { if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) 80052c8: 687b ldr r3, [r7, #4] 80052ca: 2280 movs r2, #128 @ 0x80 80052cc: 589b ldr r3, [r3, r2] 80052ce: 0018 movs r0, r3 80052d0: f7fd fe30 bl 8002f34 80052d4: 1e03 subs r3, r0, #0 80052d6: d00e beq.n 80052f6 { if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) 80052d8: 687b ldr r3, [r7, #4] 80052da: 2280 movs r2, #128 @ 0x80 80052dc: 589b ldr r3, [r3, r2] 80052de: 0018 movs r0, r3 80052e0: f7fd ff3c bl 800315c 80052e4: 0003 movs r3, r0 80052e6: 2b20 cmp r3, #32 80052e8: d105 bne.n 80052f6 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 80052ea: 687b ldr r3, [r7, #4] 80052ec: 2290 movs r2, #144 @ 0x90 80052ee: 2110 movs r1, #16 80052f0: 5099 str r1, [r3, r2] return HAL_TIMEOUT; 80052f2: 2303 movs r3, #3 80052f4: e004 b.n 8005300 } } } UART_EndRxTransfer(huart); 80052f6: 687b ldr r3, [r7, #4] 80052f8: 0018 movs r0, r3 80052fa: f000 fc4b bl 8005b94 } return HAL_OK; 80052fe: 2300 movs r3, #0 } 8005300: 0018 movs r0, r3 8005302: 46bd mov sp, r7 8005304: b00c add sp, #48 @ 0x30 8005306: bd80 pop {r7, pc} 08005308 : * @brief Tx Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8005308: b580 push {r7, lr} 800530a: b082 sub sp, #8 800530c: af00 add r7, sp, #0 800530e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback can be implemented in the user file. */ } 8005310: 46c0 nop @ (mov r8, r8) 8005312: 46bd mov sp, r7 8005314: b002 add sp, #8 8005316: bd80 pop {r7, pc} 08005318 : * @brief Tx Half Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8005318: b580 push {r7, lr} 800531a: b082 sub sp, #8 800531c: af00 add r7, sp, #0 800531e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback can be implemented in the user file. */ } 8005320: 46c0 nop @ (mov r8, r8) 8005322: 46bd mov sp, r7 8005324: b002 add sp, #8 8005326: bd80 pop {r7, pc} 08005328 : * @brief Rx Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8005328: b580 push {r7, lr} 800532a: b082 sub sp, #8 800532c: af00 add r7, sp, #0 800532e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback can be implemented in the user file. */ } 8005330: 46c0 nop @ (mov r8, r8) 8005332: 46bd mov sp, r7 8005334: b002 add sp, #8 8005336: bd80 pop {r7, pc} 08005338 : * @brief Rx Half Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8005338: b580 push {r7, lr} 800533a: b082 sub sp, #8 800533c: af00 add r7, sp, #0 800533e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback can be implemented in the user file. */ } 8005340: 46c0 nop @ (mov r8, r8) 8005342: 46bd mov sp, r7 8005344: b002 add sp, #8 8005346: bd80 pop {r7, pc} 08005348 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8005348: b580 push {r7, lr} 800534a: b082 sub sp, #8 800534c: af00 add r7, sp, #0 800534e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8005350: 46c0 nop @ (mov r8, r8) 8005352: 46bd mov sp, r7 8005354: b002 add sp, #8 8005356: bd80 pop {r7, pc} 08005358 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8005358: b580 push {r7, lr} 800535a: b088 sub sp, #32 800535c: af00 add r7, sp, #0 800535e: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8005360: 231a movs r3, #26 8005362: 18fb adds r3, r7, r3 8005364: 2200 movs r2, #0 8005366: 701a strb r2, [r3, #0] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8005368: 687b ldr r3, [r7, #4] 800536a: 689a ldr r2, [r3, #8] 800536c: 687b ldr r3, [r7, #4] 800536e: 691b ldr r3, [r3, #16] 8005370: 431a orrs r2, r3 8005372: 687b ldr r3, [r7, #4] 8005374: 695b ldr r3, [r3, #20] 8005376: 431a orrs r2, r3 8005378: 687b ldr r3, [r7, #4] 800537a: 69db ldr r3, [r3, #28] 800537c: 4313 orrs r3, r2 800537e: 61fb str r3, [r7, #28] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8005380: 687b ldr r3, [r7, #4] 8005382: 681b ldr r3, [r3, #0] 8005384: 681b ldr r3, [r3, #0] 8005386: 4aa1 ldr r2, [pc, #644] @ (800560c ) 8005388: 4013 ands r3, r2 800538a: 0019 movs r1, r3 800538c: 687b ldr r3, [r7, #4] 800538e: 681b ldr r3, [r3, #0] 8005390: 69fa ldr r2, [r7, #28] 8005392: 430a orrs r2, r1 8005394: 601a str r2, [r3, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8005396: 687b ldr r3, [r7, #4] 8005398: 681b ldr r3, [r3, #0] 800539a: 685b ldr r3, [r3, #4] 800539c: 4a9c ldr r2, [pc, #624] @ (8005610 ) 800539e: 4013 ands r3, r2 80053a0: 0019 movs r1, r3 80053a2: 687b ldr r3, [r7, #4] 80053a4: 68da ldr r2, [r3, #12] 80053a6: 687b ldr r3, [r7, #4] 80053a8: 681b ldr r3, [r3, #0] 80053aa: 430a orrs r2, r1 80053ac: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 80053ae: 687b ldr r3, [r7, #4] 80053b0: 699b ldr r3, [r3, #24] 80053b2: 61fb str r3, [r7, #28] if (!(UART_INSTANCE_LOWPOWER(huart))) { tmpreg |= huart->Init.OneBitSampling; 80053b4: 687b ldr r3, [r7, #4] 80053b6: 6a1b ldr r3, [r3, #32] 80053b8: 69fa ldr r2, [r7, #28] 80053ba: 4313 orrs r3, r2 80053bc: 61fb str r3, [r7, #28] } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 80053be: 687b ldr r3, [r7, #4] 80053c0: 681b ldr r3, [r3, #0] 80053c2: 689b ldr r3, [r3, #8] 80053c4: 4a93 ldr r2, [pc, #588] @ (8005614 ) 80053c6: 4013 ands r3, r2 80053c8: 0019 movs r1, r3 80053ca: 687b ldr r3, [r7, #4] 80053cc: 681b ldr r3, [r3, #0] 80053ce: 69fa ldr r2, [r7, #28] 80053d0: 430a orrs r2, r1 80053d2: 609a str r2, [r3, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 80053d4: 687b ldr r3, [r7, #4] 80053d6: 681b ldr r3, [r3, #0] 80053d8: 6adb ldr r3, [r3, #44] @ 0x2c 80053da: 220f movs r2, #15 80053dc: 4393 bics r3, r2 80053de: 0019 movs r1, r3 80053e0: 687b ldr r3, [r7, #4] 80053e2: 6a5a ldr r2, [r3, #36] @ 0x24 80053e4: 687b ldr r3, [r7, #4] 80053e6: 681b ldr r3, [r3, #0] 80053e8: 430a orrs r2, r1 80053ea: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 80053ec: 687b ldr r3, [r7, #4] 80053ee: 681b ldr r3, [r3, #0] 80053f0: 4a89 ldr r2, [pc, #548] @ (8005618 ) 80053f2: 4293 cmp r3, r2 80053f4: d127 bne.n 8005446 80053f6: 4b89 ldr r3, [pc, #548] @ (800561c ) 80053f8: 6d5b ldr r3, [r3, #84] @ 0x54 80053fa: 2203 movs r2, #3 80053fc: 4013 ands r3, r2 80053fe: 2b03 cmp r3, #3 8005400: d017 beq.n 8005432 8005402: d81b bhi.n 800543c 8005404: 2b02 cmp r3, #2 8005406: d00a beq.n 800541e 8005408: d818 bhi.n 800543c 800540a: 2b00 cmp r3, #0 800540c: d002 beq.n 8005414 800540e: 2b01 cmp r3, #1 8005410: d00a beq.n 8005428 8005412: e013 b.n 800543c 8005414: 231b movs r3, #27 8005416: 18fb adds r3, r7, r3 8005418: 2200 movs r2, #0 800541a: 701a strb r2, [r3, #0] 800541c: e021 b.n 8005462 800541e: 231b movs r3, #27 8005420: 18fb adds r3, r7, r3 8005422: 2202 movs r2, #2 8005424: 701a strb r2, [r3, #0] 8005426: e01c b.n 8005462 8005428: 231b movs r3, #27 800542a: 18fb adds r3, r7, r3 800542c: 2204 movs r2, #4 800542e: 701a strb r2, [r3, #0] 8005430: e017 b.n 8005462 8005432: 231b movs r3, #27 8005434: 18fb adds r3, r7, r3 8005436: 2208 movs r2, #8 8005438: 701a strb r2, [r3, #0] 800543a: e012 b.n 8005462 800543c: 231b movs r3, #27 800543e: 18fb adds r3, r7, r3 8005440: 2210 movs r2, #16 8005442: 701a strb r2, [r3, #0] 8005444: e00d b.n 8005462 8005446: 687b ldr r3, [r7, #4] 8005448: 681b ldr r3, [r3, #0] 800544a: 4a75 ldr r2, [pc, #468] @ (8005620 ) 800544c: 4293 cmp r3, r2 800544e: d104 bne.n 800545a 8005450: 231b movs r3, #27 8005452: 18fb adds r3, r7, r3 8005454: 2200 movs r2, #0 8005456: 701a strb r2, [r3, #0] 8005458: e003 b.n 8005462 800545a: 231b movs r3, #27 800545c: 18fb adds r3, r7, r3 800545e: 2210 movs r2, #16 8005460: 701a strb r2, [r3, #0] } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8005462: 687b ldr r3, [r7, #4] 8005464: 69da ldr r2, [r3, #28] 8005466: 2380 movs r3, #128 @ 0x80 8005468: 021b lsls r3, r3, #8 800546a: 429a cmp r2, r3 800546c: d000 beq.n 8005470 800546e: e065 b.n 800553c { switch (clocksource) 8005470: 231b movs r3, #27 8005472: 18fb adds r3, r7, r3 8005474: 781b ldrb r3, [r3, #0] 8005476: 2b08 cmp r3, #8 8005478: d015 beq.n 80054a6 800547a: dc18 bgt.n 80054ae 800547c: 2b04 cmp r3, #4 800547e: d00d beq.n 800549c 8005480: dc15 bgt.n 80054ae 8005482: 2b00 cmp r3, #0 8005484: d002 beq.n 800548c 8005486: 2b02 cmp r3, #2 8005488: d005 beq.n 8005496 800548a: e010 b.n 80054ae { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 800548c: f7fe ff18 bl 80042c0 8005490: 0003 movs r3, r0 8005492: 617b str r3, [r7, #20] break; 8005494: e012 b.n 80054bc case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8005496: 4b63 ldr r3, [pc, #396] @ (8005624 ) 8005498: 617b str r3, [r7, #20] break; 800549a: e00f b.n 80054bc case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 800549c: f7fe fe84 bl 80041a8 80054a0: 0003 movs r3, r0 80054a2: 617b str r3, [r7, #20] break; 80054a4: e00a b.n 80054bc case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80054a6: 2380 movs r3, #128 @ 0x80 80054a8: 021b lsls r3, r3, #8 80054aa: 617b str r3, [r7, #20] break; 80054ac: e006 b.n 80054bc default: pclk = 0U; 80054ae: 2300 movs r3, #0 80054b0: 617b str r3, [r7, #20] ret = HAL_ERROR; 80054b2: 231a movs r3, #26 80054b4: 18fb adds r3, r7, r3 80054b6: 2201 movs r2, #1 80054b8: 701a strb r2, [r3, #0] break; 80054ba: 46c0 nop @ (mov r8, r8) } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 80054bc: 697b ldr r3, [r7, #20] 80054be: 2b00 cmp r3, #0 80054c0: d100 bne.n 80054c4 80054c2: e08d b.n 80055e0 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80054c4: 687b ldr r3, [r7, #4] 80054c6: 6a5a ldr r2, [r3, #36] @ 0x24 80054c8: 4b57 ldr r3, [pc, #348] @ (8005628 ) 80054ca: 0052 lsls r2, r2, #1 80054cc: 5ad3 ldrh r3, [r2, r3] 80054ce: 0019 movs r1, r3 80054d0: 6978 ldr r0, [r7, #20] 80054d2: f7fa fe15 bl 8000100 <__udivsi3> 80054d6: 0003 movs r3, r0 80054d8: 005a lsls r2, r3, #1 80054da: 687b ldr r3, [r7, #4] 80054dc: 685b ldr r3, [r3, #4] 80054de: 085b lsrs r3, r3, #1 80054e0: 18d2 adds r2, r2, r3 80054e2: 687b ldr r3, [r7, #4] 80054e4: 685b ldr r3, [r3, #4] 80054e6: 0019 movs r1, r3 80054e8: 0010 movs r0, r2 80054ea: f7fa fe09 bl 8000100 <__udivsi3> 80054ee: 0003 movs r3, r0 80054f0: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 80054f2: 693b ldr r3, [r7, #16] 80054f4: 2b0f cmp r3, #15 80054f6: d91c bls.n 8005532 80054f8: 693a ldr r2, [r7, #16] 80054fa: 2380 movs r3, #128 @ 0x80 80054fc: 025b lsls r3, r3, #9 80054fe: 429a cmp r2, r3 8005500: d217 bcs.n 8005532 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8005502: 693b ldr r3, [r7, #16] 8005504: b29a uxth r2, r3 8005506: 200e movs r0, #14 8005508: 183b adds r3, r7, r0 800550a: 210f movs r1, #15 800550c: 438a bics r2, r1 800550e: 801a strh r2, [r3, #0] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8005510: 693b ldr r3, [r7, #16] 8005512: 085b lsrs r3, r3, #1 8005514: b29b uxth r3, r3 8005516: 2207 movs r2, #7 8005518: 4013 ands r3, r2 800551a: b299 uxth r1, r3 800551c: 183b adds r3, r7, r0 800551e: 183a adds r2, r7, r0 8005520: 8812 ldrh r2, [r2, #0] 8005522: 430a orrs r2, r1 8005524: 801a strh r2, [r3, #0] huart->Instance->BRR = brrtemp; 8005526: 687b ldr r3, [r7, #4] 8005528: 681b ldr r3, [r3, #0] 800552a: 183a adds r2, r7, r0 800552c: 8812 ldrh r2, [r2, #0] 800552e: 60da str r2, [r3, #12] 8005530: e056 b.n 80055e0 } else { ret = HAL_ERROR; 8005532: 231a movs r3, #26 8005534: 18fb adds r3, r7, r3 8005536: 2201 movs r2, #1 8005538: 701a strb r2, [r3, #0] 800553a: e051 b.n 80055e0 } } } else { switch (clocksource) 800553c: 231b movs r3, #27 800553e: 18fb adds r3, r7, r3 8005540: 781b ldrb r3, [r3, #0] 8005542: 2b08 cmp r3, #8 8005544: d015 beq.n 8005572 8005546: dc18 bgt.n 800557a 8005548: 2b04 cmp r3, #4 800554a: d00d beq.n 8005568 800554c: dc15 bgt.n 800557a 800554e: 2b00 cmp r3, #0 8005550: d002 beq.n 8005558 8005552: 2b02 cmp r3, #2 8005554: d005 beq.n 8005562 8005556: e010 b.n 800557a { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8005558: f7fe feb2 bl 80042c0 800555c: 0003 movs r3, r0 800555e: 617b str r3, [r7, #20] break; 8005560: e012 b.n 8005588 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8005562: 4b30 ldr r3, [pc, #192] @ (8005624 ) 8005564: 617b str r3, [r7, #20] break; 8005566: e00f b.n 8005588 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8005568: f7fe fe1e bl 80041a8 800556c: 0003 movs r3, r0 800556e: 617b str r3, [r7, #20] break; 8005570: e00a b.n 8005588 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8005572: 2380 movs r3, #128 @ 0x80 8005574: 021b lsls r3, r3, #8 8005576: 617b str r3, [r7, #20] break; 8005578: e006 b.n 8005588 default: pclk = 0U; 800557a: 2300 movs r3, #0 800557c: 617b str r3, [r7, #20] ret = HAL_ERROR; 800557e: 231a movs r3, #26 8005580: 18fb adds r3, r7, r3 8005582: 2201 movs r2, #1 8005584: 701a strb r2, [r3, #0] break; 8005586: 46c0 nop @ (mov r8, r8) } if (pclk != 0U) 8005588: 697b ldr r3, [r7, #20] 800558a: 2b00 cmp r3, #0 800558c: d028 beq.n 80055e0 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800558e: 687b ldr r3, [r7, #4] 8005590: 6a5a ldr r2, [r3, #36] @ 0x24 8005592: 4b25 ldr r3, [pc, #148] @ (8005628 ) 8005594: 0052 lsls r2, r2, #1 8005596: 5ad3 ldrh r3, [r2, r3] 8005598: 0019 movs r1, r3 800559a: 6978 ldr r0, [r7, #20] 800559c: f7fa fdb0 bl 8000100 <__udivsi3> 80055a0: 0003 movs r3, r0 80055a2: 001a movs r2, r3 80055a4: 687b ldr r3, [r7, #4] 80055a6: 685b ldr r3, [r3, #4] 80055a8: 085b lsrs r3, r3, #1 80055aa: 18d2 adds r2, r2, r3 80055ac: 687b ldr r3, [r7, #4] 80055ae: 685b ldr r3, [r3, #4] 80055b0: 0019 movs r1, r3 80055b2: 0010 movs r0, r2 80055b4: f7fa fda4 bl 8000100 <__udivsi3> 80055b8: 0003 movs r3, r0 80055ba: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 80055bc: 693b ldr r3, [r7, #16] 80055be: 2b0f cmp r3, #15 80055c0: d90a bls.n 80055d8 80055c2: 693a ldr r2, [r7, #16] 80055c4: 2380 movs r3, #128 @ 0x80 80055c6: 025b lsls r3, r3, #9 80055c8: 429a cmp r2, r3 80055ca: d205 bcs.n 80055d8 { huart->Instance->BRR = (uint16_t)usartdiv; 80055cc: 693b ldr r3, [r7, #16] 80055ce: b29a uxth r2, r3 80055d0: 687b ldr r3, [r7, #4] 80055d2: 681b ldr r3, [r3, #0] 80055d4: 60da str r2, [r3, #12] 80055d6: e003 b.n 80055e0 } else { ret = HAL_ERROR; 80055d8: 231a movs r3, #26 80055da: 18fb adds r3, r7, r3 80055dc: 2201 movs r2, #1 80055de: 701a strb r2, [r3, #0] } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 80055e0: 687b ldr r3, [r7, #4] 80055e2: 226a movs r2, #106 @ 0x6a 80055e4: 2101 movs r1, #1 80055e6: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1; 80055e8: 687b ldr r3, [r7, #4] 80055ea: 2268 movs r2, #104 @ 0x68 80055ec: 2101 movs r1, #1 80055ee: 5299 strh r1, [r3, r2] /* Clear ISR function pointers */ huart->RxISR = NULL; 80055f0: 687b ldr r3, [r7, #4] 80055f2: 2200 movs r2, #0 80055f4: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 80055f6: 687b ldr r3, [r7, #4] 80055f8: 2200 movs r2, #0 80055fa: 679a str r2, [r3, #120] @ 0x78 return ret; 80055fc: 231a movs r3, #26 80055fe: 18fb adds r3, r7, r3 8005600: 781b ldrb r3, [r3, #0] } 8005602: 0018 movs r0, r3 8005604: 46bd mov sp, r7 8005606: b008 add sp, #32 8005608: bd80 pop {r7, pc} 800560a: 46c0 nop @ (mov r8, r8) 800560c: cfff69f3 .word 0xcfff69f3 8005610: ffffcfff .word 0xffffcfff 8005614: 11fff4ff .word 0x11fff4ff 8005618: 40013800 .word 0x40013800 800561c: 40021000 .word 0x40021000 8005620: 40004400 .word 0x40004400 8005624: 00f42400 .word 0x00f42400 8005628: 08006128 .word 0x08006128 0800562c : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 800562c: b580 push {r7, lr} 800562e: b082 sub sp, #8 8005630: af00 add r7, sp, #0 8005632: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8005634: 687b ldr r3, [r7, #4] 8005636: 6a9b ldr r3, [r3, #40] @ 0x28 8005638: 2208 movs r2, #8 800563a: 4013 ands r3, r2 800563c: d00b beq.n 8005656 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 800563e: 687b ldr r3, [r7, #4] 8005640: 681b ldr r3, [r3, #0] 8005642: 685b ldr r3, [r3, #4] 8005644: 4a4a ldr r2, [pc, #296] @ (8005770 ) 8005646: 4013 ands r3, r2 8005648: 0019 movs r1, r3 800564a: 687b ldr r3, [r7, #4] 800564c: 6b9a ldr r2, [r3, #56] @ 0x38 800564e: 687b ldr r3, [r7, #4] 8005650: 681b ldr r3, [r3, #0] 8005652: 430a orrs r2, r1 8005654: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8005656: 687b ldr r3, [r7, #4] 8005658: 6a9b ldr r3, [r3, #40] @ 0x28 800565a: 2201 movs r2, #1 800565c: 4013 ands r3, r2 800565e: d00b beq.n 8005678 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8005660: 687b ldr r3, [r7, #4] 8005662: 681b ldr r3, [r3, #0] 8005664: 685b ldr r3, [r3, #4] 8005666: 4a43 ldr r2, [pc, #268] @ (8005774 ) 8005668: 4013 ands r3, r2 800566a: 0019 movs r1, r3 800566c: 687b ldr r3, [r7, #4] 800566e: 6ada ldr r2, [r3, #44] @ 0x2c 8005670: 687b ldr r3, [r7, #4] 8005672: 681b ldr r3, [r3, #0] 8005674: 430a orrs r2, r1 8005676: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8005678: 687b ldr r3, [r7, #4] 800567a: 6a9b ldr r3, [r3, #40] @ 0x28 800567c: 2202 movs r2, #2 800567e: 4013 ands r3, r2 8005680: d00b beq.n 800569a { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8005682: 687b ldr r3, [r7, #4] 8005684: 681b ldr r3, [r3, #0] 8005686: 685b ldr r3, [r3, #4] 8005688: 4a3b ldr r2, [pc, #236] @ (8005778 ) 800568a: 4013 ands r3, r2 800568c: 0019 movs r1, r3 800568e: 687b ldr r3, [r7, #4] 8005690: 6b1a ldr r2, [r3, #48] @ 0x30 8005692: 687b ldr r3, [r7, #4] 8005694: 681b ldr r3, [r3, #0] 8005696: 430a orrs r2, r1 8005698: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 800569a: 687b ldr r3, [r7, #4] 800569c: 6a9b ldr r3, [r3, #40] @ 0x28 800569e: 2204 movs r2, #4 80056a0: 4013 ands r3, r2 80056a2: d00b beq.n 80056bc { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 80056a4: 687b ldr r3, [r7, #4] 80056a6: 681b ldr r3, [r3, #0] 80056a8: 685b ldr r3, [r3, #4] 80056aa: 4a34 ldr r2, [pc, #208] @ (800577c ) 80056ac: 4013 ands r3, r2 80056ae: 0019 movs r1, r3 80056b0: 687b ldr r3, [r7, #4] 80056b2: 6b5a ldr r2, [r3, #52] @ 0x34 80056b4: 687b ldr r3, [r7, #4] 80056b6: 681b ldr r3, [r3, #0] 80056b8: 430a orrs r2, r1 80056ba: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 80056bc: 687b ldr r3, [r7, #4] 80056be: 6a9b ldr r3, [r3, #40] @ 0x28 80056c0: 2210 movs r2, #16 80056c2: 4013 ands r3, r2 80056c4: d00b beq.n 80056de { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 80056c6: 687b ldr r3, [r7, #4] 80056c8: 681b ldr r3, [r3, #0] 80056ca: 689b ldr r3, [r3, #8] 80056cc: 4a2c ldr r2, [pc, #176] @ (8005780 ) 80056ce: 4013 ands r3, r2 80056d0: 0019 movs r1, r3 80056d2: 687b ldr r3, [r7, #4] 80056d4: 6bda ldr r2, [r3, #60] @ 0x3c 80056d6: 687b ldr r3, [r7, #4] 80056d8: 681b ldr r3, [r3, #0] 80056da: 430a orrs r2, r1 80056dc: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 80056de: 687b ldr r3, [r7, #4] 80056e0: 6a9b ldr r3, [r3, #40] @ 0x28 80056e2: 2220 movs r2, #32 80056e4: 4013 ands r3, r2 80056e6: d00b beq.n 8005700 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 80056e8: 687b ldr r3, [r7, #4] 80056ea: 681b ldr r3, [r3, #0] 80056ec: 689b ldr r3, [r3, #8] 80056ee: 4a25 ldr r2, [pc, #148] @ (8005784 ) 80056f0: 4013 ands r3, r2 80056f2: 0019 movs r1, r3 80056f4: 687b ldr r3, [r7, #4] 80056f6: 6c1a ldr r2, [r3, #64] @ 0x40 80056f8: 687b ldr r3, [r7, #4] 80056fa: 681b ldr r3, [r3, #0] 80056fc: 430a orrs r2, r1 80056fe: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8005700: 687b ldr r3, [r7, #4] 8005702: 6a9b ldr r3, [r3, #40] @ 0x28 8005704: 2240 movs r2, #64 @ 0x40 8005706: 4013 ands r3, r2 8005708: d01d beq.n 8005746 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 800570a: 687b ldr r3, [r7, #4] 800570c: 681b ldr r3, [r3, #0] 800570e: 685b ldr r3, [r3, #4] 8005710: 4a1d ldr r2, [pc, #116] @ (8005788 ) 8005712: 4013 ands r3, r2 8005714: 0019 movs r1, r3 8005716: 687b ldr r3, [r7, #4] 8005718: 6c5a ldr r2, [r3, #68] @ 0x44 800571a: 687b ldr r3, [r7, #4] 800571c: 681b ldr r3, [r3, #0] 800571e: 430a orrs r2, r1 8005720: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8005722: 687b ldr r3, [r7, #4] 8005724: 6c5a ldr r2, [r3, #68] @ 0x44 8005726: 2380 movs r3, #128 @ 0x80 8005728: 035b lsls r3, r3, #13 800572a: 429a cmp r2, r3 800572c: d10b bne.n 8005746 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 800572e: 687b ldr r3, [r7, #4] 8005730: 681b ldr r3, [r3, #0] 8005732: 685b ldr r3, [r3, #4] 8005734: 4a15 ldr r2, [pc, #84] @ (800578c ) 8005736: 4013 ands r3, r2 8005738: 0019 movs r1, r3 800573a: 687b ldr r3, [r7, #4] 800573c: 6c9a ldr r2, [r3, #72] @ 0x48 800573e: 687b ldr r3, [r7, #4] 8005740: 681b ldr r3, [r3, #0] 8005742: 430a orrs r2, r1 8005744: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8005746: 687b ldr r3, [r7, #4] 8005748: 6a9b ldr r3, [r3, #40] @ 0x28 800574a: 2280 movs r2, #128 @ 0x80 800574c: 4013 ands r3, r2 800574e: d00b beq.n 8005768 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8005750: 687b ldr r3, [r7, #4] 8005752: 681b ldr r3, [r3, #0] 8005754: 685b ldr r3, [r3, #4] 8005756: 4a0e ldr r2, [pc, #56] @ (8005790 ) 8005758: 4013 ands r3, r2 800575a: 0019 movs r1, r3 800575c: 687b ldr r3, [r7, #4] 800575e: 6cda ldr r2, [r3, #76] @ 0x4c 8005760: 687b ldr r3, [r7, #4] 8005762: 681b ldr r3, [r3, #0] 8005764: 430a orrs r2, r1 8005766: 605a str r2, [r3, #4] } } 8005768: 46c0 nop @ (mov r8, r8) 800576a: 46bd mov sp, r7 800576c: b002 add sp, #8 800576e: bd80 pop {r7, pc} 8005770: ffff7fff .word 0xffff7fff 8005774: fffdffff .word 0xfffdffff 8005778: fffeffff .word 0xfffeffff 800577c: fffbffff .word 0xfffbffff 8005780: ffffefff .word 0xffffefff 8005784: ffffdfff .word 0xffffdfff 8005788: ffefffff .word 0xffefffff 800578c: ff9fffff .word 0xff9fffff 8005790: fff7ffff .word 0xfff7ffff 08005794 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8005794: b580 push {r7, lr} 8005796: b092 sub sp, #72 @ 0x48 8005798: af02 add r7, sp, #8 800579a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800579c: 687b ldr r3, [r7, #4] 800579e: 2290 movs r2, #144 @ 0x90 80057a0: 2100 movs r1, #0 80057a2: 5099 str r1, [r3, r2] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 80057a4: f7fc f860 bl 8001868 80057a8: 0003 movs r3, r0 80057aa: 63fb str r3, [r7, #60] @ 0x3c /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 80057ac: 687b ldr r3, [r7, #4] 80057ae: 681b ldr r3, [r3, #0] 80057b0: 681b ldr r3, [r3, #0] 80057b2: 2208 movs r2, #8 80057b4: 4013 ands r3, r2 80057b6: 2b08 cmp r3, #8 80057b8: d12d bne.n 8005816 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 80057ba: 6bfb ldr r3, [r7, #60] @ 0x3c 80057bc: 2280 movs r2, #128 @ 0x80 80057be: 0391 lsls r1, r2, #14 80057c0: 6878 ldr r0, [r7, #4] 80057c2: 4a47 ldr r2, [pc, #284] @ (80058e0 ) 80057c4: 9200 str r2, [sp, #0] 80057c6: 2200 movs r2, #0 80057c8: f000 f88e bl 80058e8 80057cc: 1e03 subs r3, r0, #0 80057ce: d022 beq.n 8005816 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80057d0: f3ef 8310 mrs r3, PRIMASK 80057d4: 627b str r3, [r7, #36] @ 0x24 return(result); 80057d6: 6a7b ldr r3, [r7, #36] @ 0x24 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 80057d8: 63bb str r3, [r7, #56] @ 0x38 80057da: 2301 movs r3, #1 80057dc: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80057de: 6abb ldr r3, [r7, #40] @ 0x28 80057e0: f383 8810 msr PRIMASK, r3 } 80057e4: 46c0 nop @ (mov r8, r8) 80057e6: 687b ldr r3, [r7, #4] 80057e8: 681b ldr r3, [r3, #0] 80057ea: 681a ldr r2, [r3, #0] 80057ec: 687b ldr r3, [r7, #4] 80057ee: 681b ldr r3, [r3, #0] 80057f0: 2180 movs r1, #128 @ 0x80 80057f2: 438a bics r2, r1 80057f4: 601a str r2, [r3, #0] 80057f6: 6bbb ldr r3, [r7, #56] @ 0x38 80057f8: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80057fa: 6afb ldr r3, [r7, #44] @ 0x2c 80057fc: f383 8810 msr PRIMASK, r3 } 8005800: 46c0 nop @ (mov r8, r8) huart->gState = HAL_UART_STATE_READY; 8005802: 687b ldr r3, [r7, #4] 8005804: 2288 movs r2, #136 @ 0x88 8005806: 2120 movs r1, #32 8005808: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); 800580a: 687b ldr r3, [r7, #4] 800580c: 2284 movs r2, #132 @ 0x84 800580e: 2100 movs r1, #0 8005810: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; 8005812: 2303 movs r3, #3 8005814: e060 b.n 80058d8 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8005816: 687b ldr r3, [r7, #4] 8005818: 681b ldr r3, [r3, #0] 800581a: 681b ldr r3, [r3, #0] 800581c: 2204 movs r2, #4 800581e: 4013 ands r3, r2 8005820: 2b04 cmp r3, #4 8005822: d146 bne.n 80058b2 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8005824: 6bfb ldr r3, [r7, #60] @ 0x3c 8005826: 2280 movs r2, #128 @ 0x80 8005828: 03d1 lsls r1, r2, #15 800582a: 6878 ldr r0, [r7, #4] 800582c: 4a2c ldr r2, [pc, #176] @ (80058e0 ) 800582e: 9200 str r2, [sp, #0] 8005830: 2200 movs r2, #0 8005832: f000 f859 bl 80058e8 8005836: 1e03 subs r3, r0, #0 8005838: d03b beq.n 80058b2 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800583a: f3ef 8310 mrs r3, PRIMASK 800583e: 60fb str r3, [r7, #12] return(result); 8005840: 68fb ldr r3, [r7, #12] { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8005842: 637b str r3, [r7, #52] @ 0x34 8005844: 2301 movs r3, #1 8005846: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005848: 693b ldr r3, [r7, #16] 800584a: f383 8810 msr PRIMASK, r3 } 800584e: 46c0 nop @ (mov r8, r8) 8005850: 687b ldr r3, [r7, #4] 8005852: 681b ldr r3, [r3, #0] 8005854: 681a ldr r2, [r3, #0] 8005856: 687b ldr r3, [r7, #4] 8005858: 681b ldr r3, [r3, #0] 800585a: 4922 ldr r1, [pc, #136] @ (80058e4 ) 800585c: 400a ands r2, r1 800585e: 601a str r2, [r3, #0] 8005860: 6b7b ldr r3, [r7, #52] @ 0x34 8005862: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005864: 697b ldr r3, [r7, #20] 8005866: f383 8810 msr PRIMASK, r3 } 800586a: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800586c: f3ef 8310 mrs r3, PRIMASK 8005870: 61bb str r3, [r7, #24] return(result); 8005872: 69bb ldr r3, [r7, #24] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005874: 633b str r3, [r7, #48] @ 0x30 8005876: 2301 movs r3, #1 8005878: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800587a: 69fb ldr r3, [r7, #28] 800587c: f383 8810 msr PRIMASK, r3 } 8005880: 46c0 nop @ (mov r8, r8) 8005882: 687b ldr r3, [r7, #4] 8005884: 681b ldr r3, [r3, #0] 8005886: 689a ldr r2, [r3, #8] 8005888: 687b ldr r3, [r7, #4] 800588a: 681b ldr r3, [r3, #0] 800588c: 2101 movs r1, #1 800588e: 438a bics r2, r1 8005890: 609a str r2, [r3, #8] 8005892: 6b3b ldr r3, [r7, #48] @ 0x30 8005894: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005896: 6a3b ldr r3, [r7, #32] 8005898: f383 8810 msr PRIMASK, r3 } 800589c: 46c0 nop @ (mov r8, r8) huart->RxState = HAL_UART_STATE_READY; 800589e: 687b ldr r3, [r7, #4] 80058a0: 228c movs r2, #140 @ 0x8c 80058a2: 2120 movs r1, #32 80058a4: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); 80058a6: 687b ldr r3, [r7, #4] 80058a8: 2284 movs r2, #132 @ 0x84 80058aa: 2100 movs r1, #0 80058ac: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; 80058ae: 2303 movs r3, #3 80058b0: e012 b.n 80058d8 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 80058b2: 687b ldr r3, [r7, #4] 80058b4: 2288 movs r2, #136 @ 0x88 80058b6: 2120 movs r1, #32 80058b8: 5099 str r1, [r3, r2] huart->RxState = HAL_UART_STATE_READY; 80058ba: 687b ldr r3, [r7, #4] 80058bc: 228c movs r2, #140 @ 0x8c 80058be: 2120 movs r1, #32 80058c0: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80058c2: 687b ldr r3, [r7, #4] 80058c4: 2200 movs r2, #0 80058c6: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 80058c8: 687b ldr r3, [r7, #4] 80058ca: 2200 movs r2, #0 80058cc: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 80058ce: 687b ldr r3, [r7, #4] 80058d0: 2284 movs r2, #132 @ 0x84 80058d2: 2100 movs r1, #0 80058d4: 5499 strb r1, [r3, r2] return HAL_OK; 80058d6: 2300 movs r3, #0 } 80058d8: 0018 movs r0, r3 80058da: 46bd mov sp, r7 80058dc: b010 add sp, #64 @ 0x40 80058de: bd80 pop {r7, pc} 80058e0: 01ffffff .word 0x01ffffff 80058e4: fffffedf .word 0xfffffedf 080058e8 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 80058e8: b580 push {r7, lr} 80058ea: b084 sub sp, #16 80058ec: af00 add r7, sp, #0 80058ee: 60f8 str r0, [r7, #12] 80058f0: 60b9 str r1, [r7, #8] 80058f2: 603b str r3, [r7, #0] 80058f4: 1dfb adds r3, r7, #7 80058f6: 701a strb r2, [r3, #0] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80058f8: e051 b.n 800599e { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80058fa: 69bb ldr r3, [r7, #24] 80058fc: 3301 adds r3, #1 80058fe: d04e beq.n 800599e { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8005900: f7fb ffb2 bl 8001868 8005904: 0002 movs r2, r0 8005906: 683b ldr r3, [r7, #0] 8005908: 1ad3 subs r3, r2, r3 800590a: 69ba ldr r2, [r7, #24] 800590c: 429a cmp r2, r3 800590e: d302 bcc.n 8005916 8005910: 69bb ldr r3, [r7, #24] 8005912: 2b00 cmp r3, #0 8005914: d101 bne.n 800591a { return HAL_TIMEOUT; 8005916: 2303 movs r3, #3 8005918: e051 b.n 80059be } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 800591a: 68fb ldr r3, [r7, #12] 800591c: 681b ldr r3, [r3, #0] 800591e: 681b ldr r3, [r3, #0] 8005920: 2204 movs r2, #4 8005922: 4013 ands r3, r2 8005924: d03b beq.n 800599e 8005926: 68bb ldr r3, [r7, #8] 8005928: 2b80 cmp r3, #128 @ 0x80 800592a: d038 beq.n 800599e 800592c: 68bb ldr r3, [r7, #8] 800592e: 2b40 cmp r3, #64 @ 0x40 8005930: d035 beq.n 800599e { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8005932: 68fb ldr r3, [r7, #12] 8005934: 681b ldr r3, [r3, #0] 8005936: 69db ldr r3, [r3, #28] 8005938: 2208 movs r2, #8 800593a: 4013 ands r3, r2 800593c: 2b08 cmp r3, #8 800593e: d111 bne.n 8005964 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8005940: 68fb ldr r3, [r7, #12] 8005942: 681b ldr r3, [r3, #0] 8005944: 2208 movs r2, #8 8005946: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8005948: 68fb ldr r3, [r7, #12] 800594a: 0018 movs r0, r3 800594c: f000 f922 bl 8005b94 huart->ErrorCode = HAL_UART_ERROR_ORE; 8005950: 68fb ldr r3, [r7, #12] 8005952: 2290 movs r2, #144 @ 0x90 8005954: 2108 movs r1, #8 8005956: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 8005958: 68fb ldr r3, [r7, #12] 800595a: 2284 movs r2, #132 @ 0x84 800595c: 2100 movs r1, #0 800595e: 5499 strb r1, [r3, r2] return HAL_ERROR; 8005960: 2301 movs r3, #1 8005962: e02c b.n 80059be } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8005964: 68fb ldr r3, [r7, #12] 8005966: 681b ldr r3, [r3, #0] 8005968: 69da ldr r2, [r3, #28] 800596a: 2380 movs r3, #128 @ 0x80 800596c: 011b lsls r3, r3, #4 800596e: 401a ands r2, r3 8005970: 2380 movs r3, #128 @ 0x80 8005972: 011b lsls r3, r3, #4 8005974: 429a cmp r2, r3 8005976: d112 bne.n 800599e { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8005978: 68fb ldr r3, [r7, #12] 800597a: 681b ldr r3, [r3, #0] 800597c: 2280 movs r2, #128 @ 0x80 800597e: 0112 lsls r2, r2, #4 8005980: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8005982: 68fb ldr r3, [r7, #12] 8005984: 0018 movs r0, r3 8005986: f000 f905 bl 8005b94 huart->ErrorCode = HAL_UART_ERROR_RTO; 800598a: 68fb ldr r3, [r7, #12] 800598c: 2290 movs r2, #144 @ 0x90 800598e: 2120 movs r1, #32 8005990: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 8005992: 68fb ldr r3, [r7, #12] 8005994: 2284 movs r2, #132 @ 0x84 8005996: 2100 movs r1, #0 8005998: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; 800599a: 2303 movs r3, #3 800599c: e00f b.n 80059be while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800599e: 68fb ldr r3, [r7, #12] 80059a0: 681b ldr r3, [r3, #0] 80059a2: 69db ldr r3, [r3, #28] 80059a4: 68ba ldr r2, [r7, #8] 80059a6: 4013 ands r3, r2 80059a8: 68ba ldr r2, [r7, #8] 80059aa: 1ad3 subs r3, r2, r3 80059ac: 425a negs r2, r3 80059ae: 4153 adcs r3, r2 80059b0: b2db uxtb r3, r3 80059b2: 001a movs r2, r3 80059b4: 1dfb adds r3, r7, #7 80059b6: 781b ldrb r3, [r3, #0] 80059b8: 429a cmp r2, r3 80059ba: d09e beq.n 80058fa } } } } return HAL_OK; 80059bc: 2300 movs r3, #0 } 80059be: 0018 movs r0, r3 80059c0: 46bd mov sp, r7 80059c2: b004 add sp, #16 80059c4: bd80 pop {r7, pc} ... 080059c8 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80059c8: b580 push {r7, lr} 80059ca: b090 sub sp, #64 @ 0x40 80059cc: af00 add r7, sp, #0 80059ce: 60f8 str r0, [r7, #12] 80059d0: 60b9 str r1, [r7, #8] 80059d2: 1dbb adds r3, r7, #6 80059d4: 801a strh r2, [r3, #0] huart->pRxBuffPtr = pData; 80059d6: 68fb ldr r3, [r7, #12] 80059d8: 68ba ldr r2, [r7, #8] 80059da: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 80059dc: 68fb ldr r3, [r7, #12] 80059de: 1dba adds r2, r7, #6 80059e0: 215c movs r1, #92 @ 0x5c 80059e2: 8812 ldrh r2, [r2, #0] 80059e4: 525a strh r2, [r3, r1] huart->ErrorCode = HAL_UART_ERROR_NONE; 80059e6: 68fb ldr r3, [r7, #12] 80059e8: 2290 movs r2, #144 @ 0x90 80059ea: 2100 movs r1, #0 80059ec: 5099 str r1, [r3, r2] huart->RxState = HAL_UART_STATE_BUSY_RX; 80059ee: 68fb ldr r3, [r7, #12] 80059f0: 228c movs r2, #140 @ 0x8c 80059f2: 2122 movs r1, #34 @ 0x22 80059f4: 5099 str r1, [r3, r2] if (huart->hdmarx != NULL) 80059f6: 68fb ldr r3, [r7, #12] 80059f8: 2280 movs r2, #128 @ 0x80 80059fa: 589b ldr r3, [r3, r2] 80059fc: 2b00 cmp r3, #0 80059fe: d02d beq.n 8005a5c { /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8005a00: 68fb ldr r3, [r7, #12] 8005a02: 2280 movs r2, #128 @ 0x80 8005a04: 589b ldr r3, [r3, r2] 8005a06: 4a40 ldr r2, [pc, #256] @ (8005b08 ) 8005a08: 62da str r2, [r3, #44] @ 0x2c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 8005a0a: 68fb ldr r3, [r7, #12] 8005a0c: 2280 movs r2, #128 @ 0x80 8005a0e: 589b ldr r3, [r3, r2] 8005a10: 4a3e ldr r2, [pc, #248] @ (8005b0c ) 8005a12: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 8005a14: 68fb ldr r3, [r7, #12] 8005a16: 2280 movs r2, #128 @ 0x80 8005a18: 589b ldr r3, [r3, r2] 8005a1a: 4a3d ldr r2, [pc, #244] @ (8005b10 ) 8005a1c: 635a str r2, [r3, #52] @ 0x34 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 8005a1e: 68fb ldr r3, [r7, #12] 8005a20: 2280 movs r2, #128 @ 0x80 8005a22: 589b ldr r3, [r3, r2] 8005a24: 2200 movs r2, #0 8005a26: 639a str r2, [r3, #56] @ 0x38 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) 8005a28: 68fb ldr r3, [r7, #12] 8005a2a: 2280 movs r2, #128 @ 0x80 8005a2c: 5898 ldr r0, [r3, r2] 8005a2e: 68fb ldr r3, [r7, #12] 8005a30: 681b ldr r3, [r3, #0] 8005a32: 3324 adds r3, #36 @ 0x24 8005a34: 0019 movs r1, r3 8005a36: 68fb ldr r3, [r7, #12] 8005a38: 6d9b ldr r3, [r3, #88] @ 0x58 8005a3a: 001a movs r2, r3 8005a3c: 1dbb adds r3, r7, #6 8005a3e: 881b ldrh r3, [r3, #0] 8005a40: f7fd f9f2 bl 8002e28 8005a44: 1e03 subs r3, r0, #0 8005a46: d009 beq.n 8005a5c { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8005a48: 68fb ldr r3, [r7, #12] 8005a4a: 2290 movs r2, #144 @ 0x90 8005a4c: 2110 movs r1, #16 8005a4e: 5099 str r1, [r3, r2] /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; 8005a50: 68fb ldr r3, [r7, #12] 8005a52: 228c movs r2, #140 @ 0x8c 8005a54: 2120 movs r1, #32 8005a56: 5099 str r1, [r3, r2] return HAL_ERROR; 8005a58: 2301 movs r3, #1 8005a5a: e050 b.n 8005afe } } /* Enable the UART Parity Error Interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8005a5c: 68fb ldr r3, [r7, #12] 8005a5e: 691b ldr r3, [r3, #16] 8005a60: 2b00 cmp r3, #0 8005a62: d019 beq.n 8005a98 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005a64: f3ef 8310 mrs r3, PRIMASK 8005a68: 62bb str r3, [r7, #40] @ 0x28 return(result); 8005a6a: 6abb ldr r3, [r7, #40] @ 0x28 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005a6c: 63fb str r3, [r7, #60] @ 0x3c 8005a6e: 2301 movs r3, #1 8005a70: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005a72: 6afb ldr r3, [r7, #44] @ 0x2c 8005a74: f383 8810 msr PRIMASK, r3 } 8005a78: 46c0 nop @ (mov r8, r8) 8005a7a: 68fb ldr r3, [r7, #12] 8005a7c: 681b ldr r3, [r3, #0] 8005a7e: 681a ldr r2, [r3, #0] 8005a80: 68fb ldr r3, [r7, #12] 8005a82: 681b ldr r3, [r3, #0] 8005a84: 2180 movs r1, #128 @ 0x80 8005a86: 0049 lsls r1, r1, #1 8005a88: 430a orrs r2, r1 8005a8a: 601a str r2, [r3, #0] 8005a8c: 6bfb ldr r3, [r7, #60] @ 0x3c 8005a8e: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005a90: 6b3b ldr r3, [r7, #48] @ 0x30 8005a92: f383 8810 msr PRIMASK, r3 } 8005a96: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005a98: f3ef 8310 mrs r3, PRIMASK 8005a9c: 613b str r3, [r7, #16] return(result); 8005a9e: 693b ldr r3, [r7, #16] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005aa0: 63bb str r3, [r7, #56] @ 0x38 8005aa2: 2301 movs r3, #1 8005aa4: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005aa6: 697b ldr r3, [r7, #20] 8005aa8: f383 8810 msr PRIMASK, r3 } 8005aac: 46c0 nop @ (mov r8, r8) 8005aae: 68fb ldr r3, [r7, #12] 8005ab0: 681b ldr r3, [r3, #0] 8005ab2: 689a ldr r2, [r3, #8] 8005ab4: 68fb ldr r3, [r7, #12] 8005ab6: 681b ldr r3, [r3, #0] 8005ab8: 2101 movs r1, #1 8005aba: 430a orrs r2, r1 8005abc: 609a str r2, [r3, #8] 8005abe: 6bbb ldr r3, [r7, #56] @ 0x38 8005ac0: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005ac2: 69bb ldr r3, [r7, #24] 8005ac4: f383 8810 msr PRIMASK, r3 } 8005ac8: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005aca: f3ef 8310 mrs r3, PRIMASK 8005ace: 61fb str r3, [r7, #28] return(result); 8005ad0: 69fb ldr r3, [r7, #28] /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005ad2: 637b str r3, [r7, #52] @ 0x34 8005ad4: 2301 movs r3, #1 8005ad6: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005ad8: 6a3b ldr r3, [r7, #32] 8005ada: f383 8810 msr PRIMASK, r3 } 8005ade: 46c0 nop @ (mov r8, r8) 8005ae0: 68fb ldr r3, [r7, #12] 8005ae2: 681b ldr r3, [r3, #0] 8005ae4: 689a ldr r2, [r3, #8] 8005ae6: 68fb ldr r3, [r7, #12] 8005ae8: 681b ldr r3, [r3, #0] 8005aea: 2140 movs r1, #64 @ 0x40 8005aec: 430a orrs r2, r1 8005aee: 609a str r2, [r3, #8] 8005af0: 6b7b ldr r3, [r7, #52] @ 0x34 8005af2: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005af4: 6a7b ldr r3, [r7, #36] @ 0x24 8005af6: f383 8810 msr PRIMASK, r3 } 8005afa: 46c0 nop @ (mov r8, r8) return HAL_OK; 8005afc: 2300 movs r3, #0 } 8005afe: 0018 movs r0, r3 8005b00: 46bd mov sp, r7 8005b02: b010 add sp, #64 @ 0x40 8005b04: bd80 pop {r7, pc} 8005b06: 46c0 nop @ (mov r8, r8) 8005b08: 08005d19 .word 0x08005d19 8005b0c: 08005e49 .word 0x08005e49 8005b10: 08005e8b .word 0x08005e8b 08005b14 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8005b14: b580 push {r7, lr} 8005b16: b08a sub sp, #40 @ 0x28 8005b18: af00 add r7, sp, #0 8005b1a: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005b1c: f3ef 8310 mrs r3, PRIMASK 8005b20: 60bb str r3, [r7, #8] return(result); 8005b22: 68bb ldr r3, [r7, #8] /* Disable TXEIE, TCIE, TXFT interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); 8005b24: 627b str r3, [r7, #36] @ 0x24 8005b26: 2301 movs r3, #1 8005b28: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005b2a: 68fb ldr r3, [r7, #12] 8005b2c: f383 8810 msr PRIMASK, r3 } 8005b30: 46c0 nop @ (mov r8, r8) 8005b32: 687b ldr r3, [r7, #4] 8005b34: 681b ldr r3, [r3, #0] 8005b36: 681a ldr r2, [r3, #0] 8005b38: 687b ldr r3, [r7, #4] 8005b3a: 681b ldr r3, [r3, #0] 8005b3c: 21c0 movs r1, #192 @ 0xc0 8005b3e: 438a bics r2, r1 8005b40: 601a str r2, [r3, #0] 8005b42: 6a7b ldr r3, [r7, #36] @ 0x24 8005b44: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005b46: 693b ldr r3, [r7, #16] 8005b48: f383 8810 msr PRIMASK, r3 } 8005b4c: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005b4e: f3ef 8310 mrs r3, PRIMASK 8005b52: 617b str r3, [r7, #20] return(result); 8005b54: 697b ldr r3, [r7, #20] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); 8005b56: 623b str r3, [r7, #32] 8005b58: 2301 movs r3, #1 8005b5a: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005b5c: 69bb ldr r3, [r7, #24] 8005b5e: f383 8810 msr PRIMASK, r3 } 8005b62: 46c0 nop @ (mov r8, r8) 8005b64: 687b ldr r3, [r7, #4] 8005b66: 681b ldr r3, [r3, #0] 8005b68: 689a ldr r2, [r3, #8] 8005b6a: 687b ldr r3, [r7, #4] 8005b6c: 681b ldr r3, [r3, #0] 8005b6e: 4908 ldr r1, [pc, #32] @ (8005b90 ) 8005b70: 400a ands r2, r1 8005b72: 609a str r2, [r3, #8] 8005b74: 6a3b ldr r3, [r7, #32] 8005b76: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005b78: 69fb ldr r3, [r7, #28] 8005b7a: f383 8810 msr PRIMASK, r3 } 8005b7e: 46c0 nop @ (mov r8, r8) /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8005b80: 687b ldr r3, [r7, #4] 8005b82: 2288 movs r2, #136 @ 0x88 8005b84: 2120 movs r1, #32 8005b86: 5099 str r1, [r3, r2] } 8005b88: 46c0 nop @ (mov r8, r8) 8005b8a: 46bd mov sp, r7 8005b8c: b00a add sp, #40 @ 0x28 8005b8e: bd80 pop {r7, pc} 8005b90: ff7fffff .word 0xff7fffff 08005b94 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8005b94: b580 push {r7, lr} 8005b96: b08e sub sp, #56 @ 0x38 8005b98: af00 add r7, sp, #0 8005b9a: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005b9c: f3ef 8310 mrs r3, PRIMASK 8005ba0: 617b str r3, [r7, #20] return(result); 8005ba2: 697b ldr r3, [r7, #20] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8005ba4: 637b str r3, [r7, #52] @ 0x34 8005ba6: 2301 movs r3, #1 8005ba8: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005baa: 69bb ldr r3, [r7, #24] 8005bac: f383 8810 msr PRIMASK, r3 } 8005bb0: 46c0 nop @ (mov r8, r8) 8005bb2: 687b ldr r3, [r7, #4] 8005bb4: 681b ldr r3, [r3, #0] 8005bb6: 681a ldr r2, [r3, #0] 8005bb8: 687b ldr r3, [r7, #4] 8005bba: 681b ldr r3, [r3, #0] 8005bbc: 4926 ldr r1, [pc, #152] @ (8005c58 ) 8005bbe: 400a ands r2, r1 8005bc0: 601a str r2, [r3, #0] 8005bc2: 6b7b ldr r3, [r7, #52] @ 0x34 8005bc4: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005bc6: 69fb ldr r3, [r7, #28] 8005bc8: f383 8810 msr PRIMASK, r3 } 8005bcc: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005bce: f3ef 8310 mrs r3, PRIMASK 8005bd2: 623b str r3, [r7, #32] return(result); 8005bd4: 6a3b ldr r3, [r7, #32] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8005bd6: 633b str r3, [r7, #48] @ 0x30 8005bd8: 2301 movs r3, #1 8005bda: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005bdc: 6a7b ldr r3, [r7, #36] @ 0x24 8005bde: f383 8810 msr PRIMASK, r3 } 8005be2: 46c0 nop @ (mov r8, r8) 8005be4: 687b ldr r3, [r7, #4] 8005be6: 681b ldr r3, [r3, #0] 8005be8: 689a ldr r2, [r3, #8] 8005bea: 687b ldr r3, [r7, #4] 8005bec: 681b ldr r3, [r3, #0] 8005bee: 491b ldr r1, [pc, #108] @ (8005c5c ) 8005bf0: 400a ands r2, r1 8005bf2: 609a str r2, [r3, #8] 8005bf4: 6b3b ldr r3, [r7, #48] @ 0x30 8005bf6: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005bf8: 6abb ldr r3, [r7, #40] @ 0x28 8005bfa: f383 8810 msr PRIMASK, r3 } 8005bfe: 46c0 nop @ (mov r8, r8) /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005c00: 687b ldr r3, [r7, #4] 8005c02: 6edb ldr r3, [r3, #108] @ 0x6c 8005c04: 2b01 cmp r3, #1 8005c06: d118 bne.n 8005c3a __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005c08: f3ef 8310 mrs r3, PRIMASK 8005c0c: 60bb str r3, [r7, #8] return(result); 8005c0e: 68bb ldr r3, [r7, #8] { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005c10: 62fb str r3, [r7, #44] @ 0x2c 8005c12: 2301 movs r3, #1 8005c14: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005c16: 68fb ldr r3, [r7, #12] 8005c18: f383 8810 msr PRIMASK, r3 } 8005c1c: 46c0 nop @ (mov r8, r8) 8005c1e: 687b ldr r3, [r7, #4] 8005c20: 681b ldr r3, [r3, #0] 8005c22: 681a ldr r2, [r3, #0] 8005c24: 687b ldr r3, [r7, #4] 8005c26: 681b ldr r3, [r3, #0] 8005c28: 2110 movs r1, #16 8005c2a: 438a bics r2, r1 8005c2c: 601a str r2, [r3, #0] 8005c2e: 6afb ldr r3, [r7, #44] @ 0x2c 8005c30: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005c32: 693b ldr r3, [r7, #16] 8005c34: f383 8810 msr PRIMASK, r3 } 8005c38: 46c0 nop @ (mov r8, r8) } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005c3a: 687b ldr r3, [r7, #4] 8005c3c: 228c movs r2, #140 @ 0x8c 8005c3e: 2120 movs r1, #32 8005c40: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005c42: 687b ldr r3, [r7, #4] 8005c44: 2200 movs r2, #0 8005c46: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 8005c48: 687b ldr r3, [r7, #4] 8005c4a: 2200 movs r2, #0 8005c4c: 675a str r2, [r3, #116] @ 0x74 } 8005c4e: 46c0 nop @ (mov r8, r8) 8005c50: 46bd mov sp, r7 8005c52: b00e add sp, #56 @ 0x38 8005c54: bd80 pop {r7, pc} 8005c56: 46c0 nop @ (mov r8, r8) 8005c58: fffffedf .word 0xfffffedf 8005c5c: effffffe .word 0xeffffffe 08005c60 : * @brief DMA UART transmit process complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8005c60: b580 push {r7, lr} 8005c62: b08c sub sp, #48 @ 0x30 8005c64: af00 add r7, sp, #0 8005c66: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8005c68: 687b ldr r3, [r7, #4] 8005c6a: 6a9b ldr r3, [r3, #40] @ 0x28 8005c6c: 62fb str r3, [r7, #44] @ 0x2c /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) 8005c6e: 687b ldr r3, [r7, #4] 8005c70: 681b ldr r3, [r3, #0] 8005c72: 681b ldr r3, [r3, #0] 8005c74: 2220 movs r2, #32 8005c76: 4013 ands r3, r2 8005c78: d135 bne.n 8005ce6 { huart->TxXferCount = 0U; 8005c7a: 6afb ldr r3, [r7, #44] @ 0x2c 8005c7c: 2256 movs r2, #86 @ 0x56 8005c7e: 2100 movs r1, #0 8005c80: 5299 strh r1, [r3, r2] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005c82: f3ef 8310 mrs r3, PRIMASK 8005c86: 60fb str r3, [r7, #12] return(result); 8005c88: 68fb ldr r3, [r7, #12] /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8005c8a: 62bb str r3, [r7, #40] @ 0x28 8005c8c: 2301 movs r3, #1 8005c8e: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005c90: 693b ldr r3, [r7, #16] 8005c92: f383 8810 msr PRIMASK, r3 } 8005c96: 46c0 nop @ (mov r8, r8) 8005c98: 6afb ldr r3, [r7, #44] @ 0x2c 8005c9a: 681b ldr r3, [r3, #0] 8005c9c: 689a ldr r2, [r3, #8] 8005c9e: 6afb ldr r3, [r7, #44] @ 0x2c 8005ca0: 681b ldr r3, [r3, #0] 8005ca2: 2180 movs r1, #128 @ 0x80 8005ca4: 438a bics r2, r1 8005ca6: 609a str r2, [r3, #8] 8005ca8: 6abb ldr r3, [r7, #40] @ 0x28 8005caa: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005cac: 697b ldr r3, [r7, #20] 8005cae: f383 8810 msr PRIMASK, r3 } 8005cb2: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005cb4: f3ef 8310 mrs r3, PRIMASK 8005cb8: 61bb str r3, [r7, #24] return(result); 8005cba: 69bb ldr r3, [r7, #24] /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8005cbc: 627b str r3, [r7, #36] @ 0x24 8005cbe: 2301 movs r3, #1 8005cc0: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005cc2: 69fb ldr r3, [r7, #28] 8005cc4: f383 8810 msr PRIMASK, r3 } 8005cc8: 46c0 nop @ (mov r8, r8) 8005cca: 6afb ldr r3, [r7, #44] @ 0x2c 8005ccc: 681b ldr r3, [r3, #0] 8005cce: 681a ldr r2, [r3, #0] 8005cd0: 6afb ldr r3, [r7, #44] @ 0x2c 8005cd2: 681b ldr r3, [r3, #0] 8005cd4: 2140 movs r1, #64 @ 0x40 8005cd6: 430a orrs r2, r1 8005cd8: 601a str r2, [r3, #0] 8005cda: 6a7b ldr r3, [r7, #36] @ 0x24 8005cdc: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005cde: 6a3b ldr r3, [r7, #32] 8005ce0: f383 8810 msr PRIMASK, r3 } 8005ce4: e004 b.n 8005cf0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8005ce6: 6afb ldr r3, [r7, #44] @ 0x2c 8005ce8: 0018 movs r0, r3 8005cea: f7ff fb0d bl 8005308 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8005cee: 46c0 nop @ (mov r8, r8) 8005cf0: 46c0 nop @ (mov r8, r8) 8005cf2: 46bd mov sp, r7 8005cf4: b00c add sp, #48 @ 0x30 8005cf6: bd80 pop {r7, pc} 08005cf8 : * @brief DMA UART transmit process half complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 8005cf8: b580 push {r7, lr} 8005cfa: b084 sub sp, #16 8005cfc: af00 add r7, sp, #0 8005cfe: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8005d00: 687b ldr r3, [r7, #4] 8005d02: 6a9b ldr r3, [r3, #40] @ 0x28 8005d04: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx Half complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx Half complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8005d06: 68fb ldr r3, [r7, #12] 8005d08: 0018 movs r0, r3 8005d0a: f7ff fb05 bl 8005318 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8005d0e: 46c0 nop @ (mov r8, r8) 8005d10: 46bd mov sp, r7 8005d12: b004 add sp, #16 8005d14: bd80 pop {r7, pc} ... 08005d18 : * @brief DMA UART receive process complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8005d18: b580 push {r7, lr} 8005d1a: b094 sub sp, #80 @ 0x50 8005d1c: af00 add r7, sp, #0 8005d1e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8005d20: 687b ldr r3, [r7, #4] 8005d22: 6a9b ldr r3, [r3, #40] @ 0x28 8005d24: 64fb str r3, [r7, #76] @ 0x4c /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) 8005d26: 687b ldr r3, [r7, #4] 8005d28: 681b ldr r3, [r3, #0] 8005d2a: 681b ldr r3, [r3, #0] 8005d2c: 2220 movs r2, #32 8005d2e: 4013 ands r3, r2 8005d30: d16f bne.n 8005e12 { huart->RxXferCount = 0U; 8005d32: 6cfb ldr r3, [r7, #76] @ 0x4c 8005d34: 225e movs r2, #94 @ 0x5e 8005d36: 2100 movs r1, #0 8005d38: 5299 strh r1, [r3, r2] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005d3a: f3ef 8310 mrs r3, PRIMASK 8005d3e: 61bb str r3, [r7, #24] return(result); 8005d40: 69bb ldr r3, [r7, #24] /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005d42: 64bb str r3, [r7, #72] @ 0x48 8005d44: 2301 movs r3, #1 8005d46: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005d48: 69fb ldr r3, [r7, #28] 8005d4a: f383 8810 msr PRIMASK, r3 } 8005d4e: 46c0 nop @ (mov r8, r8) 8005d50: 6cfb ldr r3, [r7, #76] @ 0x4c 8005d52: 681b ldr r3, [r3, #0] 8005d54: 681a ldr r2, [r3, #0] 8005d56: 6cfb ldr r3, [r7, #76] @ 0x4c 8005d58: 681b ldr r3, [r3, #0] 8005d5a: 493a ldr r1, [pc, #232] @ (8005e44 ) 8005d5c: 400a ands r2, r1 8005d5e: 601a str r2, [r3, #0] 8005d60: 6cbb ldr r3, [r7, #72] @ 0x48 8005d62: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005d64: 6a3b ldr r3, [r7, #32] 8005d66: f383 8810 msr PRIMASK, r3 } 8005d6a: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005d6c: f3ef 8310 mrs r3, PRIMASK 8005d70: 627b str r3, [r7, #36] @ 0x24 return(result); 8005d72: 6a7b ldr r3, [r7, #36] @ 0x24 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005d74: 647b str r3, [r7, #68] @ 0x44 8005d76: 2301 movs r3, #1 8005d78: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005d7a: 6abb ldr r3, [r7, #40] @ 0x28 8005d7c: f383 8810 msr PRIMASK, r3 } 8005d80: 46c0 nop @ (mov r8, r8) 8005d82: 6cfb ldr r3, [r7, #76] @ 0x4c 8005d84: 681b ldr r3, [r3, #0] 8005d86: 689a ldr r2, [r3, #8] 8005d88: 6cfb ldr r3, [r7, #76] @ 0x4c 8005d8a: 681b ldr r3, [r3, #0] 8005d8c: 2101 movs r1, #1 8005d8e: 438a bics r2, r1 8005d90: 609a str r2, [r3, #8] 8005d92: 6c7b ldr r3, [r7, #68] @ 0x44 8005d94: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005d96: 6afb ldr r3, [r7, #44] @ 0x2c 8005d98: f383 8810 msr PRIMASK, r3 } 8005d9c: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005d9e: f3ef 8310 mrs r3, PRIMASK 8005da2: 633b str r3, [r7, #48] @ 0x30 return(result); 8005da4: 6b3b ldr r3, [r7, #48] @ 0x30 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005da6: 643b str r3, [r7, #64] @ 0x40 8005da8: 2301 movs r3, #1 8005daa: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005dac: 6b7b ldr r3, [r7, #52] @ 0x34 8005dae: f383 8810 msr PRIMASK, r3 } 8005db2: 46c0 nop @ (mov r8, r8) 8005db4: 6cfb ldr r3, [r7, #76] @ 0x4c 8005db6: 681b ldr r3, [r3, #0] 8005db8: 689a ldr r2, [r3, #8] 8005dba: 6cfb ldr r3, [r7, #76] @ 0x4c 8005dbc: 681b ldr r3, [r3, #0] 8005dbe: 2140 movs r1, #64 @ 0x40 8005dc0: 438a bics r2, r1 8005dc2: 609a str r2, [r3, #8] 8005dc4: 6c3b ldr r3, [r7, #64] @ 0x40 8005dc6: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005dc8: 6bbb ldr r3, [r7, #56] @ 0x38 8005dca: f383 8810 msr PRIMASK, r3 } 8005dce: 46c0 nop @ (mov r8, r8) /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005dd0: 6cfb ldr r3, [r7, #76] @ 0x4c 8005dd2: 228c movs r2, #140 @ 0x8c 8005dd4: 2120 movs r1, #32 8005dd6: 5099 str r1, [r3, r2] /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005dd8: 6cfb ldr r3, [r7, #76] @ 0x4c 8005dda: 6edb ldr r3, [r3, #108] @ 0x6c 8005ddc: 2b01 cmp r3, #1 8005dde: d118 bne.n 8005e12 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005de0: f3ef 8310 mrs r3, PRIMASK 8005de4: 60fb str r3, [r7, #12] return(result); 8005de6: 68fb ldr r3, [r7, #12] { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005de8: 63fb str r3, [r7, #60] @ 0x3c 8005dea: 2301 movs r3, #1 8005dec: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005dee: 693b ldr r3, [r7, #16] 8005df0: f383 8810 msr PRIMASK, r3 } 8005df4: 46c0 nop @ (mov r8, r8) 8005df6: 6cfb ldr r3, [r7, #76] @ 0x4c 8005df8: 681b ldr r3, [r3, #0] 8005dfa: 681a ldr r2, [r3, #0] 8005dfc: 6cfb ldr r3, [r7, #76] @ 0x4c 8005dfe: 681b ldr r3, [r3, #0] 8005e00: 2110 movs r1, #16 8005e02: 438a bics r2, r1 8005e04: 601a str r2, [r3, #0] 8005e06: 6bfb ldr r3, [r7, #60] @ 0x3c 8005e08: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005e0a: 697b ldr r3, [r7, #20] 8005e0c: f383 8810 msr PRIMASK, r3 } 8005e10: 46c0 nop @ (mov r8, r8) } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8005e12: 6cfb ldr r3, [r7, #76] @ 0x4c 8005e14: 2200 movs r2, #0 8005e16: 671a str r2, [r3, #112] @ 0x70 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005e18: 6cfb ldr r3, [r7, #76] @ 0x4c 8005e1a: 6edb ldr r3, [r3, #108] @ 0x6c 8005e1c: 2b01 cmp r3, #1 8005e1e: d108 bne.n 8005e32 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8005e20: 6cfb ldr r3, [r7, #76] @ 0x4c 8005e22: 225c movs r2, #92 @ 0x5c 8005e24: 5a9a ldrh r2, [r3, r2] 8005e26: 6cfb ldr r3, [r7, #76] @ 0x4c 8005e28: 0011 movs r1, r2 8005e2a: 0018 movs r0, r3 8005e2c: f7fb f9de bl 80011ec #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8005e30: e003 b.n 8005e3a HAL_UART_RxCpltCallback(huart); 8005e32: 6cfb ldr r3, [r7, #76] @ 0x4c 8005e34: 0018 movs r0, r3 8005e36: f7ff fa77 bl 8005328 } 8005e3a: 46c0 nop @ (mov r8, r8) 8005e3c: 46bd mov sp, r7 8005e3e: b014 add sp, #80 @ 0x50 8005e40: bd80 pop {r7, pc} 8005e42: 46c0 nop @ (mov r8, r8) 8005e44: fffffeff .word 0xfffffeff 08005e48 : * @brief DMA UART receive process half complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8005e48: b580 push {r7, lr} 8005e4a: b084 sub sp, #16 8005e4c: af00 add r7, sp, #0 8005e4e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8005e50: 687b ldr r3, [r7, #4] 8005e52: 6a9b ldr r3, [r3, #40] @ 0x28 8005e54: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 8005e56: 68fb ldr r3, [r7, #12] 8005e58: 2201 movs r2, #1 8005e5a: 671a str r2, [r3, #112] @ 0x70 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005e5c: 68fb ldr r3, [r7, #12] 8005e5e: 6edb ldr r3, [r3, #108] @ 0x6c 8005e60: 2b01 cmp r3, #1 8005e62: d10a bne.n 8005e7a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 8005e64: 68fb ldr r3, [r7, #12] 8005e66: 225c movs r2, #92 @ 0x5c 8005e68: 5a9b ldrh r3, [r3, r2] 8005e6a: 085b lsrs r3, r3, #1 8005e6c: b29a uxth r2, r3 8005e6e: 68fb ldr r3, [r7, #12] 8005e70: 0011 movs r1, r2 8005e72: 0018 movs r0, r3 8005e74: f7fb f9ba bl 80011ec #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8005e78: e003 b.n 8005e82 HAL_UART_RxHalfCpltCallback(huart); 8005e7a: 68fb ldr r3, [r7, #12] 8005e7c: 0018 movs r0, r3 8005e7e: f7ff fa5b bl 8005338 } 8005e82: 46c0 nop @ (mov r8, r8) 8005e84: 46bd mov sp, r7 8005e86: b004 add sp, #16 8005e88: bd80 pop {r7, pc} 08005e8a : * @brief DMA UART communication error callback. * @param hdma DMA handle. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8005e8a: b580 push {r7, lr} 8005e8c: b086 sub sp, #24 8005e8e: af00 add r7, sp, #0 8005e90: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8005e92: 687b ldr r3, [r7, #4] 8005e94: 6a9b ldr r3, [r3, #40] @ 0x28 8005e96: 617b str r3, [r7, #20] const HAL_UART_StateTypeDef gstate = huart->gState; 8005e98: 697b ldr r3, [r7, #20] 8005e9a: 2288 movs r2, #136 @ 0x88 8005e9c: 589b ldr r3, [r3, r2] 8005e9e: 613b str r3, [r7, #16] const HAL_UART_StateTypeDef rxstate = huart->RxState; 8005ea0: 697b ldr r3, [r7, #20] 8005ea2: 228c movs r2, #140 @ 0x8c 8005ea4: 589b ldr r3, [r3, r2] 8005ea6: 60fb str r3, [r7, #12] /* Stop UART DMA Tx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && 8005ea8: 697b ldr r3, [r7, #20] 8005eaa: 681b ldr r3, [r3, #0] 8005eac: 689b ldr r3, [r3, #8] 8005eae: 2280 movs r2, #128 @ 0x80 8005eb0: 4013 ands r3, r2 8005eb2: 2b80 cmp r3, #128 @ 0x80 8005eb4: d10a bne.n 8005ecc 8005eb6: 693b ldr r3, [r7, #16] 8005eb8: 2b21 cmp r3, #33 @ 0x21 8005eba: d107 bne.n 8005ecc (gstate == HAL_UART_STATE_BUSY_TX)) { huart->TxXferCount = 0U; 8005ebc: 697b ldr r3, [r7, #20] 8005ebe: 2256 movs r2, #86 @ 0x56 8005ec0: 2100 movs r1, #0 8005ec2: 5299 strh r1, [r3, r2] UART_EndTxTransfer(huart); 8005ec4: 697b ldr r3, [r7, #20] 8005ec6: 0018 movs r0, r3 8005ec8: f7ff fe24 bl 8005b14 } /* Stop UART DMA Rx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && 8005ecc: 697b ldr r3, [r7, #20] 8005ece: 681b ldr r3, [r3, #0] 8005ed0: 689b ldr r3, [r3, #8] 8005ed2: 2240 movs r2, #64 @ 0x40 8005ed4: 4013 ands r3, r2 8005ed6: 2b40 cmp r3, #64 @ 0x40 8005ed8: d10a bne.n 8005ef0 8005eda: 68fb ldr r3, [r7, #12] 8005edc: 2b22 cmp r3, #34 @ 0x22 8005ede: d107 bne.n 8005ef0 (rxstate == HAL_UART_STATE_BUSY_RX)) { huart->RxXferCount = 0U; 8005ee0: 697b ldr r3, [r7, #20] 8005ee2: 225e movs r2, #94 @ 0x5e 8005ee4: 2100 movs r1, #0 8005ee6: 5299 strh r1, [r3, r2] UART_EndRxTransfer(huart); 8005ee8: 697b ldr r3, [r7, #20] 8005eea: 0018 movs r0, r3 8005eec: f7ff fe52 bl 8005b94 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8005ef0: 697b ldr r3, [r7, #20] 8005ef2: 2290 movs r2, #144 @ 0x90 8005ef4: 589b ldr r3, [r3, r2] 8005ef6: 2210 movs r2, #16 8005ef8: 431a orrs r2, r3 8005efa: 697b ldr r3, [r7, #20] 8005efc: 2190 movs r1, #144 @ 0x90 8005efe: 505a str r2, [r3, r1] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005f00: 697b ldr r3, [r7, #20] 8005f02: 0018 movs r0, r3 8005f04: f7ff fa20 bl 8005348 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8005f08: 46c0 nop @ (mov r8, r8) 8005f0a: 46bd mov sp, r7 8005f0c: b006 add sp, #24 8005f0e: bd80 pop {r7, pc} 08005f10 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8005f10: b5b0 push {r4, r5, r7, lr} 8005f12: b08a sub sp, #40 @ 0x28 8005f14: af00 add r7, sp, #0 8005f16: 60f8 str r0, [r7, #12] 8005f18: 60b9 str r1, [r7, #8] 8005f1a: 1dbb adds r3, r7, #6 8005f1c: 801a strh r2, [r3, #0] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8005f1e: 68fb ldr r3, [r7, #12] 8005f20: 228c movs r2, #140 @ 0x8c 8005f22: 589b ldr r3, [r3, r2] 8005f24: 2b20 cmp r3, #32 8005f26: d156 bne.n 8005fd6 { if ((pData == NULL) || (Size == 0U)) 8005f28: 68bb ldr r3, [r7, #8] 8005f2a: 2b00 cmp r3, #0 8005f2c: d003 beq.n 8005f36 8005f2e: 1dbb adds r3, r7, #6 8005f30: 881b ldrh r3, [r3, #0] 8005f32: 2b00 cmp r3, #0 8005f34: d101 bne.n 8005f3a { return HAL_ERROR; 8005f36: 2301 movs r3, #1 8005f38: e04e b.n 8005fd8 } /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter should be aligned on a uint16_t frontier, as data copy from RDR will be handled by DMA from a uint16_t frontier. */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8005f3a: 68fb ldr r3, [r7, #12] 8005f3c: 689a ldr r2, [r3, #8] 8005f3e: 2380 movs r3, #128 @ 0x80 8005f40: 015b lsls r3, r3, #5 8005f42: 429a cmp r2, r3 8005f44: d109 bne.n 8005f5a 8005f46: 68fb ldr r3, [r7, #12] 8005f48: 691b ldr r3, [r3, #16] 8005f4a: 2b00 cmp r3, #0 8005f4c: d105 bne.n 8005f5a { if ((((uint32_t)pData) & 1U) != 0U) 8005f4e: 68bb ldr r3, [r7, #8] 8005f50: 2201 movs r2, #1 8005f52: 4013 ands r3, r2 8005f54: d001 beq.n 8005f5a { return HAL_ERROR; 8005f56: 2301 movs r3, #1 8005f58: e03e b.n 8005fd8 } } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8005f5a: 68fb ldr r3, [r7, #12] 8005f5c: 2201 movs r2, #1 8005f5e: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8005f60: 68fb ldr r3, [r7, #12] 8005f62: 2200 movs r2, #0 8005f64: 671a str r2, [r3, #112] @ 0x70 status = UART_Start_Receive_DMA(huart, pData, Size); 8005f66: 2527 movs r5, #39 @ 0x27 8005f68: 197c adds r4, r7, r5 8005f6a: 1dbb adds r3, r7, #6 8005f6c: 881a ldrh r2, [r3, #0] 8005f6e: 68b9 ldr r1, [r7, #8] 8005f70: 68fb ldr r3, [r7, #12] 8005f72: 0018 movs r0, r3 8005f74: f7ff fd28 bl 80059c8 8005f78: 0003 movs r3, r0 8005f7a: 7023 strb r3, [r4, #0] /* Check Rx process has been successfully started */ if (status == HAL_OK) 8005f7c: 197b adds r3, r7, r5 8005f7e: 781b ldrb r3, [r3, #0] 8005f80: 2b00 cmp r3, #0 8005f82: d124 bne.n 8005fce { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005f84: 68fb ldr r3, [r7, #12] 8005f86: 6edb ldr r3, [r3, #108] @ 0x6c 8005f88: 2b01 cmp r3, #1 8005f8a: d11c bne.n 8005fc6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8005f8c: 68fb ldr r3, [r7, #12] 8005f8e: 681b ldr r3, [r3, #0] 8005f90: 2210 movs r2, #16 8005f92: 621a str r2, [r3, #32] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8005f94: f3ef 8310 mrs r3, PRIMASK 8005f98: 617b str r3, [r7, #20] return(result); 8005f9a: 697b ldr r3, [r7, #20] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005f9c: 623b str r3, [r7, #32] 8005f9e: 2301 movs r3, #1 8005fa0: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005fa2: 69bb ldr r3, [r7, #24] 8005fa4: f383 8810 msr PRIMASK, r3 } 8005fa8: 46c0 nop @ (mov r8, r8) 8005faa: 68fb ldr r3, [r7, #12] 8005fac: 681b ldr r3, [r3, #0] 8005fae: 681a ldr r2, [r3, #0] 8005fb0: 68fb ldr r3, [r7, #12] 8005fb2: 681b ldr r3, [r3, #0] 8005fb4: 2110 movs r1, #16 8005fb6: 430a orrs r2, r1 8005fb8: 601a str r2, [r3, #0] 8005fba: 6a3b ldr r3, [r7, #32] 8005fbc: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8005fbe: 69fb ldr r3, [r7, #28] 8005fc0: f383 8810 msr PRIMASK, r3 } 8005fc4: e003 b.n 8005fce { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8005fc6: 2327 movs r3, #39 @ 0x27 8005fc8: 18fb adds r3, r7, r3 8005fca: 2201 movs r2, #1 8005fcc: 701a strb r2, [r3, #0] } } return status; 8005fce: 2327 movs r3, #39 @ 0x27 8005fd0: 18fb adds r3, r7, r3 8005fd2: 781b ldrb r3, [r3, #0] 8005fd4: e000 b.n 8005fd8 } else { return HAL_BUSY; 8005fd6: 2302 movs r3, #2 } } 8005fd8: 0018 movs r0, r3 8005fda: 46bd mov sp, r7 8005fdc: b00a add sp, #40 @ 0x28 8005fde: bdb0 pop {r4, r5, r7, pc} 08005fe0 : 8005fe0: 0003 movs r3, r0 8005fe2: 1882 adds r2, r0, r2 8005fe4: 4293 cmp r3, r2 8005fe6: d100 bne.n 8005fea 8005fe8: 4770 bx lr 8005fea: 7019 strb r1, [r3, #0] 8005fec: 3301 adds r3, #1 8005fee: e7f9 b.n 8005fe4 08005ff0 <__libc_init_array>: 8005ff0: b570 push {r4, r5, r6, lr} 8005ff2: 2600 movs r6, #0 8005ff4: 4c0c ldr r4, [pc, #48] @ (8006028 <__libc_init_array+0x38>) 8005ff6: 4d0d ldr r5, [pc, #52] @ (800602c <__libc_init_array+0x3c>) 8005ff8: 1b64 subs r4, r4, r5 8005ffa: 10a4 asrs r4, r4, #2 8005ffc: 42a6 cmp r6, r4 8005ffe: d109 bne.n 8006014 <__libc_init_array+0x24> 8006000: 2600 movs r6, #0 8006002: f000 f819 bl 8006038 <_init> 8006006: 4c0a ldr r4, [pc, #40] @ (8006030 <__libc_init_array+0x40>) 8006008: 4d0a ldr r5, [pc, #40] @ (8006034 <__libc_init_array+0x44>) 800600a: 1b64 subs r4, r4, r5 800600c: 10a4 asrs r4, r4, #2 800600e: 42a6 cmp r6, r4 8006010: d105 bne.n 800601e <__libc_init_array+0x2e> 8006012: bd70 pop {r4, r5, r6, pc} 8006014: 00b3 lsls r3, r6, #2 8006016: 58eb ldr r3, [r5, r3] 8006018: 4798 blx r3 800601a: 3601 adds r6, #1 800601c: e7ee b.n 8005ffc <__libc_init_array+0xc> 800601e: 00b3 lsls r3, r6, #2 8006020: 58eb ldr r3, [r5, r3] 8006022: 4798 blx r3 8006024: 3601 adds r6, #1 8006026: e7f2 b.n 800600e <__libc_init_array+0x1e> 8006028: 08006140 .word 0x08006140 800602c: 08006140 .word 0x08006140 8006030: 08006144 .word 0x08006144 8006034: 08006140 .word 0x08006140 08006038 <_init>: 8006038: b5f8 push {r3, r4, r5, r6, r7, lr} 800603a: 46c0 nop @ (mov r8, r8) 800603c: bcf8 pop {r3, r4, r5, r6, r7} 800603e: bc08 pop {r3} 8006040: 469e mov lr, r3 8006042: 4770 bx lr 08006044 <_fini>: 8006044: b5f8 push {r3, r4, r5, r6, r7, lr} 8006046: 46c0 nop @ (mov r8, r8) 8006048: bcf8 pop {r3, r4, r5, r6, r7} 800604a: bc08 pop {r3} 800604c: 469e mov lr, r3 800604e: 4770 bx lr 08006050 <__FLASH_Program_Fast_veneer>: 8006050: b401 push {r0} 8006052: 4802 ldr r0, [pc, #8] @ (800605c <__FLASH_Program_Fast_veneer+0xc>) 8006054: 4684 mov ip, r0 8006056: bc01 pop {r0} 8006058: 4760 bx ip 800605a: bf00 nop 800605c: 2000010d .word 0x2000010d Disassembly of section .data: 20000000 : 20000000: 00f42400 .$.. 20000004 : 20000004: aa7fd500 54812bfe 8356fc29 7da802d7 .....+.T).V....} 20000014: f82d8752 06d379ac d104ae7b 2ffa5085 R.-..y..{....P./ 20000024: 0edb71a4 f0258f5a 27f2588d d90ca673 .q..Z.%..X.'s... 20000034: 5c8923f6 a277dd08 75a00adf 8b5ef421 .#.\..w....u!.^. 20000044: 37e2489d c91cb663 1ecb61b4 e0359f4a .H.7c....a..J.5. 20000054: 65b01acf 9b4ee431 4c9933e6 b267cd18 ...e1.N..3.L..g. 20000064: 9346ec39 6db812c7 ba6fc510 44913bee 9.F....m..o..;.D 20000074: c114be6b 3fea4095 e83d9742 16c369bc k....@.?B.=..i.. 20000084: 45903aef bb6ec411 6cb913c6 9247ed38 .:.E..n....l8.G. 20000094: 17c268bd e93c9643 3eeb4194 c015bf6a .h..C.<..A.>j... 200000a4: e1349e4b 1fca60b5 c81db762 36e3499c K.4..`..b....I.6 200000b4: b366cc19 4d9832e7 9a4fe530 64b11bce ..f..2.M0.O....d 200000c4: d80da772 26f3598c f1248e5b 0fda70a5 r....Y.&[.$..p.. 200000d4: 8a5ff520 74a10bde a376dc09 5d8822f7 ._....t..v..".] 200000e4: 7ca903d6 8257fd28 55802aff ab7ed401 ...|(.W..*.U..~. 200000f4: 2efb5184 d005af7a 07d278ad f92c8653 .Q..z....x..S.,. 20000104 : 20000104: 00000004 .... 20000108 : 20000108: 00000001 .... 2000010c : * @param Address Specifies the address to be programmed. * @param DataAddress Specifies the address where the data are stored. * @retval None */ static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) { 2000010c: b580 push {r7, lr} 2000010e: b088 sub sp, #32 20000110: af00 add r7, sp, #0 20000112: 6078 str r0, [r7, #4] 20000114: 6039 str r1, [r7, #0] uint8_t index = 0; 20000116: 231f movs r3, #31 20000118: 18fb adds r3, r7, r3 2000011a: 2200 movs r2, #0 2000011c: 701a strb r2, [r3, #0] uint32_t dest = Address; 2000011e: 687b ldr r3, [r7, #4] 20000120: 61bb str r3, [r7, #24] uint32_t src = DataAddress; 20000122: 683b ldr r3, [r7, #0] 20000124: 617b str r3, [r7, #20] uint32_t primask_bit; /* Set FSTPG bit */ SET_BIT(FLASH->CR, FLASH_CR_FSTPG); 20000126: 4b1a ldr r3, [pc, #104] @ (20000190 ) 20000128: 695a ldr r2, [r3, #20] 2000012a: 4b19 ldr r3, [pc, #100] @ (20000190 ) 2000012c: 2180 movs r1, #128 @ 0x80 2000012e: 02c9 lsls r1, r1, #11 20000130: 430a orrs r2, r1 20000132: 615a str r2, [r3, #20] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 20000134: f3ef 8310 mrs r3, PRIMASK 20000138: 60fb str r3, [r7, #12] return(result); 2000013a: 68fb ldr r3, [r7, #12] /* Enter critical section: row programming should not be longer than 7 ms */ primask_bit = __get_PRIMASK(); 2000013c: 613b str r3, [r7, #16] __ASM volatile ("cpsid i" : : : "memory"); 2000013e: b672 cpsid i } 20000140: 46c0 nop @ (mov r8, r8) __disable_irq(); /* Fast Program : 64 words */ while (index < 64U) 20000142: e00f b.n 20000164 { *(uint32_t *)dest = *(uint32_t *)src; 20000144: 697a ldr r2, [r7, #20] 20000146: 69bb ldr r3, [r7, #24] 20000148: 6812 ldr r2, [r2, #0] 2000014a: 601a str r2, [r3, #0] src += 4U; 2000014c: 697b ldr r3, [r7, #20] 2000014e: 3304 adds r3, #4 20000150: 617b str r3, [r7, #20] dest += 4U; 20000152: 69bb ldr r3, [r7, #24] 20000154: 3304 adds r3, #4 20000156: 61bb str r3, [r7, #24] index++; 20000158: 211f movs r1, #31 2000015a: 187b adds r3, r7, r1 2000015c: 781a ldrb r2, [r3, #0] 2000015e: 187b adds r3, r7, r1 20000160: 3201 adds r2, #1 20000162: 701a strb r2, [r3, #0] while (index < 64U) 20000164: 231f movs r3, #31 20000166: 18fb adds r3, r7, r3 20000168: 781b ldrb r3, [r3, #0] 2000016a: 2b3f cmp r3, #63 @ 0x3f 2000016c: d9ea bls.n 20000144 be anyway done later */ #if defined(FLASH_DBANK_SUPPORT) while ((FLASH->SR & (FLASH_SR_BSY1 | FLASH_SR_BSY2)) != 0x00U) #else while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U) 2000016e: 46c0 nop @ (mov r8, r8) 20000170: 4b07 ldr r3, [pc, #28] @ (20000190 ) 20000172: 691a ldr r2, [r3, #16] 20000174: 2380 movs r3, #128 @ 0x80 20000176: 025b lsls r3, r3, #9 20000178: 4013 ands r3, r2 2000017a: d1f9 bne.n 20000170 2000017c: 693b ldr r3, [r7, #16] 2000017e: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 20000180: 68bb ldr r3, [r7, #8] 20000182: f383 8810 msr PRIMASK, r3 } 20000186: 46c0 nop @ (mov r8, r8) { } /* Exit critical section: restore previous priority mask */ __set_PRIMASK(primask_bit); } 20000188: 46c0 nop @ (mov r8, r8) 2000018a: 46bd mov sp, r7 2000018c: b008 add sp, #32 2000018e: bd80 pop {r7, pc} 20000190: 40022000 .word 0x40022000