STM32G030_Dshot/Debug/STM32G030_Dshot.list

STM32G030_Dshot.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000000b8  08000000  08000000  00001000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00002fe0  080000b8  080000b8  000010b8  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000040  08003098  08003098  00004098  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  080030d8  080030d8  0000500c  2**0
                  CONTENTS
  4 .ARM          00000000  080030d8  080030d8  0000500c  2**0
                  CONTENTS
  5 .preinit_array 00000000  080030d8  080030d8  0000500c  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  080030d8  080030d8  000040d8  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  080030dc  080030dc  000040dc  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         0000000c  20000000  080030e0  00005000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          000001d4  2000000c  080030ec  0000500c  2**2
                  ALLOC
 10 ._user_heap_stack 00000600  200001e0  080030ec  000051e0  2**0
                  ALLOC
 11 .ARM.attributes 00000028  00000000  00000000  0000500c  2**0
                  CONTENTS, READONLY
 12 .debug_info   0000a1c3  00000000  00000000  00005034  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_abbrev 00001d00  00000000  00000000  0000f1f7  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_aranges 00000b28  00000000  00000000  00010ef8  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_rnglists 0000089c  00000000  00000000  00011a20  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_macro  00014370  00000000  00000000  000122bc  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_line   0000c984  00000000  00000000  0002662c  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_str    00080c0f  00000000  00000000  00032fb0  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .comment      00000043  00000000  00000000  000b3bbf  2**0
                  CONTENTS, READONLY
 20 .debug_frame  00002744  00000000  00000000  000b3c04  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 21 .debug_line_str 0000004a  00000000  00000000  000b6348  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

080000b8 <__do_global_dtors_aux>:
 80000b8:	b510      	push	{r4, lr}
 80000ba:	4c06      	ldr	r4, [pc, #24]	@ (80000d4 <__do_global_dtors_aux+0x1c>)
 80000bc:	7823      	ldrb	r3, [r4, #0]
 80000be:	2b00      	cmp	r3, #0
 80000c0:	d107      	bne.n	80000d2 <__do_global_dtors_aux+0x1a>
 80000c2:	4b05      	ldr	r3, [pc, #20]	@ (80000d8 <__do_global_dtors_aux+0x20>)
 80000c4:	2b00      	cmp	r3, #0
 80000c6:	d002      	beq.n	80000ce <__do_global_dtors_aux+0x16>
 80000c8:	4804      	ldr	r0, [pc, #16]	@ (80000dc <__do_global_dtors_aux+0x24>)
 80000ca:	e000      	b.n	80000ce <__do_global_dtors_aux+0x16>
 80000cc:	bf00      	nop
 80000ce:	2301      	movs	r3, #1
 80000d0:	7023      	strb	r3, [r4, #0]
 80000d2:	bd10      	pop	{r4, pc}
 80000d4:	2000000c 	.word	0x2000000c
 80000d8:	00000000 	.word	0x00000000
 80000dc:	08003080 	.word	0x08003080

080000e0 <frame_dummy>:
 80000e0:	4b04      	ldr	r3, [pc, #16]	@ (80000f4 <frame_dummy+0x14>)
 80000e2:	b510      	push	{r4, lr}
 80000e4:	2b00      	cmp	r3, #0
 80000e6:	d003      	beq.n	80000f0 <frame_dummy+0x10>
 80000e8:	4903      	ldr	r1, [pc, #12]	@ (80000f8 <frame_dummy+0x18>)
 80000ea:	4804      	ldr	r0, [pc, #16]	@ (80000fc <frame_dummy+0x1c>)
 80000ec:	e000      	b.n	80000f0 <frame_dummy+0x10>
 80000ee:	bf00      	nop
 80000f0:	bd10      	pop	{r4, pc}
 80000f2:	46c0      	nop			@ (mov r8, r8)
 80000f4:	00000000 	.word	0x00000000
 80000f8:	20000010 	.word	0x20000010
 80000fc:	08003080 	.word	0x08003080

08000100 <__udivsi3>:
 8000100:	2200      	movs	r2, #0
 8000102:	0843      	lsrs	r3, r0, #1
 8000104:	428b      	cmp	r3, r1
 8000106:	d374      	bcc.n	80001f2 <__udivsi3+0xf2>
 8000108:	0903      	lsrs	r3, r0, #4
 800010a:	428b      	cmp	r3, r1
 800010c:	d35f      	bcc.n	80001ce <__udivsi3+0xce>
 800010e:	0a03      	lsrs	r3, r0, #8
 8000110:	428b      	cmp	r3, r1
 8000112:	d344      	bcc.n	800019e <__udivsi3+0x9e>
 8000114:	0b03      	lsrs	r3, r0, #12
 8000116:	428b      	cmp	r3, r1
 8000118:	d328      	bcc.n	800016c <__udivsi3+0x6c>
 800011a:	0c03      	lsrs	r3, r0, #16
 800011c:	428b      	cmp	r3, r1
 800011e:	d30d      	bcc.n	800013c <__udivsi3+0x3c>
 8000120:	22ff      	movs	r2, #255	@ 0xff
 8000122:	0209      	lsls	r1, r1, #8
 8000124:	ba12      	rev	r2, r2
 8000126:	0c03      	lsrs	r3, r0, #16
 8000128:	428b      	cmp	r3, r1
 800012a:	d302      	bcc.n	8000132 <__udivsi3+0x32>
 800012c:	1212      	asrs	r2, r2, #8
 800012e:	0209      	lsls	r1, r1, #8
 8000130:	d065      	beq.n	80001fe <__udivsi3+0xfe>
 8000132:	0b03      	lsrs	r3, r0, #12
 8000134:	428b      	cmp	r3, r1
 8000136:	d319      	bcc.n	800016c <__udivsi3+0x6c>
 8000138:	e000      	b.n	800013c <__udivsi3+0x3c>
 800013a:	0a09      	lsrs	r1, r1, #8
 800013c:	0bc3      	lsrs	r3, r0, #15
 800013e:	428b      	cmp	r3, r1
 8000140:	d301      	bcc.n	8000146 <__udivsi3+0x46>
 8000142:	03cb      	lsls	r3, r1, #15
 8000144:	1ac0      	subs	r0, r0, r3
 8000146:	4152      	adcs	r2, r2
 8000148:	0b83      	lsrs	r3, r0, #14
 800014a:	428b      	cmp	r3, r1
 800014c:	d301      	bcc.n	8000152 <__udivsi3+0x52>
 800014e:	038b      	lsls	r3, r1, #14
 8000150:	1ac0      	subs	r0, r0, r3
 8000152:	4152      	adcs	r2, r2
 8000154:	0b43      	lsrs	r3, r0, #13
 8000156:	428b      	cmp	r3, r1
 8000158:	d301      	bcc.n	800015e <__udivsi3+0x5e>
 800015a:	034b      	lsls	r3, r1, #13
 800015c:	1ac0      	subs	r0, r0, r3
 800015e:	4152      	adcs	r2, r2
 8000160:	0b03      	lsrs	r3, r0, #12
 8000162:	428b      	cmp	r3, r1
 8000164:	d301      	bcc.n	800016a <__udivsi3+0x6a>
 8000166:	030b      	lsls	r3, r1, #12
 8000168:	1ac0      	subs	r0, r0, r3
 800016a:	4152      	adcs	r2, r2
 800016c:	0ac3      	lsrs	r3, r0, #11
 800016e:	428b      	cmp	r3, r1
 8000170:	d301      	bcc.n	8000176 <__udivsi3+0x76>
 8000172:	02cb      	lsls	r3, r1, #11
 8000174:	1ac0      	subs	r0, r0, r3
 8000176:	4152      	adcs	r2, r2
 8000178:	0a83      	lsrs	r3, r0, #10
 800017a:	428b      	cmp	r3, r1
 800017c:	d301      	bcc.n	8000182 <__udivsi3+0x82>
 800017e:	028b      	lsls	r3, r1, #10
 8000180:	1ac0      	subs	r0, r0, r3
 8000182:	4152      	adcs	r2, r2
 8000184:	0a43      	lsrs	r3, r0, #9
 8000186:	428b      	cmp	r3, r1
 8000188:	d301      	bcc.n	800018e <__udivsi3+0x8e>
 800018a:	024b      	lsls	r3, r1, #9
 800018c:	1ac0      	subs	r0, r0, r3
 800018e:	4152      	adcs	r2, r2
 8000190:	0a03      	lsrs	r3, r0, #8
 8000192:	428b      	cmp	r3, r1
 8000194:	d301      	bcc.n	800019a <__udivsi3+0x9a>
 8000196:	020b      	lsls	r3, r1, #8
 8000198:	1ac0      	subs	r0, r0, r3
 800019a:	4152      	adcs	r2, r2
 800019c:	d2cd      	bcs.n	800013a <__udivsi3+0x3a>
 800019e:	09c3      	lsrs	r3, r0, #7
 80001a0:	428b      	cmp	r3, r1
 80001a2:	d301      	bcc.n	80001a8 <__udivsi3+0xa8>
 80001a4:	01cb      	lsls	r3, r1, #7
 80001a6:	1ac0      	subs	r0, r0, r3
 80001a8:	4152      	adcs	r2, r2
 80001aa:	0983      	lsrs	r3, r0, #6
 80001ac:	428b      	cmp	r3, r1
 80001ae:	d301      	bcc.n	80001b4 <__udivsi3+0xb4>
 80001b0:	018b      	lsls	r3, r1, #6
 80001b2:	1ac0      	subs	r0, r0, r3
 80001b4:	4152      	adcs	r2, r2
 80001b6:	0943      	lsrs	r3, r0, #5
 80001b8:	428b      	cmp	r3, r1
 80001ba:	d301      	bcc.n	80001c0 <__udivsi3+0xc0>
 80001bc:	014b      	lsls	r3, r1, #5
 80001be:	1ac0      	subs	r0, r0, r3
 80001c0:	4152      	adcs	r2, r2
 80001c2:	0903      	lsrs	r3, r0, #4
 80001c4:	428b      	cmp	r3, r1
 80001c6:	d301      	bcc.n	80001cc <__udivsi3+0xcc>
 80001c8:	010b      	lsls	r3, r1, #4
 80001ca:	1ac0      	subs	r0, r0, r3
 80001cc:	4152      	adcs	r2, r2
 80001ce:	08c3      	lsrs	r3, r0, #3
 80001d0:	428b      	cmp	r3, r1
 80001d2:	d301      	bcc.n	80001d8 <__udivsi3+0xd8>
 80001d4:	00cb      	lsls	r3, r1, #3
 80001d6:	1ac0      	subs	r0, r0, r3
 80001d8:	4152      	adcs	r2, r2
 80001da:	0883      	lsrs	r3, r0, #2
 80001dc:	428b      	cmp	r3, r1
 80001de:	d301      	bcc.n	80001e4 <__udivsi3+0xe4>
 80001e0:	008b      	lsls	r3, r1, #2
 80001e2:	1ac0      	subs	r0, r0, r3
 80001e4:	4152      	adcs	r2, r2
 80001e6:	0843      	lsrs	r3, r0, #1
 80001e8:	428b      	cmp	r3, r1
 80001ea:	d301      	bcc.n	80001f0 <__udivsi3+0xf0>
 80001ec:	004b      	lsls	r3, r1, #1
 80001ee:	1ac0      	subs	r0, r0, r3
 80001f0:	4152      	adcs	r2, r2
 80001f2:	1a41      	subs	r1, r0, r1
 80001f4:	d200      	bcs.n	80001f8 <__udivsi3+0xf8>
 80001f6:	4601      	mov	r1, r0
 80001f8:	4152      	adcs	r2, r2
 80001fa:	4610      	mov	r0, r2
 80001fc:	4770      	bx	lr
 80001fe:	e7ff      	b.n	8000200 <__udivsi3+0x100>
 8000200:	b501      	push	{r0, lr}
 8000202:	2000      	movs	r0, #0
 8000204:	f000 f806 	bl	8000214 <__aeabi_idiv0>
 8000208:	bd02      	pop	{r1, pc}
 800020a:	46c0      	nop			@ (mov r8, r8)

0800020c <__aeabi_uidivmod>:
 800020c:	2900      	cmp	r1, #0
 800020e:	d0f7      	beq.n	8000200 <__udivsi3+0x100>
 8000210:	e776      	b.n	8000100 <__udivsi3>
 8000212:	4770      	bx	lr

08000214 <__aeabi_idiv0>:
 8000214:	4770      	bx	lr
 8000216:	46c0      	nop			@ (mov r8, r8)

08000218 <DMA1_Channel1_IRQ>:
extern DMA_HandleTypeDef hdma_tim3_ch2;

DShotStruct DShot;
PWMInputStruct PWMInput;

void DMA1_Channel1_IRQ (DMA_HandleTypeDef *hdma) {
 8000218:	b590      	push	{r4, r7, lr}
 800021a:	b089      	sub	sp, #36	@ 0x24
 800021c:	af00      	add	r7, sp, #0
 800021e:	6078      	str	r0, [r7, #4]
	uint32_t flag_it = DMA1->ISR;
 8000220:	4b98      	ldr	r3, [pc, #608]	@ (8000484 <DMA1_Channel1_IRQ+0x26c>)
 8000222:	681b      	ldr	r3, [r3, #0]
 8000224:	617b      	str	r3, [r7, #20]
	uint32_t source_it = hdma->Instance->CCR;
 8000226:	687b      	ldr	r3, [r7, #4]
 8000228:	681b      	ldr	r3, [r3, #0]
 800022a:	681b      	ldr	r3, [r3, #0]
 800022c:	613b      	str	r3, [r7, #16]
	uint16_t value;
	uint16_t crc_d;
	uint16_t crc_p;
  	uint8_t i;
  	uint16_t dif_min = 0xFFFF;
 800022e:	2318      	movs	r3, #24
 8000230:	18fb      	adds	r3, r7, r3
 8000232:	2201      	movs	r2, #1
 8000234:	4252      	negs	r2, r2
 8000236:	801a      	strh	r2, [r3, #0]
  	uint8_t D;

	if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC)))
 8000238:	687b      	ldr	r3, [r7, #4]
 800023a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800023c:	221c      	movs	r2, #28
 800023e:	4013      	ands	r3, r2
 8000240:	2202      	movs	r2, #2
 8000242:	409a      	lsls	r2, r3
 8000244:	0013      	movs	r3, r2
 8000246:	697a      	ldr	r2, [r7, #20]
 8000248:	4013      	ands	r3, r2
 800024a:	d100      	bne.n	800024e <DMA1_Channel1_IRQ+0x36>
 800024c:	e117      	b.n	800047e <DMA1_Channel1_IRQ+0x266>
 800024e:	693b      	ldr	r3, [r7, #16]
 8000250:	2202      	movs	r2, #2
 8000252:	4013      	ands	r3, r2
 8000254:	d100      	bne.n	8000258 <DMA1_Channel1_IRQ+0x40>
 8000256:	e112      	b.n	800047e <DMA1_Channel1_IRQ+0x266>
	  {
	      if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8000258:	687b      	ldr	r3, [r7, #4]
 800025a:	681b      	ldr	r3, [r3, #0]
 800025c:	681b      	ldr	r3, [r3, #0]
 800025e:	2220      	movs	r2, #32
 8000260:	4013      	ands	r3, r2
 8000262:	d10b      	bne.n	800027c <DMA1_Channel1_IRQ+0x64>
	      {
	        // Disable the transfer complete and error interrupt
	        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
 8000264:	687b      	ldr	r3, [r7, #4]
 8000266:	681b      	ldr	r3, [r3, #0]
 8000268:	681a      	ldr	r2, [r3, #0]
 800026a:	687b      	ldr	r3, [r7, #4]
 800026c:	681b      	ldr	r3, [r3, #0]
 800026e:	210a      	movs	r1, #10
 8000270:	438a      	bics	r2, r1
 8000272:	601a      	str	r2, [r3, #0]

	        // Change the DMA state
	        hdma->State = HAL_DMA_STATE_READY;
 8000274:	687b      	ldr	r3, [r7, #4]
 8000276:	2225      	movs	r2, #37	@ 0x25
 8000278:	2101      	movs	r1, #1
 800027a:	5499      	strb	r1, [r3, r2]
	      }
	      // Clear the transfer complete flag
	      __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
 800027c:	4b81      	ldr	r3, [pc, #516]	@ (8000484 <DMA1_Channel1_IRQ+0x26c>)
 800027e:	6859      	ldr	r1, [r3, #4]
 8000280:	687b      	ldr	r3, [r7, #4]
 8000282:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8000284:	221c      	movs	r2, #28
 8000286:	4013      	ands	r3, r2
 8000288:	2202      	movs	r2, #2
 800028a:	409a      	lsls	r2, r3
 800028c:	4b7d      	ldr	r3, [pc, #500]	@ (8000484 <DMA1_Channel1_IRQ+0x26c>)
 800028e:	430a      	orrs	r2, r1
 8000290:	605a      	str	r2, [r3, #4]

	      // Process Unlocked
	      __HAL_UNLOCK(hdma);
 8000292:	687b      	ldr	r3, [r7, #4]
 8000294:	2224      	movs	r2, #36	@ 0x24
 8000296:	2100      	movs	r1, #0
 8000298:	5499      	strb	r1, [r3, r2]



	  	TIM3->CNT = 0;
 800029a:	4b7b      	ldr	r3, [pc, #492]	@ (8000488 <DMA1_Channel1_IRQ+0x270>)
 800029c:	2200      	movs	r2, #0
 800029e:	625a      	str	r2, [r3, #36]	@ 0x24

	  	// Check Packet
		for (i=0; i<16; i++) {
 80002a0:	231b      	movs	r3, #27
 80002a2:	18fb      	adds	r3, r7, r3
 80002a4:	2200      	movs	r2, #0
 80002a6:	701a      	strb	r2, [r3, #0]
 80002a8:	e062      	b.n	8000370 <DMA1_Channel1_IRQ+0x158>
			DShot.Dif[i] = DShot.T1[i]-DShot.T2[i];
 80002aa:	201b      	movs	r0, #27
 80002ac:	183b      	adds	r3, r7, r0
 80002ae:	781b      	ldrb	r3, [r3, #0]
 80002b0:	4a76      	ldr	r2, [pc, #472]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 80002b2:	009b      	lsls	r3, r3, #2
 80002b4:	18d3      	adds	r3, r2, r3
 80002b6:	3304      	adds	r3, #4
 80002b8:	681b      	ldr	r3, [r3, #0]
 80002ba:	b299      	uxth	r1, r3
 80002bc:	183b      	adds	r3, r7, r0
 80002be:	781b      	ldrb	r3, [r3, #0]
 80002c0:	4a72      	ldr	r2, [pc, #456]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 80002c2:	3310      	adds	r3, #16
 80002c4:	009b      	lsls	r3, r3, #2
 80002c6:	18d3      	adds	r3, r2, r3
 80002c8:	3304      	adds	r3, #4
 80002ca:	681b      	ldr	r3, [r3, #0]
 80002cc:	b29a      	uxth	r2, r3
 80002ce:	183b      	adds	r3, r7, r0
 80002d0:	781b      	ldrb	r3, [r3, #0]
 80002d2:	1a8a      	subs	r2, r1, r2
 80002d4:	b291      	uxth	r1, r2
 80002d6:	4a6d      	ldr	r2, [pc, #436]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 80002d8:	3340      	adds	r3, #64	@ 0x40
 80002da:	005b      	lsls	r3, r3, #1
 80002dc:	18d3      	adds	r3, r2, r3
 80002de:	3304      	adds	r3, #4
 80002e0:	1c0a      	adds	r2, r1, #0
 80002e2:	801a      	strh	r2, [r3, #0]
			if ((DShot.Type == DShot_Auto)) {
 80002e4:	4b69      	ldr	r3, [pc, #420]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 80002e6:	789b      	ldrb	r3, [r3, #2]
 80002e8:	2b03      	cmp	r3, #3
 80002ea:	d116      	bne.n	800031a <DMA1_Channel1_IRQ+0x102>
				if (DShot.Dif[i] < dif_min) {
 80002ec:	183b      	adds	r3, r7, r0
 80002ee:	781b      	ldrb	r3, [r3, #0]
 80002f0:	4a66      	ldr	r2, [pc, #408]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 80002f2:	3340      	adds	r3, #64	@ 0x40
 80002f4:	005b      	lsls	r3, r3, #1
 80002f6:	18d3      	adds	r3, r2, r3
 80002f8:	3304      	adds	r3, #4
 80002fa:	881b      	ldrh	r3, [r3, #0]
 80002fc:	2118      	movs	r1, #24
 80002fe:	187a      	adds	r2, r7, r1
 8000300:	8812      	ldrh	r2, [r2, #0]
 8000302:	429a      	cmp	r2, r3
 8000304:	d909      	bls.n	800031a <DMA1_Channel1_IRQ+0x102>
					dif_min = DShot.Dif[i];
 8000306:	183b      	adds	r3, r7, r0
 8000308:	781a      	ldrb	r2, [r3, #0]
 800030a:	187b      	adds	r3, r7, r1
 800030c:	495f      	ldr	r1, [pc, #380]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 800030e:	3240      	adds	r2, #64	@ 0x40
 8000310:	0052      	lsls	r2, r2, #1
 8000312:	188a      	adds	r2, r1, r2
 8000314:	3204      	adds	r2, #4
 8000316:	8812      	ldrh	r2, [r2, #0]
 8000318:	801a      	strh	r2, [r3, #0]
				}
			}
			if (DShot.Dif[i] > 64000) {
 800031a:	231b      	movs	r3, #27
 800031c:	18fb      	adds	r3, r7, r3
 800031e:	781b      	ldrb	r3, [r3, #0]
 8000320:	4a5a      	ldr	r2, [pc, #360]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 8000322:	3340      	adds	r3, #64	@ 0x40
 8000324:	005b      	lsls	r3, r3, #1
 8000326:	18d3      	adds	r3, r2, r3
 8000328:	3304      	adds	r3, #4
 800032a:	881a      	ldrh	r2, [r3, #0]
 800032c:	23fa      	movs	r3, #250	@ 0xfa
 800032e:	021b      	lsls	r3, r3, #8
 8000330:	429a      	cmp	r2, r3
 8000332:	d917      	bls.n	8000364 <DMA1_Channel1_IRQ+0x14c>
				DShot.Restart_Counter++;
 8000334:	4b55      	ldr	r3, [pc, #340]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 8000336:	22a6      	movs	r2, #166	@ 0xa6
 8000338:	5c9b      	ldrb	r3, [r3, r2]
 800033a:	3301      	adds	r3, #1
 800033c:	b2d9      	uxtb	r1, r3
 800033e:	4b53      	ldr	r3, [pc, #332]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 8000340:	22a6      	movs	r2, #166	@ 0xa6
 8000342:	5499      	strb	r1, [r3, r2]
				if (DShot.Restart_Counter < 100) {
 8000344:	4b51      	ldr	r3, [pc, #324]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 8000346:	22a6      	movs	r2, #166	@ 0xa6
 8000348:	5c9b      	ldrb	r3, [r3, r2]
 800034a:	2b63      	cmp	r3, #99	@ 0x63
 800034c:	d807      	bhi.n	800035e <DMA1_Channel1_IRQ+0x146>
					Dshot_DeInit();
 800034e:	f000 f903 	bl	8000558 <Dshot_DeInit>
					Dshot_Init(DShot.Type);
 8000352:	4b4e      	ldr	r3, [pc, #312]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 8000354:	789b      	ldrb	r3, [r3, #2]
 8000356:	0018      	movs	r0, r3
 8000358:	f000 f89a 	bl	8000490 <Dshot_Init>
				} else {
					Dshot_DeInit();
				}
				return;
 800035c:	e08f      	b.n	800047e <DMA1_Channel1_IRQ+0x266>
					Dshot_DeInit();
 800035e:	f000 f8fb 	bl	8000558 <Dshot_DeInit>
				return;
 8000362:	e08c      	b.n	800047e <DMA1_Channel1_IRQ+0x266>
		for (i=0; i<16; i++) {
 8000364:	211b      	movs	r1, #27
 8000366:	187b      	adds	r3, r7, r1
 8000368:	781a      	ldrb	r2, [r3, #0]
 800036a:	187b      	adds	r3, r7, r1
 800036c:	3201      	adds	r2, #1
 800036e:	701a      	strb	r2, [r3, #0]
 8000370:	231b      	movs	r3, #27
 8000372:	18fb      	adds	r3, r7, r3
 8000374:	781b      	ldrb	r3, [r3, #0]
 8000376:	2b0f      	cmp	r3, #15
 8000378:	d997      	bls.n	80002aa <DMA1_Channel1_IRQ+0x92>
			}
		}

		// If DShot_Auto then autodetect 'TDif'
		if (DShot.Type == DShot_Auto) {
 800037a:	4b44      	ldr	r3, [pc, #272]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 800037c:	789b      	ldrb	r3, [r3, #2]
 800037e:	2b03      	cmp	r3, #3
 8000380:	d10b      	bne.n	800039a <DMA1_Channel1_IRQ+0x182>
			DShot.TDif = dif_min + (dif_min / 2);
 8000382:	2118      	movs	r1, #24
 8000384:	187b      	adds	r3, r7, r1
 8000386:	881b      	ldrh	r3, [r3, #0]
 8000388:	085b      	lsrs	r3, r3, #1
 800038a:	b29a      	uxth	r2, r3
 800038c:	187b      	adds	r3, r7, r1
 800038e:	881b      	ldrh	r3, [r3, #0]
 8000390:	18d3      	adds	r3, r2, r3
 8000392:	b299      	uxth	r1, r3
 8000394:	4b3d      	ldr	r3, [pc, #244]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 8000396:	22a4      	movs	r2, #164	@ 0xa4
 8000398:	5299      	strh	r1, [r3, r2]
		}


	  	value = 0;
 800039a:	231e      	movs	r3, #30
 800039c:	18fb      	adds	r3, r7, r3
 800039e:	2200      	movs	r2, #0
 80003a0:	801a      	strh	r2, [r3, #0]
	  	crc_p = 0;
 80003a2:	231c      	movs	r3, #28
 80003a4:	18fb      	adds	r3, r7, r3
 80003a6:	2200      	movs	r2, #0
 80003a8:	801a      	strh	r2, [r3, #0]
	  	for (i=0; i<16; i++) {
 80003aa:	231b      	movs	r3, #27
 80003ac:	18fb      	adds	r3, r7, r3
 80003ae:	2200      	movs	r2, #0
 80003b0:	701a      	strb	r2, [r3, #0]
 80003b2:	e03b      	b.n	800042c <DMA1_Channel1_IRQ+0x214>
	  		D = (DShot.Dif[i] > DShot.TDif);
 80003b4:	201b      	movs	r0, #27
 80003b6:	183b      	adds	r3, r7, r0
 80003b8:	781b      	ldrb	r3, [r3, #0]
 80003ba:	4a34      	ldr	r2, [pc, #208]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 80003bc:	3340      	adds	r3, #64	@ 0x40
 80003be:	005b      	lsls	r3, r3, #1
 80003c0:	18d3      	adds	r3, r2, r3
 80003c2:	3304      	adds	r3, #4
 80003c4:	881b      	ldrh	r3, [r3, #0]
 80003c6:	4a31      	ldr	r2, [pc, #196]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 80003c8:	21a4      	movs	r1, #164	@ 0xa4
 80003ca:	5a52      	ldrh	r2, [r2, r1]
 80003cc:	429a      	cmp	r2, r3
 80003ce:	419b      	sbcs	r3, r3
 80003d0:	425b      	negs	r3, r3
 80003d2:	b2da      	uxtb	r2, r3
 80003d4:	210d      	movs	r1, #13
 80003d6:	187b      	adds	r3, r7, r1
 80003d8:	701a      	strb	r2, [r3, #0]

	  		// Calculate value
	  		if (i <= 11) {
 80003da:	183b      	adds	r3, r7, r0
 80003dc:	781b      	ldrb	r3, [r3, #0]
 80003de:	2b0b      	cmp	r3, #11
 80003e0:	d80c      	bhi.n	80003fc <DMA1_Channel1_IRQ+0x1e4>
	  			value = (value << 1) | D;
 80003e2:	201e      	movs	r0, #30
 80003e4:	183b      	adds	r3, r7, r0
 80003e6:	881b      	ldrh	r3, [r3, #0]
 80003e8:	005b      	lsls	r3, r3, #1
 80003ea:	b21a      	sxth	r2, r3
 80003ec:	187b      	adds	r3, r7, r1
 80003ee:	781b      	ldrb	r3, [r3, #0]
 80003f0:	b21b      	sxth	r3, r3
 80003f2:	4313      	orrs	r3, r2
 80003f4:	b21a      	sxth	r2, r3
 80003f6:	183b      	adds	r3, r7, r0
 80003f8:	801a      	strh	r2, [r3, #0]
 80003fa:	e011      	b.n	8000420 <DMA1_Channel1_IRQ+0x208>
	  		} else {
	  			if (i > 11) { // Get CRC from packet
 80003fc:	231b      	movs	r3, #27
 80003fe:	18fb      	adds	r3, r7, r3
 8000400:	781b      	ldrb	r3, [r3, #0]
 8000402:	2b0b      	cmp	r3, #11
 8000404:	d90c      	bls.n	8000420 <DMA1_Channel1_IRQ+0x208>
	  				crc_p = (crc_p << 1) | D;
 8000406:	211c      	movs	r1, #28
 8000408:	187b      	adds	r3, r7, r1
 800040a:	881b      	ldrh	r3, [r3, #0]
 800040c:	005b      	lsls	r3, r3, #1
 800040e:	b21a      	sxth	r2, r3
 8000410:	230d      	movs	r3, #13
 8000412:	18fb      	adds	r3, r7, r3
 8000414:	781b      	ldrb	r3, [r3, #0]
 8000416:	b21b      	sxth	r3, r3
 8000418:	4313      	orrs	r3, r2
 800041a:	b21a      	sxth	r2, r3
 800041c:	187b      	adds	r3, r7, r1
 800041e:	801a      	strh	r2, [r3, #0]
	  	for (i=0; i<16; i++) {
 8000420:	211b      	movs	r1, #27
 8000422:	187b      	adds	r3, r7, r1
 8000424:	781a      	ldrb	r2, [r3, #0]
 8000426:	187b      	adds	r3, r7, r1
 8000428:	3201      	adds	r2, #1
 800042a:	701a      	strb	r2, [r3, #0]
 800042c:	231b      	movs	r3, #27
 800042e:	18fb      	adds	r3, r7, r3
 8000430:	781b      	ldrb	r3, [r3, #0]
 8000432:	2b0f      	cmp	r3, #15
 8000434:	d9be      	bls.n	80003b4 <DMA1_Channel1_IRQ+0x19c>
	  		}

	  	}

	  	// Calculate CRC
	  	crc_d = (value ^ (value >> 4) ^ (value >> 8)) & 0xF;
 8000436:	201e      	movs	r0, #30
 8000438:	183b      	adds	r3, r7, r0
 800043a:	881b      	ldrh	r3, [r3, #0]
 800043c:	091b      	lsrs	r3, r3, #4
 800043e:	b29a      	uxth	r2, r3
 8000440:	183b      	adds	r3, r7, r0
 8000442:	881b      	ldrh	r3, [r3, #0]
 8000444:	4053      	eors	r3, r2
 8000446:	b29a      	uxth	r2, r3
 8000448:	183b      	adds	r3, r7, r0
 800044a:	881b      	ldrh	r3, [r3, #0]
 800044c:	0a1b      	lsrs	r3, r3, #8
 800044e:	b29b      	uxth	r3, r3
 8000450:	4053      	eors	r3, r2
 8000452:	b29a      	uxth	r2, r3
 8000454:	240e      	movs	r4, #14
 8000456:	193b      	adds	r3, r7, r4
 8000458:	210f      	movs	r1, #15
 800045a:	400a      	ands	r2, r1
 800045c:	801a      	strh	r2, [r3, #0]
  		// Check CRC
  		if (crc_d == crc_p ) {
 800045e:	193a      	adds	r2, r7, r4
 8000460:	231c      	movs	r3, #28
 8000462:	18fb      	adds	r3, r7, r3
 8000464:	8812      	ldrh	r2, [r2, #0]
 8000466:	881b      	ldrh	r3, [r3, #0]
 8000468:	429a      	cmp	r2, r3
 800046a:	d108      	bne.n	800047e <DMA1_Channel1_IRQ+0x266>
  			DShot.Value = (value >> 1) & 0x7FF;
 800046c:	183b      	adds	r3, r7, r0
 800046e:	881b      	ldrh	r3, [r3, #0]
 8000470:	085b      	lsrs	r3, r3, #1
 8000472:	b29b      	uxth	r3, r3
 8000474:	055b      	lsls	r3, r3, #21
 8000476:	0d5b      	lsrs	r3, r3, #21
 8000478:	b29a      	uxth	r2, r3
 800047a:	4b04      	ldr	r3, [pc, #16]	@ (800048c <DMA1_Channel1_IRQ+0x274>)
 800047c:	801a      	strh	r2, [r3, #0]
  		}

	  }
}
 800047e:	46bd      	mov	sp, r7
 8000480:	b009      	add	sp, #36	@ 0x24
 8000482:	bd90      	pop	{r4, r7, pc}
 8000484:	40020000 	.word	0x40020000
 8000488:	40000400 	.word	0x40000400
 800048c:	20000028 	.word	0x20000028

08000490 <Dshot_Init>:

void Dshot_Init(uint8_t type) {
 8000490:	b580      	push	{r7, lr}
 8000492:	b082      	sub	sp, #8
 8000494:	af00      	add	r7, sp, #0
 8000496:	0002      	movs	r2, r0
 8000498:	1dfb      	adds	r3, r7, #7
 800049a:	701a      	strb	r2, [r3, #0]

	switch ( type )
 800049c:	1dfb      	adds	r3, r7, #7
 800049e:	781b      	ldrb	r3, [r3, #0]
 80004a0:	2b03      	cmp	r3, #3
 80004a2:	d020      	beq.n	80004e6 <Dshot_Init+0x56>
 80004a4:	dc27      	bgt.n	80004f6 <Dshot_Init+0x66>
 80004a6:	2b02      	cmp	r3, #2
 80004a8:	d015      	beq.n	80004d6 <Dshot_Init+0x46>
 80004aa:	dc24      	bgt.n	80004f6 <Dshot_Init+0x66>
 80004ac:	2b00      	cmp	r3, #0
 80004ae:	d002      	beq.n	80004b6 <Dshot_Init+0x26>
 80004b0:	2b01      	cmp	r3, #1
 80004b2:	d008      	beq.n	80004c6 <Dshot_Init+0x36>
 80004b4:	e01f      	b.n	80004f6 <Dshot_Init+0x66>
	{
	    case DShot_150:
	    	DShot.TDif = DSHOT150_TIM_TRIG;
 80004b6:	4b23      	ldr	r3, [pc, #140]	@ (8000544 <Dshot_Init+0xb4>)
 80004b8:	22a4      	movs	r2, #164	@ 0xa4
 80004ba:	21d5      	movs	r1, #213	@ 0xd5
 80004bc:	5299      	strh	r1, [r3, r2]
	    	DShot.Type = DShot_150;
 80004be:	4b21      	ldr	r3, [pc, #132]	@ (8000544 <Dshot_Init+0xb4>)
 80004c0:	2200      	movs	r2, #0
 80004c2:	709a      	strb	r2, [r3, #2]
	        break;
 80004c4:	e01f      	b.n	8000506 <Dshot_Init+0x76>
	    case DShot_300:
	    	DShot.TDif = DSHOT300_TIM_TRIG;
 80004c6:	4b1f      	ldr	r3, [pc, #124]	@ (8000544 <Dshot_Init+0xb4>)
 80004c8:	22a4      	movs	r2, #164	@ 0xa4
 80004ca:	216a      	movs	r1, #106	@ 0x6a
 80004cc:	5299      	strh	r1, [r3, r2]
	    	DShot.Type = DShot_300;
 80004ce:	4b1d      	ldr	r3, [pc, #116]	@ (8000544 <Dshot_Init+0xb4>)
 80004d0:	2201      	movs	r2, #1
 80004d2:	709a      	strb	r2, [r3, #2]
	        break;
 80004d4:	e017      	b.n	8000506 <Dshot_Init+0x76>
	    case DShot_600:
	    	DShot.TDif = DSHOT600_TIM_TRIG;
 80004d6:	4b1b      	ldr	r3, [pc, #108]	@ (8000544 <Dshot_Init+0xb4>)
 80004d8:	22a4      	movs	r2, #164	@ 0xa4
 80004da:	2135      	movs	r1, #53	@ 0x35
 80004dc:	5299      	strh	r1, [r3, r2]
	    	DShot.Type = DShot_600;
 80004de:	4b19      	ldr	r3, [pc, #100]	@ (8000544 <Dshot_Init+0xb4>)
 80004e0:	2202      	movs	r2, #2
 80004e2:	709a      	strb	r2, [r3, #2]
	        break;
 80004e4:	e00f      	b.n	8000506 <Dshot_Init+0x76>
	    case DShot_Auto:
	    	DShot.TDif = 0;
 80004e6:	4b17      	ldr	r3, [pc, #92]	@ (8000544 <Dshot_Init+0xb4>)
 80004e8:	22a4      	movs	r2, #164	@ 0xa4
 80004ea:	2100      	movs	r1, #0
 80004ec:	5299      	strh	r1, [r3, r2]
	    	DShot.Type = DShot_Auto;
 80004ee:	4b15      	ldr	r3, [pc, #84]	@ (8000544 <Dshot_Init+0xb4>)
 80004f0:	2203      	movs	r2, #3
 80004f2:	709a      	strb	r2, [r3, #2]
	        break;
 80004f4:	e007      	b.n	8000506 <Dshot_Init+0x76>
	    default:
	    	DShot.TDif = 0;
 80004f6:	4b13      	ldr	r3, [pc, #76]	@ (8000544 <Dshot_Init+0xb4>)
 80004f8:	22a4      	movs	r2, #164	@ 0xa4
 80004fa:	2100      	movs	r1, #0
 80004fc:	5299      	strh	r1, [r3, r2]
	    	DShot.Type = DShot_Auto;
 80004fe:	4b11      	ldr	r3, [pc, #68]	@ (8000544 <Dshot_Init+0xb4>)
 8000500:	2203      	movs	r2, #3
 8000502:	709a      	strb	r2, [r3, #2]
	    	break;
 8000504:	46c0      	nop			@ (mov r8, r8)

	}

	htim3.Init.Prescaler = 0;
 8000506:	4b10      	ldr	r3, [pc, #64]	@ (8000548 <Dshot_Init+0xb8>)
 8000508:	2200      	movs	r2, #0
 800050a:	605a      	str	r2, [r3, #4]
	htim3.Init.Period = 20000;
 800050c:	4b0e      	ldr	r3, [pc, #56]	@ (8000548 <Dshot_Init+0xb8>)
 800050e:	4a0f      	ldr	r2, [pc, #60]	@ (800054c <Dshot_Init+0xbc>)
 8000510:	60da      	str	r2, [r3, #12]
	if (HAL_TIM_Base_Init(&htim3) != HAL_OK) {
 8000512:	4b0d      	ldr	r3, [pc, #52]	@ (8000548 <Dshot_Init+0xb8>)
 8000514:	0018      	movs	r0, r3
 8000516:	f001 fce3 	bl	8001ee0 <HAL_TIM_Base_Init>
 800051a:	1e03      	subs	r3, r0, #0
 800051c:	d001      	beq.n	8000522 <Dshot_Init+0x92>
		Error_Handler();
 800051e:	f000 f9c3 	bl	80008a8 <Error_Handler>
	}
	HAL_TIM_IC_Start_DMA(&htim3, TIM_CHANNEL_1, DShot.T1, 16);
 8000522:	4a0b      	ldr	r2, [pc, #44]	@ (8000550 <Dshot_Init+0xc0>)
 8000524:	4808      	ldr	r0, [pc, #32]	@ (8000548 <Dshot_Init+0xb8>)
 8000526:	2310      	movs	r3, #16
 8000528:	2100      	movs	r1, #0
 800052a:	f001 fd91 	bl	8002050 <HAL_TIM_IC_Start_DMA>
	HAL_TIM_IC_Start_DMA(&htim3, TIM_CHANNEL_2, DShot.T2, 16);
 800052e:	4a09      	ldr	r2, [pc, #36]	@ (8000554 <Dshot_Init+0xc4>)
 8000530:	4805      	ldr	r0, [pc, #20]	@ (8000548 <Dshot_Init+0xb8>)
 8000532:	2310      	movs	r3, #16
 8000534:	2104      	movs	r1, #4
 8000536:	f001 fd8b 	bl	8002050 <HAL_TIM_IC_Start_DMA>
}
 800053a:	46c0      	nop			@ (mov r8, r8)
 800053c:	46bd      	mov	sp, r7
 800053e:	b002      	add	sp, #8
 8000540:	bd80      	pop	{r7, pc}
 8000542:	46c0      	nop			@ (mov r8, r8)
 8000544:	20000028 	.word	0x20000028
 8000548:	200000d8 	.word	0x200000d8
 800054c:	00004e20 	.word	0x00004e20
 8000550:	2000002c 	.word	0x2000002c
 8000554:	2000006c 	.word	0x2000006c

08000558 <Dshot_DeInit>:

void Dshot_DeInit(void) {
 8000558:	b580      	push	{r7, lr}
 800055a:	af00      	add	r7, sp, #0
	HAL_TIM_IC_Stop_DMA(&htim3, TIM_CHANNEL_1);
 800055c:	4b06      	ldr	r3, [pc, #24]	@ (8000578 <Dshot_DeInit+0x20>)
 800055e:	2100      	movs	r1, #0
 8000560:	0018      	movs	r0, r3
 8000562:	f001 ff2d 	bl	80023c0 <HAL_TIM_IC_Stop_DMA>
	HAL_TIM_IC_Stop_DMA(&htim3, TIM_CHANNEL_2);
 8000566:	4b04      	ldr	r3, [pc, #16]	@ (8000578 <Dshot_DeInit+0x20>)
 8000568:	2104      	movs	r1, #4
 800056a:	0018      	movs	r0, r3
 800056c:	f001 ff28 	bl	80023c0 <HAL_TIM_IC_Stop_DMA>
}
 8000570:	46c0      	nop			@ (mov r8, r8)
 8000572:	46bd      	mov	sp, r7
 8000574:	bd80      	pop	{r7, pc}
 8000576:	46c0      	nop			@ (mov r8, r8)
 8000578:	200000d8 	.word	0x200000d8

0800057c <TIM3_IRQ>:

uint32_t PWMInput_Get(void) {
	return PWMInput.Value;
}

void TIM3_IRQ(void) {
 800057c:	b580      	push	{r7, lr}
 800057e:	af00      	add	r7, sp, #0
	if (__HAL_TIM_GET_IT_SOURCE(&htim3, TIM_IT_CC1) != RESET)
 8000580:	4b2c      	ldr	r3, [pc, #176]	@ (8000634 <TIM3_IRQ+0xb8>)
 8000582:	681b      	ldr	r3, [r3, #0]
 8000584:	68db      	ldr	r3, [r3, #12]
 8000586:	2202      	movs	r2, #2
 8000588:	4013      	ands	r3, r2
 800058a:	2b02      	cmp	r3, #2
 800058c:	d110      	bne.n	80005b0 <TIM3_IRQ+0x34>
	{
	  if (__HAL_TIM_GET_FLAG(&htim3, TIM_FLAG_CC1) != RESET)
 800058e:	4b29      	ldr	r3, [pc, #164]	@ (8000634 <TIM3_IRQ+0xb8>)
 8000590:	681b      	ldr	r3, [r3, #0]
 8000592:	691b      	ldr	r3, [r3, #16]
 8000594:	2202      	movs	r2, #2
 8000596:	4013      	ands	r3, r2
 8000598:	2b02      	cmp	r3, #2
 800059a:	d104      	bne.n	80005a6 <TIM3_IRQ+0x2a>
	  {
		  __HAL_TIM_CLEAR_FLAG(&htim3, TIM_FLAG_CC1);
 800059c:	4b25      	ldr	r3, [pc, #148]	@ (8000634 <TIM3_IRQ+0xb8>)
 800059e:	681b      	ldr	r3, [r3, #0]
 80005a0:	2203      	movs	r2, #3
 80005a2:	4252      	negs	r2, r2
 80005a4:	611a      	str	r2, [r3, #16]
	  }
	  __HAL_TIM_CLEAR_IT(&htim3, TIM_IT_CC1);
 80005a6:	4b23      	ldr	r3, [pc, #140]	@ (8000634 <TIM3_IRQ+0xb8>)
 80005a8:	681b      	ldr	r3, [r3, #0]
 80005aa:	2203      	movs	r2, #3
 80005ac:	4252      	negs	r2, r2
 80005ae:	611a      	str	r2, [r3, #16]
	}

	if (__HAL_TIM_GET_IT_SOURCE(&htim3, TIM_IT_CC2) != RESET)
 80005b0:	4b20      	ldr	r3, [pc, #128]	@ (8000634 <TIM3_IRQ+0xb8>)
 80005b2:	681b      	ldr	r3, [r3, #0]
 80005b4:	68db      	ldr	r3, [r3, #12]
 80005b6:	2204      	movs	r2, #4
 80005b8:	4013      	ands	r3, r2
 80005ba:	2b04      	cmp	r3, #4
 80005bc:	d11e      	bne.n	80005fc <TIM3_IRQ+0x80>
	{
		if (__HAL_TIM_GET_FLAG(&htim3, TIM_FLAG_CC2) != RESET)
 80005be:	4b1d      	ldr	r3, [pc, #116]	@ (8000634 <TIM3_IRQ+0xb8>)
 80005c0:	681b      	ldr	r3, [r3, #0]
 80005c2:	691b      	ldr	r3, [r3, #16]
 80005c4:	2204      	movs	r2, #4
 80005c6:	4013      	ands	r3, r2
 80005c8:	2b04      	cmp	r3, #4
 80005ca:	d112      	bne.n	80005f2 <TIM3_IRQ+0x76>
		{
			__HAL_TIM_CLEAR_FLAG(&htim3, TIM_FLAG_CC2);
 80005cc:	4b19      	ldr	r3, [pc, #100]	@ (8000634 <TIM3_IRQ+0xb8>)
 80005ce:	681b      	ldr	r3, [r3, #0]
 80005d0:	2205      	movs	r2, #5
 80005d2:	4252      	negs	r2, r2
 80005d4:	611a      	str	r2, [r3, #16]

			PWMInput.Value = HAL_TIM_ReadCapturedValue(&htim3, TIM_CHANNEL_1);
 80005d6:	4b17      	ldr	r3, [pc, #92]	@ (8000634 <TIM3_IRQ+0xb8>)
 80005d8:	2100      	movs	r1, #0
 80005da:	0018      	movs	r0, r3
 80005dc:	f002 f93e 	bl	800285c <HAL_TIM_ReadCapturedValue>
 80005e0:	0002      	movs	r2, r0
 80005e2:	4b15      	ldr	r3, [pc, #84]	@ (8000638 <TIM3_IRQ+0xbc>)
 80005e4:	601a      	str	r2, [r3, #0]

			TIM3->CNT = 0;
 80005e6:	4b15      	ldr	r3, [pc, #84]	@ (800063c <TIM3_IRQ+0xc0>)
 80005e8:	2200      	movs	r2, #0
 80005ea:	625a      	str	r2, [r3, #36]	@ 0x24
	        PWMInput.OverCaptureCounter = 0;
 80005ec:	4b12      	ldr	r3, [pc, #72]	@ (8000638 <TIM3_IRQ+0xbc>)
 80005ee:	2200      	movs	r2, #0
 80005f0:	605a      	str	r2, [r3, #4]
		}
		__HAL_TIM_CLEAR_IT(&htim3, TIM_IT_CC2);
 80005f2:	4b10      	ldr	r3, [pc, #64]	@ (8000634 <TIM3_IRQ+0xb8>)
 80005f4:	681b      	ldr	r3, [r3, #0]
 80005f6:	2205      	movs	r2, #5
 80005f8:	4252      	negs	r2, r2
 80005fa:	611a      	str	r2, [r3, #16]
	 }

	if (__HAL_TIM_GET_IT_SOURCE(&htim3, TIM_IT_UPDATE) != RESET)
 80005fc:	4b0d      	ldr	r3, [pc, #52]	@ (8000634 <TIM3_IRQ+0xb8>)
 80005fe:	681b      	ldr	r3, [r3, #0]
 8000600:	68db      	ldr	r3, [r3, #12]
 8000602:	2201      	movs	r2, #1
 8000604:	4013      	ands	r3, r2
 8000606:	2b01      	cmp	r3, #1
 8000608:	d111      	bne.n	800062e <TIM3_IRQ+0xb2>
	{
		__HAL_TIM_CLEAR_IT(&htim3, TIM_IT_UPDATE);
 800060a:	4b0a      	ldr	r3, [pc, #40]	@ (8000634 <TIM3_IRQ+0xb8>)
 800060c:	681b      	ldr	r3, [r3, #0]
 800060e:	2202      	movs	r2, #2
 8000610:	4252      	negs	r2, r2
 8000612:	611a      	str	r2, [r3, #16]

		if (PWMInput.OverCaptureCounter > 3) {
 8000614:	4b08      	ldr	r3, [pc, #32]	@ (8000638 <TIM3_IRQ+0xbc>)
 8000616:	685b      	ldr	r3, [r3, #4]
 8000618:	2b03      	cmp	r3, #3
 800061a:	d903      	bls.n	8000624 <TIM3_IRQ+0xa8>
			PWMInput.Value = 0;
 800061c:	4b06      	ldr	r3, [pc, #24]	@ (8000638 <TIM3_IRQ+0xbc>)
 800061e:	2200      	movs	r2, #0
 8000620:	601a      	str	r2, [r3, #0]
		} else {
			PWMInput.OverCaptureCounter++;
		}

	}
}
 8000622:	e004      	b.n	800062e <TIM3_IRQ+0xb2>
			PWMInput.OverCaptureCounter++;
 8000624:	4b04      	ldr	r3, [pc, #16]	@ (8000638 <TIM3_IRQ+0xbc>)
 8000626:	685b      	ldr	r3, [r3, #4]
 8000628:	1c5a      	adds	r2, r3, #1
 800062a:	4b03      	ldr	r3, [pc, #12]	@ (8000638 <TIM3_IRQ+0xbc>)
 800062c:	605a      	str	r2, [r3, #4]
}
 800062e:	46c0      	nop			@ (mov r8, r8)
 8000630:	46bd      	mov	sp, r7
 8000632:	bd80      	pop	{r7, pc}
 8000634:	200000d8 	.word	0x200000d8
 8000638:	200000d0 	.word	0x200000d0
 800063c:	40000400 	.word	0x40000400

08000640 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8000640:	b580      	push	{r7, lr}
 8000642:	af00      	add	r7, sp, #0
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8000644:	f000 fa7c 	bl	8000b40 <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 8000648:	f000 f80b 	bl	8000662 <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 800064c:	f000 f916 	bl	800087c <MX_GPIO_Init>
  MX_DMA_Init();
 8000650:	f000 f8ee 	bl	8000830 <MX_DMA_Init>
  MX_TIM3_Init();
 8000654:	f000 f860 	bl	8000718 <MX_TIM3_Init>
  /* USER CODE BEGIN 2 */

  User_Init();
 8000658:	f000 fa37 	bl	8000aca <User_Init>

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
  {
	  User_MainLoop();
 800065c:	f000 fa3d 	bl	8000ada <User_MainLoop>
 8000660:	e7fc      	b.n	800065c <main+0x1c>

08000662 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8000662:	b590      	push	{r4, r7, lr}
 8000664:	b093      	sub	sp, #76	@ 0x4c
 8000666:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8000668:	2414      	movs	r4, #20
 800066a:	193b      	adds	r3, r7, r4
 800066c:	0018      	movs	r0, r3
 800066e:	2334      	movs	r3, #52	@ 0x34
 8000670:	001a      	movs	r2, r3
 8000672:	2100      	movs	r1, #0
 8000674:	f002 fcd8 	bl	8003028 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8000678:	1d3b      	adds	r3, r7, #4
 800067a:	0018      	movs	r0, r3
 800067c:	2310      	movs	r3, #16
 800067e:	001a      	movs	r2, r3
 8000680:	2100      	movs	r1, #0
 8000682:	f002 fcd1 	bl	8003028 <memset>

  /** Configure the main internal regulator output voltage
  */
  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
 8000686:	2380      	movs	r3, #128	@ 0x80
 8000688:	009b      	lsls	r3, r3, #2
 800068a:	0018      	movs	r0, r3
 800068c:	f000 ff4e 	bl	800152c <HAL_PWREx_ControlVoltageScaling>

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8000690:	193b      	adds	r3, r7, r4
 8000692:	2202      	movs	r2, #2
 8000694:	601a      	str	r2, [r3, #0]
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8000696:	193b      	adds	r3, r7, r4
 8000698:	2280      	movs	r2, #128	@ 0x80
 800069a:	0052      	lsls	r2, r2, #1
 800069c:	60da      	str	r2, [r3, #12]
  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
 800069e:	0021      	movs	r1, r4
 80006a0:	187b      	adds	r3, r7, r1
 80006a2:	2200      	movs	r2, #0
 80006a4:	611a      	str	r2, [r3, #16]
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 80006a6:	187b      	adds	r3, r7, r1
 80006a8:	2240      	movs	r2, #64	@ 0x40
 80006aa:	615a      	str	r2, [r3, #20]
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 80006ac:	187b      	adds	r3, r7, r1
 80006ae:	2202      	movs	r2, #2
 80006b0:	61da      	str	r2, [r3, #28]
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
 80006b2:	187b      	adds	r3, r7, r1
 80006b4:	2202      	movs	r2, #2
 80006b6:	621a      	str	r2, [r3, #32]
  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
 80006b8:	187b      	adds	r3, r7, r1
 80006ba:	2200      	movs	r2, #0
 80006bc:	625a      	str	r2, [r3, #36]	@ 0x24
  RCC_OscInitStruct.PLL.PLLN = 8;
 80006be:	187b      	adds	r3, r7, r1
 80006c0:	2208      	movs	r2, #8
 80006c2:	629a      	str	r2, [r3, #40]	@ 0x28
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
 80006c4:	187b      	adds	r3, r7, r1
 80006c6:	2280      	movs	r2, #128	@ 0x80
 80006c8:	0292      	lsls	r2, r2, #10
 80006ca:	62da      	str	r2, [r3, #44]	@ 0x2c
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
 80006cc:	187b      	adds	r3, r7, r1
 80006ce:	2280      	movs	r2, #128	@ 0x80
 80006d0:	0592      	lsls	r2, r2, #22
 80006d2:	631a      	str	r2, [r3, #48]	@ 0x30
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 80006d4:	187b      	adds	r3, r7, r1
 80006d6:	0018      	movs	r0, r3
 80006d8:	f000 ff68 	bl	80015ac <HAL_RCC_OscConfig>
 80006dc:	1e03      	subs	r3, r0, #0
 80006de:	d001      	beq.n	80006e4 <SystemClock_Config+0x82>
  {
    Error_Handler();
 80006e0:	f000 f8e2 	bl	80008a8 <Error_Handler>
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 80006e4:	1d3b      	adds	r3, r7, #4
 80006e6:	2207      	movs	r2, #7
 80006e8:	601a      	str	r2, [r3, #0]
                              |RCC_CLOCKTYPE_PCLK1;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 80006ea:	1d3b      	adds	r3, r7, #4
 80006ec:	2202      	movs	r2, #2
 80006ee:	605a      	str	r2, [r3, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 80006f0:	1d3b      	adds	r3, r7, #4
 80006f2:	2200      	movs	r2, #0
 80006f4:	609a      	str	r2, [r3, #8]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 80006f6:	1d3b      	adds	r3, r7, #4
 80006f8:	2200      	movs	r2, #0
 80006fa:	60da      	str	r2, [r3, #12]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 80006fc:	1d3b      	adds	r3, r7, #4
 80006fe:	2102      	movs	r1, #2
 8000700:	0018      	movs	r0, r3
 8000702:	f001 fa63 	bl	8001bcc <HAL_RCC_ClockConfig>
 8000706:	1e03      	subs	r3, r0, #0
 8000708:	d001      	beq.n	800070e <SystemClock_Config+0xac>
  {
    Error_Handler();
 800070a:	f000 f8cd 	bl	80008a8 <Error_Handler>
  }
}
 800070e:	46c0      	nop			@ (mov r8, r8)
 8000710:	46bd      	mov	sp, r7
 8000712:	b013      	add	sp, #76	@ 0x4c
 8000714:	bd90      	pop	{r4, r7, pc}
	...

08000718 <MX_TIM3_Init>:
  * @brief TIM3 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM3_Init(void)
{
 8000718:	b580      	push	{r7, lr}
 800071a:	b08c      	sub	sp, #48	@ 0x30
 800071c:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM3_Init 0 */

  /* USER CODE END TIM3_Init 0 */

  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
 800071e:	2320      	movs	r3, #32
 8000720:	18fb      	adds	r3, r7, r3
 8000722:	0018      	movs	r0, r3
 8000724:	2310      	movs	r3, #16
 8000726:	001a      	movs	r2, r3
 8000728:	2100      	movs	r1, #0
 800072a:	f002 fc7d 	bl	8003028 <memset>
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 800072e:	2314      	movs	r3, #20
 8000730:	18fb      	adds	r3, r7, r3
 8000732:	0018      	movs	r0, r3
 8000734:	230c      	movs	r3, #12
 8000736:	001a      	movs	r2, r3
 8000738:	2100      	movs	r1, #0
 800073a:	f002 fc75 	bl	8003028 <memset>
  TIM_IC_InitTypeDef sConfigIC = {0};
 800073e:	1d3b      	adds	r3, r7, #4
 8000740:	0018      	movs	r0, r3
 8000742:	2310      	movs	r3, #16
 8000744:	001a      	movs	r2, r3
 8000746:	2100      	movs	r1, #0
 8000748:	f002 fc6e 	bl	8003028 <memset>

  /* USER CODE BEGIN TIM3_Init 1 */

  /* USER CODE END TIM3_Init 1 */
  htim3.Instance = TIM3;
 800074c:	4b35      	ldr	r3, [pc, #212]	@ (8000824 <MX_TIM3_Init+0x10c>)
 800074e:	4a36      	ldr	r2, [pc, #216]	@ (8000828 <MX_TIM3_Init+0x110>)
 8000750:	601a      	str	r2, [r3, #0]
  htim3.Init.Prescaler = 0;
 8000752:	4b34      	ldr	r3, [pc, #208]	@ (8000824 <MX_TIM3_Init+0x10c>)
 8000754:	2200      	movs	r2, #0
 8000756:	605a      	str	r2, [r3, #4]
  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
 8000758:	4b32      	ldr	r3, [pc, #200]	@ (8000824 <MX_TIM3_Init+0x10c>)
 800075a:	2200      	movs	r2, #0
 800075c:	609a      	str	r2, [r3, #8]
  htim3.Init.Period = 20000;
 800075e:	4b31      	ldr	r3, [pc, #196]	@ (8000824 <MX_TIM3_Init+0x10c>)
 8000760:	4a32      	ldr	r2, [pc, #200]	@ (800082c <MX_TIM3_Init+0x114>)
 8000762:	60da      	str	r2, [r3, #12]
  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 8000764:	4b2f      	ldr	r3, [pc, #188]	@ (8000824 <MX_TIM3_Init+0x10c>)
 8000766:	2200      	movs	r2, #0
 8000768:	611a      	str	r2, [r3, #16]
  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 800076a:	4b2e      	ldr	r3, [pc, #184]	@ (8000824 <MX_TIM3_Init+0x10c>)
 800076c:	2200      	movs	r2, #0
 800076e:	619a      	str	r2, [r3, #24]
  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
 8000770:	4b2c      	ldr	r3, [pc, #176]	@ (8000824 <MX_TIM3_Init+0x10c>)
 8000772:	0018      	movs	r0, r3
 8000774:	f001 fbb4 	bl	8001ee0 <HAL_TIM_Base_Init>
 8000778:	1e03      	subs	r3, r0, #0
 800077a:	d001      	beq.n	8000780 <MX_TIM3_Init+0x68>
  {
    Error_Handler();
 800077c:	f000 f894 	bl	80008a8 <Error_Handler>
  }
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 8000780:	2120      	movs	r1, #32
 8000782:	187b      	adds	r3, r7, r1
 8000784:	2280      	movs	r2, #128	@ 0x80
 8000786:	0152      	lsls	r2, r2, #5
 8000788:	601a      	str	r2, [r3, #0]
  if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
 800078a:	187a      	adds	r2, r7, r1
 800078c:	4b25      	ldr	r3, [pc, #148]	@ (8000824 <MX_TIM3_Init+0x10c>)
 800078e:	0011      	movs	r1, r2
 8000790:	0018      	movs	r0, r3
 8000792:	f001 ff8d 	bl	80026b0 <HAL_TIM_ConfigClockSource>
 8000796:	1e03      	subs	r3, r0, #0
 8000798:	d001      	beq.n	800079e <MX_TIM3_Init+0x86>
  {
    Error_Handler();
 800079a:	f000 f885 	bl	80008a8 <Error_Handler>
  }
  if (HAL_TIM_IC_Init(&htim3) != HAL_OK)
 800079e:	4b21      	ldr	r3, [pc, #132]	@ (8000824 <MX_TIM3_Init+0x10c>)
 80007a0:	0018      	movs	r0, r3
 80007a2:	f001 fbf5 	bl	8001f90 <HAL_TIM_IC_Init>
 80007a6:	1e03      	subs	r3, r0, #0
 80007a8:	d001      	beq.n	80007ae <MX_TIM3_Init+0x96>
  {
    Error_Handler();
 80007aa:	f000 f87d 	bl	80008a8 <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 80007ae:	2114      	movs	r1, #20
 80007b0:	187b      	adds	r3, r7, r1
 80007b2:	2200      	movs	r2, #0
 80007b4:	601a      	str	r2, [r3, #0]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 80007b6:	187b      	adds	r3, r7, r1
 80007b8:	2200      	movs	r2, #0
 80007ba:	609a      	str	r2, [r3, #8]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
 80007bc:	187a      	adds	r2, r7, r1
 80007be:	4b19      	ldr	r3, [pc, #100]	@ (8000824 <MX_TIM3_Init+0x10c>)
 80007c0:	0011      	movs	r1, r2
 80007c2:	0018      	movs	r0, r3
 80007c4:	f002 fbce 	bl	8002f64 <HAL_TIMEx_MasterConfigSynchronization>
 80007c8:	1e03      	subs	r3, r0, #0
 80007ca:	d001      	beq.n	80007d0 <MX_TIM3_Init+0xb8>
  {
    Error_Handler();
 80007cc:	f000 f86c 	bl	80008a8 <Error_Handler>
  }
  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_FALLING;
 80007d0:	1d3b      	adds	r3, r7, #4
 80007d2:	2202      	movs	r2, #2
 80007d4:	601a      	str	r2, [r3, #0]
  sConfigIC.ICSelection = TIM_ICSELECTION_INDIRECTTI;
 80007d6:	1d3b      	adds	r3, r7, #4
 80007d8:	2202      	movs	r2, #2
 80007da:	605a      	str	r2, [r3, #4]
  sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
 80007dc:	1d3b      	adds	r3, r7, #4
 80007de:	2200      	movs	r2, #0
 80007e0:	609a      	str	r2, [r3, #8]
  sConfigIC.ICFilter = 0;
 80007e2:	1d3b      	adds	r3, r7, #4
 80007e4:	2200      	movs	r2, #0
 80007e6:	60da      	str	r2, [r3, #12]
  if (HAL_TIM_IC_ConfigChannel(&htim3, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
 80007e8:	1d39      	adds	r1, r7, #4
 80007ea:	4b0e      	ldr	r3, [pc, #56]	@ (8000824 <MX_TIM3_Init+0x10c>)
 80007ec:	2200      	movs	r2, #0
 80007ee:	0018      	movs	r0, r3
 80007f0:	f001 feba 	bl	8002568 <HAL_TIM_IC_ConfigChannel>
 80007f4:	1e03      	subs	r3, r0, #0
 80007f6:	d001      	beq.n	80007fc <MX_TIM3_Init+0xe4>
  {
    Error_Handler();
 80007f8:	f000 f856 	bl	80008a8 <Error_Handler>
  }
  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
 80007fc:	1d3b      	adds	r3, r7, #4
 80007fe:	2200      	movs	r2, #0
 8000800:	601a      	str	r2, [r3, #0]
  sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
 8000802:	1d3b      	adds	r3, r7, #4
 8000804:	2201      	movs	r2, #1
 8000806:	605a      	str	r2, [r3, #4]
  if (HAL_TIM_IC_ConfigChannel(&htim3, &sConfigIC, TIM_CHANNEL_2) != HAL_OK)
 8000808:	1d39      	adds	r1, r7, #4
 800080a:	4b06      	ldr	r3, [pc, #24]	@ (8000824 <MX_TIM3_Init+0x10c>)
 800080c:	2204      	movs	r2, #4
 800080e:	0018      	movs	r0, r3
 8000810:	f001 feaa 	bl	8002568 <HAL_TIM_IC_ConfigChannel>
 8000814:	1e03      	subs	r3, r0, #0
 8000816:	d001      	beq.n	800081c <MX_TIM3_Init+0x104>
  {
    Error_Handler();
 8000818:	f000 f846 	bl	80008a8 <Error_Handler>
  }
  /* USER CODE BEGIN TIM3_Init 2 */

  /* USER CODE END TIM3_Init 2 */

}
 800081c:	46c0      	nop			@ (mov r8, r8)
 800081e:	46bd      	mov	sp, r7
 8000820:	b00c      	add	sp, #48	@ 0x30
 8000822:	bd80      	pop	{r7, pc}
 8000824:	200000d8 	.word	0x200000d8
 8000828:	40000400 	.word	0x40000400
 800082c:	00004e20 	.word	0x00004e20

08000830 <MX_DMA_Init>:

/**
  * Enable DMA controller clock
  */
static void MX_DMA_Init(void)
{
 8000830:	b580      	push	{r7, lr}
 8000832:	b082      	sub	sp, #8
 8000834:	af00      	add	r7, sp, #0

  /* DMA controller clock enable */
  __HAL_RCC_DMA1_CLK_ENABLE();
 8000836:	4b10      	ldr	r3, [pc, #64]	@ (8000878 <MX_DMA_Init+0x48>)
 8000838:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 800083a:	4b0f      	ldr	r3, [pc, #60]	@ (8000878 <MX_DMA_Init+0x48>)
 800083c:	2101      	movs	r1, #1
 800083e:	430a      	orrs	r2, r1
 8000840:	639a      	str	r2, [r3, #56]	@ 0x38
 8000842:	4b0d      	ldr	r3, [pc, #52]	@ (8000878 <MX_DMA_Init+0x48>)
 8000844:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8000846:	2201      	movs	r2, #1
 8000848:	4013      	ands	r3, r2
 800084a:	607b      	str	r3, [r7, #4]
 800084c:	687b      	ldr	r3, [r7, #4]

  /* DMA interrupt init */
  /* DMA1_Channel1_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 800084e:	2200      	movs	r2, #0
 8000850:	2100      	movs	r1, #0
 8000852:	2009      	movs	r0, #9
 8000854:	f000 faca 	bl	8000dec <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
 8000858:	2009      	movs	r0, #9
 800085a:	f000 fadc 	bl	8000e16 <HAL_NVIC_EnableIRQ>
  /* DMA1_Channel2_3_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0);
 800085e:	2200      	movs	r2, #0
 8000860:	2100      	movs	r1, #0
 8000862:	200a      	movs	r0, #10
 8000864:	f000 fac2 	bl	8000dec <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
 8000868:	200a      	movs	r0, #10
 800086a:	f000 fad4 	bl	8000e16 <HAL_NVIC_EnableIRQ>

}
 800086e:	46c0      	nop			@ (mov r8, r8)
 8000870:	46bd      	mov	sp, r7
 8000872:	b002      	add	sp, #8
 8000874:	bd80      	pop	{r7, pc}
 8000876:	46c0      	nop			@ (mov r8, r8)
 8000878:	40021000 	.word	0x40021000

0800087c <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 800087c:	b580      	push	{r7, lr}
 800087e:	b082      	sub	sp, #8
 8000880:	af00      	add	r7, sp, #0

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8000882:	4b08      	ldr	r3, [pc, #32]	@ (80008a4 <MX_GPIO_Init+0x28>)
 8000884:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 8000886:	4b07      	ldr	r3, [pc, #28]	@ (80008a4 <MX_GPIO_Init+0x28>)
 8000888:	2101      	movs	r1, #1
 800088a:	430a      	orrs	r2, r1
 800088c:	635a      	str	r2, [r3, #52]	@ 0x34
 800088e:	4b05      	ldr	r3, [pc, #20]	@ (80008a4 <MX_GPIO_Init+0x28>)
 8000890:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8000892:	2201      	movs	r2, #1
 8000894:	4013      	ands	r3, r2
 8000896:	607b      	str	r3, [r7, #4]
 8000898:	687b      	ldr	r3, [r7, #4]

}
 800089a:	46c0      	nop			@ (mov r8, r8)
 800089c:	46bd      	mov	sp, r7
 800089e:	b002      	add	sp, #8
 80008a0:	bd80      	pop	{r7, pc}
 80008a2:	46c0      	nop			@ (mov r8, r8)
 80008a4:	40021000 	.word	0x40021000

080008a8 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 80008a8:	b580      	push	{r7, lr}
 80008aa:	af00      	add	r7, sp, #0
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 80008ac:	b672      	cpsid	i
}
 80008ae:	46c0      	nop			@ (mov r8, r8)
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 80008b0:	46c0      	nop			@ (mov r8, r8)
 80008b2:	e7fd      	b.n	80008b0 <Error_Handler+0x8>

080008b4 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 80008b4:	b580      	push	{r7, lr}
 80008b6:	b082      	sub	sp, #8
 80008b8:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 80008ba:	4b0f      	ldr	r3, [pc, #60]	@ (80008f8 <HAL_MspInit+0x44>)
 80008bc:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
 80008be:	4b0e      	ldr	r3, [pc, #56]	@ (80008f8 <HAL_MspInit+0x44>)
 80008c0:	2101      	movs	r1, #1
 80008c2:	430a      	orrs	r2, r1
 80008c4:	641a      	str	r2, [r3, #64]	@ 0x40
 80008c6:	4b0c      	ldr	r3, [pc, #48]	@ (80008f8 <HAL_MspInit+0x44>)
 80008c8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80008ca:	2201      	movs	r2, #1
 80008cc:	4013      	ands	r3, r2
 80008ce:	607b      	str	r3, [r7, #4]
 80008d0:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 80008d2:	4b09      	ldr	r3, [pc, #36]	@ (80008f8 <HAL_MspInit+0x44>)
 80008d4:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 80008d6:	4b08      	ldr	r3, [pc, #32]	@ (80008f8 <HAL_MspInit+0x44>)
 80008d8:	2180      	movs	r1, #128	@ 0x80
 80008da:	0549      	lsls	r1, r1, #21
 80008dc:	430a      	orrs	r2, r1
 80008de:	63da      	str	r2, [r3, #60]	@ 0x3c
 80008e0:	4b05      	ldr	r3, [pc, #20]	@ (80008f8 <HAL_MspInit+0x44>)
 80008e2:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 80008e4:	2380      	movs	r3, #128	@ 0x80
 80008e6:	055b      	lsls	r3, r3, #21
 80008e8:	4013      	ands	r3, r2
 80008ea:	603b      	str	r3, [r7, #0]
 80008ec:	683b      	ldr	r3, [r7, #0]
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 80008ee:	46c0      	nop			@ (mov r8, r8)
 80008f0:	46bd      	mov	sp, r7
 80008f2:	b002      	add	sp, #8
 80008f4:	bd80      	pop	{r7, pc}
 80008f6:	46c0      	nop			@ (mov r8, r8)
 80008f8:	40021000 	.word	0x40021000

080008fc <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
 80008fc:	b590      	push	{r4, r7, lr}
 80008fe:	b08b      	sub	sp, #44	@ 0x2c
 8000900:	af00      	add	r7, sp, #0
 8000902:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000904:	2414      	movs	r4, #20
 8000906:	193b      	adds	r3, r7, r4
 8000908:	0018      	movs	r0, r3
 800090a:	2314      	movs	r3, #20
 800090c:	001a      	movs	r2, r3
 800090e:	2100      	movs	r1, #0
 8000910:	f002 fb8a 	bl	8003028 <memset>
  if(htim_base->Instance==TIM3)
 8000914:	687b      	ldr	r3, [r7, #4]
 8000916:	681b      	ldr	r3, [r3, #0]
 8000918:	4a4a      	ldr	r2, [pc, #296]	@ (8000a44 <HAL_TIM_Base_MspInit+0x148>)
 800091a:	4293      	cmp	r3, r2
 800091c:	d000      	beq.n	8000920 <HAL_TIM_Base_MspInit+0x24>
 800091e:	e08c      	b.n	8000a3a <HAL_TIM_Base_MspInit+0x13e>
  {
  /* USER CODE BEGIN TIM3_MspInit 0 */

  /* USER CODE END TIM3_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM3_CLK_ENABLE();
 8000920:	4b49      	ldr	r3, [pc, #292]	@ (8000a48 <HAL_TIM_Base_MspInit+0x14c>)
 8000922:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 8000924:	4b48      	ldr	r3, [pc, #288]	@ (8000a48 <HAL_TIM_Base_MspInit+0x14c>)
 8000926:	2102      	movs	r1, #2
 8000928:	430a      	orrs	r2, r1
 800092a:	63da      	str	r2, [r3, #60]	@ 0x3c
 800092c:	4b46      	ldr	r3, [pc, #280]	@ (8000a48 <HAL_TIM_Base_MspInit+0x14c>)
 800092e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8000930:	2202      	movs	r2, #2
 8000932:	4013      	ands	r3, r2
 8000934:	613b      	str	r3, [r7, #16]
 8000936:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8000938:	4b43      	ldr	r3, [pc, #268]	@ (8000a48 <HAL_TIM_Base_MspInit+0x14c>)
 800093a:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 800093c:	4b42      	ldr	r3, [pc, #264]	@ (8000a48 <HAL_TIM_Base_MspInit+0x14c>)
 800093e:	2101      	movs	r1, #1
 8000940:	430a      	orrs	r2, r1
 8000942:	635a      	str	r2, [r3, #52]	@ 0x34
 8000944:	4b40      	ldr	r3, [pc, #256]	@ (8000a48 <HAL_TIM_Base_MspInit+0x14c>)
 8000946:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8000948:	2201      	movs	r2, #1
 800094a:	4013      	ands	r3, r2
 800094c:	60fb      	str	r3, [r7, #12]
 800094e:	68fb      	ldr	r3, [r7, #12]
    /**TIM3 GPIO Configuration
    PA7     ------> TIM3_CH2
    */
    GPIO_InitStruct.Pin = PWM_DSHOT_INPUT_Pin;
 8000950:	0021      	movs	r1, r4
 8000952:	187b      	adds	r3, r7, r1
 8000954:	2280      	movs	r2, #128	@ 0x80
 8000956:	601a      	str	r2, [r3, #0]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000958:	187b      	adds	r3, r7, r1
 800095a:	2202      	movs	r2, #2
 800095c:	605a      	str	r2, [r3, #4]
    GPIO_InitStruct.Pull = GPIO_PULLDOWN;
 800095e:	187b      	adds	r3, r7, r1
 8000960:	2202      	movs	r2, #2
 8000962:	609a      	str	r2, [r3, #8]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000964:	187b      	adds	r3, r7, r1
 8000966:	2203      	movs	r2, #3
 8000968:	60da      	str	r2, [r3, #12]
    GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
 800096a:	187b      	adds	r3, r7, r1
 800096c:	2201      	movs	r2, #1
 800096e:	611a      	str	r2, [r3, #16]
    HAL_GPIO_Init(PWM_DSHOT_INPUT_GPIO_Port, &GPIO_InitStruct);
 8000970:	187a      	adds	r2, r7, r1
 8000972:	23a0      	movs	r3, #160	@ 0xa0
 8000974:	05db      	lsls	r3, r3, #23
 8000976:	0011      	movs	r1, r2
 8000978:	0018      	movs	r0, r3
 800097a:	f000 fc73 	bl	8001264 <HAL_GPIO_Init>

    /* TIM3 DMA Init */
    /* TIM3_CH1 Init */
    hdma_tim3_ch1.Instance = DMA1_Channel1;
 800097e:	4b33      	ldr	r3, [pc, #204]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 8000980:	4a33      	ldr	r2, [pc, #204]	@ (8000a50 <HAL_TIM_Base_MspInit+0x154>)
 8000982:	601a      	str	r2, [r3, #0]
    hdma_tim3_ch1.Init.Request = DMA_REQUEST_TIM3_CH1;
 8000984:	4b31      	ldr	r3, [pc, #196]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 8000986:	2220      	movs	r2, #32
 8000988:	605a      	str	r2, [r3, #4]
    hdma_tim3_ch1.Init.Direction = DMA_PERIPH_TO_MEMORY;
 800098a:	4b30      	ldr	r3, [pc, #192]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 800098c:	2200      	movs	r2, #0
 800098e:	609a      	str	r2, [r3, #8]
    hdma_tim3_ch1.Init.PeriphInc = DMA_PINC_DISABLE;
 8000990:	4b2e      	ldr	r3, [pc, #184]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 8000992:	2200      	movs	r2, #0
 8000994:	60da      	str	r2, [r3, #12]
    hdma_tim3_ch1.Init.MemInc = DMA_MINC_ENABLE;
 8000996:	4b2d      	ldr	r3, [pc, #180]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 8000998:	2280      	movs	r2, #128	@ 0x80
 800099a:	611a      	str	r2, [r3, #16]
    hdma_tim3_ch1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
 800099c:	4b2b      	ldr	r3, [pc, #172]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 800099e:	2280      	movs	r2, #128	@ 0x80
 80009a0:	0092      	lsls	r2, r2, #2
 80009a2:	615a      	str	r2, [r3, #20]
    hdma_tim3_ch1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
 80009a4:	4b29      	ldr	r3, [pc, #164]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 80009a6:	2280      	movs	r2, #128	@ 0x80
 80009a8:	0112      	lsls	r2, r2, #4
 80009aa:	619a      	str	r2, [r3, #24]
    hdma_tim3_ch1.Init.Mode = DMA_CIRCULAR;
 80009ac:	4b27      	ldr	r3, [pc, #156]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 80009ae:	2220      	movs	r2, #32
 80009b0:	61da      	str	r2, [r3, #28]
    hdma_tim3_ch1.Init.Priority = DMA_PRIORITY_LOW;
 80009b2:	4b26      	ldr	r3, [pc, #152]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 80009b4:	2200      	movs	r2, #0
 80009b6:	621a      	str	r2, [r3, #32]
    if (HAL_DMA_Init(&hdma_tim3_ch1) != HAL_OK)
 80009b8:	4b24      	ldr	r3, [pc, #144]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 80009ba:	0018      	movs	r0, r3
 80009bc:	f000 fa48 	bl	8000e50 <HAL_DMA_Init>
 80009c0:	1e03      	subs	r3, r0, #0
 80009c2:	d001      	beq.n	80009c8 <HAL_TIM_Base_MspInit+0xcc>
    {
      Error_Handler();
 80009c4:	f7ff ff70 	bl	80008a8 <Error_Handler>
    }

    __HAL_LINKDMA(htim_base,hdma[TIM_DMA_ID_CC1],hdma_tim3_ch1);
 80009c8:	687b      	ldr	r3, [r7, #4]
 80009ca:	4a20      	ldr	r2, [pc, #128]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 80009cc:	625a      	str	r2, [r3, #36]	@ 0x24
 80009ce:	4b1f      	ldr	r3, [pc, #124]	@ (8000a4c <HAL_TIM_Base_MspInit+0x150>)
 80009d0:	687a      	ldr	r2, [r7, #4]
 80009d2:	629a      	str	r2, [r3, #40]	@ 0x28

    /* TIM3_CH2 Init */
    hdma_tim3_ch2.Instance = DMA1_Channel2;
 80009d4:	4b1f      	ldr	r3, [pc, #124]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 80009d6:	4a20      	ldr	r2, [pc, #128]	@ (8000a58 <HAL_TIM_Base_MspInit+0x15c>)
 80009d8:	601a      	str	r2, [r3, #0]
    hdma_tim3_ch2.Init.Request = DMA_REQUEST_TIM3_CH2;
 80009da:	4b1e      	ldr	r3, [pc, #120]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 80009dc:	2221      	movs	r2, #33	@ 0x21
 80009de:	605a      	str	r2, [r3, #4]
    hdma_tim3_ch2.Init.Direction = DMA_PERIPH_TO_MEMORY;
 80009e0:	4b1c      	ldr	r3, [pc, #112]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 80009e2:	2200      	movs	r2, #0
 80009e4:	609a      	str	r2, [r3, #8]
    hdma_tim3_ch2.Init.PeriphInc = DMA_PINC_DISABLE;
 80009e6:	4b1b      	ldr	r3, [pc, #108]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 80009e8:	2200      	movs	r2, #0
 80009ea:	60da      	str	r2, [r3, #12]
    hdma_tim3_ch2.Init.MemInc = DMA_MINC_ENABLE;
 80009ec:	4b19      	ldr	r3, [pc, #100]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 80009ee:	2280      	movs	r2, #128	@ 0x80
 80009f0:	611a      	str	r2, [r3, #16]
    hdma_tim3_ch2.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
 80009f2:	4b18      	ldr	r3, [pc, #96]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 80009f4:	2280      	movs	r2, #128	@ 0x80
 80009f6:	0092      	lsls	r2, r2, #2
 80009f8:	615a      	str	r2, [r3, #20]
    hdma_tim3_ch2.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
 80009fa:	4b16      	ldr	r3, [pc, #88]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 80009fc:	2280      	movs	r2, #128	@ 0x80
 80009fe:	0112      	lsls	r2, r2, #4
 8000a00:	619a      	str	r2, [r3, #24]
    hdma_tim3_ch2.Init.Mode = DMA_CIRCULAR;
 8000a02:	4b14      	ldr	r3, [pc, #80]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 8000a04:	2220      	movs	r2, #32
 8000a06:	61da      	str	r2, [r3, #28]
    hdma_tim3_ch2.Init.Priority = DMA_PRIORITY_LOW;
 8000a08:	4b12      	ldr	r3, [pc, #72]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 8000a0a:	2200      	movs	r2, #0
 8000a0c:	621a      	str	r2, [r3, #32]
    if (HAL_DMA_Init(&hdma_tim3_ch2) != HAL_OK)
 8000a0e:	4b11      	ldr	r3, [pc, #68]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 8000a10:	0018      	movs	r0, r3
 8000a12:	f000 fa1d 	bl	8000e50 <HAL_DMA_Init>
 8000a16:	1e03      	subs	r3, r0, #0
 8000a18:	d001      	beq.n	8000a1e <HAL_TIM_Base_MspInit+0x122>
    {
      Error_Handler();
 8000a1a:	f7ff ff45 	bl	80008a8 <Error_Handler>
    }

    __HAL_LINKDMA(htim_base,hdma[TIM_DMA_ID_CC2],hdma_tim3_ch2);
 8000a1e:	687b      	ldr	r3, [r7, #4]
 8000a20:	4a0c      	ldr	r2, [pc, #48]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 8000a22:	629a      	str	r2, [r3, #40]	@ 0x28
 8000a24:	4b0b      	ldr	r3, [pc, #44]	@ (8000a54 <HAL_TIM_Base_MspInit+0x158>)
 8000a26:	687a      	ldr	r2, [r7, #4]
 8000a28:	629a      	str	r2, [r3, #40]	@ 0x28

    /* TIM3 interrupt Init */
    HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
 8000a2a:	2200      	movs	r2, #0
 8000a2c:	2100      	movs	r1, #0
 8000a2e:	2010      	movs	r0, #16
 8000a30:	f000 f9dc 	bl	8000dec <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(TIM3_IRQn);
 8000a34:	2010      	movs	r0, #16
 8000a36:	f000 f9ee 	bl	8000e16 <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN TIM3_MspInit 1 */

  /* USER CODE END TIM3_MspInit 1 */
  }

}
 8000a3a:	46c0      	nop			@ (mov r8, r8)
 8000a3c:	46bd      	mov	sp, r7
 8000a3e:	b00b      	add	sp, #44	@ 0x2c
 8000a40:	bd90      	pop	{r4, r7, pc}
 8000a42:	46c0      	nop			@ (mov r8, r8)
 8000a44:	40000400 	.word	0x40000400
 8000a48:	40021000 	.word	0x40021000
 8000a4c:	20000124 	.word	0x20000124
 8000a50:	40020008 	.word	0x40020008
 8000a54:	20000180 	.word	0x20000180
 8000a58:	4002001c 	.word	0x4002001c

08000a5c <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 8000a5c:	b580      	push	{r7, lr}
 8000a5e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 8000a60:	46c0      	nop			@ (mov r8, r8)
 8000a62:	e7fd      	b.n	8000a60 <NMI_Handler+0x4>

08000a64 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8000a64:	b580      	push	{r7, lr}
 8000a66:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8000a68:	46c0      	nop			@ (mov r8, r8)
 8000a6a:	e7fd      	b.n	8000a68 <HardFault_Handler+0x4>

08000a6c <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 8000a6c:	b580      	push	{r7, lr}
 8000a6e:	af00      	add	r7, sp, #0

  /* USER CODE END SVC_IRQn 0 */
  /* USER CODE BEGIN SVC_IRQn 1 */

  /* USER CODE END SVC_IRQn 1 */
}
 8000a70:	46c0      	nop			@ (mov r8, r8)
 8000a72:	46bd      	mov	sp, r7
 8000a74:	bd80      	pop	{r7, pc}

08000a76 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8000a76:	b580      	push	{r7, lr}
 8000a78:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 8000a7a:	46c0      	nop			@ (mov r8, r8)
 8000a7c:	46bd      	mov	sp, r7
 8000a7e:	bd80      	pop	{r7, pc}

08000a80 <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 8000a80:	b580      	push	{r7, lr}
 8000a82:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8000a84:	f000 f8c6 	bl	8000c14 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 8000a88:	46c0      	nop			@ (mov r8, r8)
 8000a8a:	46bd      	mov	sp, r7
 8000a8c:	bd80      	pop	{r7, pc}
	...

08000a90 <DMA1_Channel1_IRQHandler>:

/**
  * @brief This function handles DMA1 channel 1 interrupt.
  */
void DMA1_Channel1_IRQHandler(void)
{
 8000a90:	b580      	push	{r7, lr}
 8000a92:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
  DMA1_Channel1_IRQ(&hdma_tim3_ch1);
 8000a94:	4b03      	ldr	r3, [pc, #12]	@ (8000aa4 <DMA1_Channel1_IRQHandler+0x14>)
 8000a96:	0018      	movs	r0, r3
 8000a98:	f7ff fbbe 	bl	8000218 <DMA1_Channel1_IRQ>
  /* USER CODE END DMA1_Channel1_IRQn 0 */
  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */

  /* USER CODE END DMA1_Channel1_IRQn 1 */
}
 8000a9c:	46c0      	nop			@ (mov r8, r8)
 8000a9e:	46bd      	mov	sp, r7
 8000aa0:	bd80      	pop	{r7, pc}
 8000aa2:	46c0      	nop			@ (mov r8, r8)
 8000aa4:	20000124 	.word	0x20000124

08000aa8 <DMA1_Channel2_3_IRQHandler>:

/**
  * @brief This function handles DMA1 channel 2 and channel 3 interrupts.
  */
void DMA1_Channel2_3_IRQHandler(void)
{
 8000aa8:	b580      	push	{r7, lr}
 8000aaa:	af00      	add	r7, sp, #0

  /* USER CODE END DMA1_Channel2_3_IRQn 0 */
  /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */

  /* USER CODE END DMA1_Channel2_3_IRQn 1 */
}
 8000aac:	46c0      	nop			@ (mov r8, r8)
 8000aae:	46bd      	mov	sp, r7
 8000ab0:	bd80      	pop	{r7, pc}

08000ab2 <TIM3_IRQHandler>:

/**
  * @brief This function handles TIM3 global interrupt.
  */
void TIM3_IRQHandler(void)
{
 8000ab2:	b580      	push	{r7, lr}
 8000ab4:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM3_IRQn 0 */
	TIM3_IRQ();
 8000ab6:	f7ff fd61 	bl	800057c <TIM3_IRQ>
  /* USER CODE END TIM3_IRQn 0 */
  /* USER CODE BEGIN TIM3_IRQn 1 */

  /* USER CODE END TIM3_IRQn 1 */
}
 8000aba:	46c0      	nop			@ (mov r8, r8)
 8000abc:	46bd      	mov	sp, r7
 8000abe:	bd80      	pop	{r7, pc}

08000ac0 <SystemInit>:
  * @brief  Setup the microcontroller system.
  * @param  None
  * @retval None
  */
void SystemInit(void)
{
 8000ac0:	b580      	push	{r7, lr}
 8000ac2:	af00      	add	r7, sp, #0
  /* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
#endif /* USER_VECT_TAB_ADDRESS */
}
 8000ac4:	46c0      	nop			@ (mov r8, r8)
 8000ac6:	46bd      	mov	sp, r7
 8000ac8:	bd80      	pop	{r7, pc}

08000aca <User_Init>:
#include "main.h"
#include "user.h"

void User_Init(void) {
 8000aca:	b580      	push	{r7, lr}
 8000acc:	af00      	add	r7, sp, #0
	//PWMInput_Init();
	Dshot_Init(DShot_300);
 8000ace:	2001      	movs	r0, #1
 8000ad0:	f7ff fcde 	bl	8000490 <Dshot_Init>
}
 8000ad4:	46c0      	nop			@ (mov r8, r8)
 8000ad6:	46bd      	mov	sp, r7
 8000ad8:	bd80      	pop	{r7, pc}

08000ada <User_MainLoop>:

uint16_t ref;

void User_MainLoop(void) {
 8000ada:	b580      	push	{r7, lr}
 8000adc:	af00      	add	r7, sp, #0


	//ref = PWMInput_Get();

	HAL_Delay(100);
 8000ade:	2064      	movs	r0, #100	@ 0x64
 8000ae0:	f000 f8b4 	bl	8000c4c <HAL_Delay>
}
 8000ae4:	46c0      	nop			@ (mov r8, r8)
 8000ae6:	46bd      	mov	sp, r7
 8000ae8:	bd80      	pop	{r7, pc}
	...

08000aec <Reset_Handler>:

  .section .text.Reset_Handler
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:
  ldr   r0, =_estack
 8000aec:	480d      	ldr	r0, [pc, #52]	@ (8000b24 <LoopForever+0x2>)
  mov   sp, r0          /* set stack pointer */
 8000aee:	4685      	mov	sp, r0

/* Call the clock system initialization function.*/
  bl  SystemInit
 8000af0:	f7ff ffe6 	bl	8000ac0 <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 8000af4:	480c      	ldr	r0, [pc, #48]	@ (8000b28 <LoopForever+0x6>)
  ldr r1, =_edata
 8000af6:	490d      	ldr	r1, [pc, #52]	@ (8000b2c <LoopForever+0xa>)
  ldr r2, =_sidata
 8000af8:	4a0d      	ldr	r2, [pc, #52]	@ (8000b30 <LoopForever+0xe>)
  movs r3, #0
 8000afa:	2300      	movs	r3, #0
  b LoopCopyDataInit
 8000afc:	e002      	b.n	8000b04 <LoopCopyDataInit>

08000afe <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 8000afe:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 8000b00:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 8000b02:	3304      	adds	r3, #4

08000b04 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8000b04:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8000b06:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8000b08:	d3f9      	bcc.n	8000afe <CopyDataInit>

/* Zero fill the bss segment. */
  ldr r2, =_sbss
 8000b0a:	4a0a      	ldr	r2, [pc, #40]	@ (8000b34 <LoopForever+0x12>)
  ldr r4, =_ebss
 8000b0c:	4c0a      	ldr	r4, [pc, #40]	@ (8000b38 <LoopForever+0x16>)
  movs r3, #0
 8000b0e:	2300      	movs	r3, #0
  b LoopFillZerobss
 8000b10:	e001      	b.n	8000b16 <LoopFillZerobss>

08000b12 <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 8000b12:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8000b14:	3204      	adds	r2, #4

08000b16 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8000b16:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8000b18:	d3fb      	bcc.n	8000b12 <FillZerobss>

/* Call static constructors */
  bl __libc_init_array
 8000b1a:	f002 fa8d 	bl	8003038 <__libc_init_array>
/* Call the application s entry point.*/
  bl main
 8000b1e:	f7ff fd8f 	bl	8000640 <main>

08000b22 <LoopForever>:

LoopForever:
  b LoopForever
 8000b22:	e7fe      	b.n	8000b22 <LoopForever>
  ldr   r0, =_estack
 8000b24:	20002000 	.word	0x20002000
  ldr r0, =_sdata
 8000b28:	20000000 	.word	0x20000000
  ldr r1, =_edata
 8000b2c:	2000000c 	.word	0x2000000c
  ldr r2, =_sidata
 8000b30:	080030e0 	.word	0x080030e0
  ldr r2, =_sbss
 8000b34:	2000000c 	.word	0x2000000c
  ldr r4, =_ebss
 8000b38:	200001e0 	.word	0x200001e0

08000b3c <ADC1_IRQHandler>:
 * @retval None
*/
  .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8000b3c:	e7fe      	b.n	8000b3c <ADC1_IRQHandler>
	...

08000b40 <HAL_Init>:
  *         each 1ms in the SysTick_Handler() interrupt handler.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 8000b40:	b580      	push	{r7, lr}
 8000b42:	b082      	sub	sp, #8
 8000b44:	af00      	add	r7, sp, #0
  HAL_StatusTypeDef  status = HAL_OK;
 8000b46:	1dfb      	adds	r3, r7, #7
 8000b48:	2200      	movs	r2, #0
 8000b4a:	701a      	strb	r2, [r3, #0]
#if (INSTRUCTION_CACHE_ENABLE == 0U)
  __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */

#if (PREFETCH_ENABLE != 0U)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8000b4c:	4b0b      	ldr	r3, [pc, #44]	@ (8000b7c <HAL_Init+0x3c>)
 8000b4e:	681a      	ldr	r2, [r3, #0]
 8000b50:	4b0a      	ldr	r3, [pc, #40]	@ (8000b7c <HAL_Init+0x3c>)
 8000b52:	2180      	movs	r1, #128	@ 0x80
 8000b54:	0049      	lsls	r1, r1, #1
 8000b56:	430a      	orrs	r2, r1
 8000b58:	601a      	str	r2, [r3, #0]
#endif /* PREFETCH_ENABLE */

  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 8000b5a:	2003      	movs	r0, #3
 8000b5c:	f000 f810 	bl	8000b80 <HAL_InitTick>
 8000b60:	1e03      	subs	r3, r0, #0
 8000b62:	d003      	beq.n	8000b6c <HAL_Init+0x2c>
  {
    status = HAL_ERROR;
 8000b64:	1dfb      	adds	r3, r7, #7
 8000b66:	2201      	movs	r2, #1
 8000b68:	701a      	strb	r2, [r3, #0]
 8000b6a:	e001      	b.n	8000b70 <HAL_Init+0x30>
  }
  else
  {
  /* Init the low level hardware */
  HAL_MspInit();
 8000b6c:	f7ff fea2 	bl	80008b4 <HAL_MspInit>
  }

  /* Return function status */
  return status;
 8000b70:	1dfb      	adds	r3, r7, #7
 8000b72:	781b      	ldrb	r3, [r3, #0]
}
 8000b74:	0018      	movs	r0, r3
 8000b76:	46bd      	mov	sp, r7
 8000b78:	b002      	add	sp, #8
 8000b7a:	bd80      	pop	{r7, pc}
 8000b7c:	40022000 	.word	0x40022000

08000b80 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8000b80:	b590      	push	{r4, r7, lr}
 8000b82:	b085      	sub	sp, #20
 8000b84:	af00      	add	r7, sp, #0
 8000b86:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef  status = HAL_OK;
 8000b88:	230f      	movs	r3, #15
 8000b8a:	18fb      	adds	r3, r7, r3
 8000b8c:	2200      	movs	r2, #0
 8000b8e:	701a      	strb	r2, [r3, #0]

  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ 
  if ((uint32_t)uwTickFreq != 0U)
 8000b90:	4b1d      	ldr	r3, [pc, #116]	@ (8000c08 <HAL_InitTick+0x88>)
 8000b92:	781b      	ldrb	r3, [r3, #0]
 8000b94:	2b00      	cmp	r3, #0
 8000b96:	d02b      	beq.n	8000bf0 <HAL_InitTick+0x70>
  {
    /*Configure the SysTick to have interrupt in 1ms time basis*/
    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U)
 8000b98:	4b1c      	ldr	r3, [pc, #112]	@ (8000c0c <HAL_InitTick+0x8c>)
 8000b9a:	681c      	ldr	r4, [r3, #0]
 8000b9c:	4b1a      	ldr	r3, [pc, #104]	@ (8000c08 <HAL_InitTick+0x88>)
 8000b9e:	781b      	ldrb	r3, [r3, #0]
 8000ba0:	0019      	movs	r1, r3
 8000ba2:	23fa      	movs	r3, #250	@ 0xfa
 8000ba4:	0098      	lsls	r0, r3, #2
 8000ba6:	f7ff faab 	bl	8000100 <__udivsi3>
 8000baa:	0003      	movs	r3, r0
 8000bac:	0019      	movs	r1, r3
 8000bae:	0020      	movs	r0, r4
 8000bb0:	f7ff faa6 	bl	8000100 <__udivsi3>
 8000bb4:	0003      	movs	r3, r0
 8000bb6:	0018      	movs	r0, r3
 8000bb8:	f000 f93d 	bl	8000e36 <HAL_SYSTICK_Config>
 8000bbc:	1e03      	subs	r3, r0, #0
 8000bbe:	d112      	bne.n	8000be6 <HAL_InitTick+0x66>
    {
      /* Configure the SysTick IRQ priority */
      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8000bc0:	687b      	ldr	r3, [r7, #4]
 8000bc2:	2b03      	cmp	r3, #3
 8000bc4:	d80a      	bhi.n	8000bdc <HAL_InitTick+0x5c>
      {
        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8000bc6:	6879      	ldr	r1, [r7, #4]
 8000bc8:	2301      	movs	r3, #1
 8000bca:	425b      	negs	r3, r3
 8000bcc:	2200      	movs	r2, #0
 8000bce:	0018      	movs	r0, r3
 8000bd0:	f000 f90c 	bl	8000dec <HAL_NVIC_SetPriority>
        uwTickPrio = TickPriority;
 8000bd4:	4b0e      	ldr	r3, [pc, #56]	@ (8000c10 <HAL_InitTick+0x90>)
 8000bd6:	687a      	ldr	r2, [r7, #4]
 8000bd8:	601a      	str	r2, [r3, #0]
 8000bda:	e00d      	b.n	8000bf8 <HAL_InitTick+0x78>
      }
      else
      {
        status = HAL_ERROR;
 8000bdc:	230f      	movs	r3, #15
 8000bde:	18fb      	adds	r3, r7, r3
 8000be0:	2201      	movs	r2, #1
 8000be2:	701a      	strb	r2, [r3, #0]
 8000be4:	e008      	b.n	8000bf8 <HAL_InitTick+0x78>
      }
    }
    else
    {
      status = HAL_ERROR;
 8000be6:	230f      	movs	r3, #15
 8000be8:	18fb      	adds	r3, r7, r3
 8000bea:	2201      	movs	r2, #1
 8000bec:	701a      	strb	r2, [r3, #0]
 8000bee:	e003      	b.n	8000bf8 <HAL_InitTick+0x78>
    }
  }
  else
  {
    status = HAL_ERROR;
 8000bf0:	230f      	movs	r3, #15
 8000bf2:	18fb      	adds	r3, r7, r3
 8000bf4:	2201      	movs	r2, #1
 8000bf6:	701a      	strb	r2, [r3, #0]
  }

  /* Return function status */
  return status;
 8000bf8:	230f      	movs	r3, #15
 8000bfa:	18fb      	adds	r3, r7, r3
 8000bfc:	781b      	ldrb	r3, [r3, #0]
}
 8000bfe:	0018      	movs	r0, r3
 8000c00:	46bd      	mov	sp, r7
 8000c02:	b005      	add	sp, #20
 8000c04:	bd90      	pop	{r4, r7, pc}
 8000c06:	46c0      	nop			@ (mov r8, r8)
 8000c08:	20000008 	.word	0x20000008
 8000c0c:	20000000 	.word	0x20000000
 8000c10:	20000004 	.word	0x20000004

08000c14 <HAL_IncTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8000c14:	b580      	push	{r7, lr}
 8000c16:	af00      	add	r7, sp, #0
  uwTick += (uint32_t)uwTickFreq;
 8000c18:	4b05      	ldr	r3, [pc, #20]	@ (8000c30 <HAL_IncTick+0x1c>)
 8000c1a:	781b      	ldrb	r3, [r3, #0]
 8000c1c:	001a      	movs	r2, r3
 8000c1e:	4b05      	ldr	r3, [pc, #20]	@ (8000c34 <HAL_IncTick+0x20>)
 8000c20:	681b      	ldr	r3, [r3, #0]
 8000c22:	18d2      	adds	r2, r2, r3
 8000c24:	4b03      	ldr	r3, [pc, #12]	@ (8000c34 <HAL_IncTick+0x20>)
 8000c26:	601a      	str	r2, [r3, #0]
}
 8000c28:	46c0      	nop			@ (mov r8, r8)
 8000c2a:	46bd      	mov	sp, r7
 8000c2c:	bd80      	pop	{r7, pc}
 8000c2e:	46c0      	nop			@ (mov r8, r8)
 8000c30:	20000008 	.word	0x20000008
 8000c34:	200001dc 	.word	0x200001dc

08000c38 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8000c38:	b580      	push	{r7, lr}
 8000c3a:	af00      	add	r7, sp, #0
  return uwTick;
 8000c3c:	4b02      	ldr	r3, [pc, #8]	@ (8000c48 <HAL_GetTick+0x10>)
 8000c3e:	681b      	ldr	r3, [r3, #0]
}
 8000c40:	0018      	movs	r0, r3
 8000c42:	46bd      	mov	sp, r7
 8000c44:	bd80      	pop	{r7, pc}
 8000c46:	46c0      	nop			@ (mov r8, r8)
 8000c48:	200001dc 	.word	0x200001dc

08000c4c <HAL_Delay>:
  *       implementations in user file.
  * @param Delay  specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 8000c4c:	b580      	push	{r7, lr}
 8000c4e:	b084      	sub	sp, #16
 8000c50:	af00      	add	r7, sp, #0
 8000c52:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = HAL_GetTick();
 8000c54:	f7ff fff0 	bl	8000c38 <HAL_GetTick>
 8000c58:	0003      	movs	r3, r0
 8000c5a:	60bb      	str	r3, [r7, #8]
  uint32_t wait = Delay;
 8000c5c:	687b      	ldr	r3, [r7, #4]
 8000c5e:	60fb      	str	r3, [r7, #12]

  /* Add a freq to guarantee minimum wait */
  if (wait < HAL_MAX_DELAY)
 8000c60:	68fb      	ldr	r3, [r7, #12]
 8000c62:	3301      	adds	r3, #1
 8000c64:	d005      	beq.n	8000c72 <HAL_Delay+0x26>
  {
    wait += (uint32_t)(uwTickFreq);
 8000c66:	4b0a      	ldr	r3, [pc, #40]	@ (8000c90 <HAL_Delay+0x44>)
 8000c68:	781b      	ldrb	r3, [r3, #0]
 8000c6a:	001a      	movs	r2, r3
 8000c6c:	68fb      	ldr	r3, [r7, #12]
 8000c6e:	189b      	adds	r3, r3, r2
 8000c70:	60fb      	str	r3, [r7, #12]
  }

  while ((HAL_GetTick() - tickstart) < wait)
 8000c72:	46c0      	nop			@ (mov r8, r8)
 8000c74:	f7ff ffe0 	bl	8000c38 <HAL_GetTick>
 8000c78:	0002      	movs	r2, r0
 8000c7a:	68bb      	ldr	r3, [r7, #8]
 8000c7c:	1ad3      	subs	r3, r2, r3
 8000c7e:	68fa      	ldr	r2, [r7, #12]
 8000c80:	429a      	cmp	r2, r3
 8000c82:	d8f7      	bhi.n	8000c74 <HAL_Delay+0x28>
  {
  }
}
 8000c84:	46c0      	nop			@ (mov r8, r8)
 8000c86:	46c0      	nop			@ (mov r8, r8)
 8000c88:	46bd      	mov	sp, r7
 8000c8a:	b004      	add	sp, #16
 8000c8c:	bd80      	pop	{r7, pc}
 8000c8e:	46c0      	nop			@ (mov r8, r8)
 8000c90:	20000008 	.word	0x20000008

08000c94 <__NVIC_EnableIRQ>:
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
 8000c94:	b580      	push	{r7, lr}
 8000c96:	b082      	sub	sp, #8
 8000c98:	af00      	add	r7, sp, #0
 8000c9a:	0002      	movs	r2, r0
 8000c9c:	1dfb      	adds	r3, r7, #7
 8000c9e:	701a      	strb	r2, [r3, #0]
  if ((int32_t)(IRQn) >= 0)
 8000ca0:	1dfb      	adds	r3, r7, #7
 8000ca2:	781b      	ldrb	r3, [r3, #0]
 8000ca4:	2b7f      	cmp	r3, #127	@ 0x7f
 8000ca6:	d809      	bhi.n	8000cbc <__NVIC_EnableIRQ+0x28>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 8000ca8:	1dfb      	adds	r3, r7, #7
 8000caa:	781b      	ldrb	r3, [r3, #0]
 8000cac:	001a      	movs	r2, r3
 8000cae:	231f      	movs	r3, #31
 8000cb0:	401a      	ands	r2, r3
 8000cb2:	4b04      	ldr	r3, [pc, #16]	@ (8000cc4 <__NVIC_EnableIRQ+0x30>)
 8000cb4:	2101      	movs	r1, #1
 8000cb6:	4091      	lsls	r1, r2
 8000cb8:	000a      	movs	r2, r1
 8000cba:	601a      	str	r2, [r3, #0]
    __COMPILER_BARRIER();
  }
}
 8000cbc:	46c0      	nop			@ (mov r8, r8)
 8000cbe:	46bd      	mov	sp, r7
 8000cc0:	b002      	add	sp, #8
 8000cc2:	bd80      	pop	{r7, pc}
 8000cc4:	e000e100 	.word	0xe000e100

08000cc8 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8000cc8:	b590      	push	{r4, r7, lr}
 8000cca:	b083      	sub	sp, #12
 8000ccc:	af00      	add	r7, sp, #0
 8000cce:	0002      	movs	r2, r0
 8000cd0:	6039      	str	r1, [r7, #0]
 8000cd2:	1dfb      	adds	r3, r7, #7
 8000cd4:	701a      	strb	r2, [r3, #0]
  if ((int32_t)(IRQn) >= 0)
 8000cd6:	1dfb      	adds	r3, r7, #7
 8000cd8:	781b      	ldrb	r3, [r3, #0]
 8000cda:	2b7f      	cmp	r3, #127	@ 0x7f
 8000cdc:	d828      	bhi.n	8000d30 <__NVIC_SetPriority+0x68>
  {
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000cde:	4a2f      	ldr	r2, [pc, #188]	@ (8000d9c <__NVIC_SetPriority+0xd4>)
 8000ce0:	1dfb      	adds	r3, r7, #7
 8000ce2:	781b      	ldrb	r3, [r3, #0]
 8000ce4:	b25b      	sxtb	r3, r3
 8000ce6:	089b      	lsrs	r3, r3, #2
 8000ce8:	33c0      	adds	r3, #192	@ 0xc0
 8000cea:	009b      	lsls	r3, r3, #2
 8000cec:	589b      	ldr	r3, [r3, r2]
 8000cee:	1dfa      	adds	r2, r7, #7
 8000cf0:	7812      	ldrb	r2, [r2, #0]
 8000cf2:	0011      	movs	r1, r2
 8000cf4:	2203      	movs	r2, #3
 8000cf6:	400a      	ands	r2, r1
 8000cf8:	00d2      	lsls	r2, r2, #3
 8000cfa:	21ff      	movs	r1, #255	@ 0xff
 8000cfc:	4091      	lsls	r1, r2
 8000cfe:	000a      	movs	r2, r1
 8000d00:	43d2      	mvns	r2, r2
 8000d02:	401a      	ands	r2, r3
 8000d04:	0011      	movs	r1, r2
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 8000d06:	683b      	ldr	r3, [r7, #0]
 8000d08:	019b      	lsls	r3, r3, #6
 8000d0a:	22ff      	movs	r2, #255	@ 0xff
 8000d0c:	401a      	ands	r2, r3
 8000d0e:	1dfb      	adds	r3, r7, #7
 8000d10:	781b      	ldrb	r3, [r3, #0]
 8000d12:	0018      	movs	r0, r3
 8000d14:	2303      	movs	r3, #3
 8000d16:	4003      	ands	r3, r0
 8000d18:	00db      	lsls	r3, r3, #3
 8000d1a:	409a      	lsls	r2, r3
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000d1c:	481f      	ldr	r0, [pc, #124]	@ (8000d9c <__NVIC_SetPriority+0xd4>)
 8000d1e:	1dfb      	adds	r3, r7, #7
 8000d20:	781b      	ldrb	r3, [r3, #0]
 8000d22:	b25b      	sxtb	r3, r3
 8000d24:	089b      	lsrs	r3, r3, #2
 8000d26:	430a      	orrs	r2, r1
 8000d28:	33c0      	adds	r3, #192	@ 0xc0
 8000d2a:	009b      	lsls	r3, r3, #2
 8000d2c:	501a      	str	r2, [r3, r0]
  else
  {
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  }
}
 8000d2e:	e031      	b.n	8000d94 <__NVIC_SetPriority+0xcc>
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000d30:	4a1b      	ldr	r2, [pc, #108]	@ (8000da0 <__NVIC_SetPriority+0xd8>)
 8000d32:	1dfb      	adds	r3, r7, #7
 8000d34:	781b      	ldrb	r3, [r3, #0]
 8000d36:	0019      	movs	r1, r3
 8000d38:	230f      	movs	r3, #15
 8000d3a:	400b      	ands	r3, r1
 8000d3c:	3b08      	subs	r3, #8
 8000d3e:	089b      	lsrs	r3, r3, #2
 8000d40:	3306      	adds	r3, #6
 8000d42:	009b      	lsls	r3, r3, #2
 8000d44:	18d3      	adds	r3, r2, r3
 8000d46:	3304      	adds	r3, #4
 8000d48:	681b      	ldr	r3, [r3, #0]
 8000d4a:	1dfa      	adds	r2, r7, #7
 8000d4c:	7812      	ldrb	r2, [r2, #0]
 8000d4e:	0011      	movs	r1, r2
 8000d50:	2203      	movs	r2, #3
 8000d52:	400a      	ands	r2, r1
 8000d54:	00d2      	lsls	r2, r2, #3
 8000d56:	21ff      	movs	r1, #255	@ 0xff
 8000d58:	4091      	lsls	r1, r2
 8000d5a:	000a      	movs	r2, r1
 8000d5c:	43d2      	mvns	r2, r2
 8000d5e:	401a      	ands	r2, r3
 8000d60:	0011      	movs	r1, r2
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 8000d62:	683b      	ldr	r3, [r7, #0]
 8000d64:	019b      	lsls	r3, r3, #6
 8000d66:	22ff      	movs	r2, #255	@ 0xff
 8000d68:	401a      	ands	r2, r3
 8000d6a:	1dfb      	adds	r3, r7, #7
 8000d6c:	781b      	ldrb	r3, [r3, #0]
 8000d6e:	0018      	movs	r0, r3
 8000d70:	2303      	movs	r3, #3
 8000d72:	4003      	ands	r3, r0
 8000d74:	00db      	lsls	r3, r3, #3
 8000d76:	409a      	lsls	r2, r3
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000d78:	4809      	ldr	r0, [pc, #36]	@ (8000da0 <__NVIC_SetPriority+0xd8>)
 8000d7a:	1dfb      	adds	r3, r7, #7
 8000d7c:	781b      	ldrb	r3, [r3, #0]
 8000d7e:	001c      	movs	r4, r3
 8000d80:	230f      	movs	r3, #15
 8000d82:	4023      	ands	r3, r4
 8000d84:	3b08      	subs	r3, #8
 8000d86:	089b      	lsrs	r3, r3, #2
 8000d88:	430a      	orrs	r2, r1
 8000d8a:	3306      	adds	r3, #6
 8000d8c:	009b      	lsls	r3, r3, #2
 8000d8e:	18c3      	adds	r3, r0, r3
 8000d90:	3304      	adds	r3, #4
 8000d92:	601a      	str	r2, [r3, #0]
}
 8000d94:	46c0      	nop			@ (mov r8, r8)
 8000d96:	46bd      	mov	sp, r7
 8000d98:	b003      	add	sp, #12
 8000d9a:	bd90      	pop	{r4, r7, pc}
 8000d9c:	e000e100 	.word	0xe000e100
 8000da0:	e000ed00 	.word	0xe000ed00

08000da4 <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 8000da4:	b580      	push	{r7, lr}
 8000da6:	b082      	sub	sp, #8
 8000da8:	af00      	add	r7, sp, #0
 8000daa:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8000dac:	687b      	ldr	r3, [r7, #4]
 8000dae:	1e5a      	subs	r2, r3, #1
 8000db0:	2380      	movs	r3, #128	@ 0x80
 8000db2:	045b      	lsls	r3, r3, #17
 8000db4:	429a      	cmp	r2, r3
 8000db6:	d301      	bcc.n	8000dbc <SysTick_Config+0x18>
  {
    return (1UL);                                                   /* Reload value impossible */
 8000db8:	2301      	movs	r3, #1
 8000dba:	e010      	b.n	8000dde <SysTick_Config+0x3a>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8000dbc:	4b0a      	ldr	r3, [pc, #40]	@ (8000de8 <SysTick_Config+0x44>)
 8000dbe:	687a      	ldr	r2, [r7, #4]
 8000dc0:	3a01      	subs	r2, #1
 8000dc2:	605a      	str	r2, [r3, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 8000dc4:	2301      	movs	r3, #1
 8000dc6:	425b      	negs	r3, r3
 8000dc8:	2103      	movs	r1, #3
 8000dca:	0018      	movs	r0, r3
 8000dcc:	f7ff ff7c 	bl	8000cc8 <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 8000dd0:	4b05      	ldr	r3, [pc, #20]	@ (8000de8 <SysTick_Config+0x44>)
 8000dd2:	2200      	movs	r2, #0
 8000dd4:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 8000dd6:	4b04      	ldr	r3, [pc, #16]	@ (8000de8 <SysTick_Config+0x44>)
 8000dd8:	2207      	movs	r2, #7
 8000dda:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 8000ddc:	2300      	movs	r3, #0
}
 8000dde:	0018      	movs	r0, r3
 8000de0:	46bd      	mov	sp, r7
 8000de2:	b002      	add	sp, #8
 8000de4:	bd80      	pop	{r7, pc}
 8000de6:	46c0      	nop			@ (mov r8, r8)
 8000de8:	e000e010 	.word	0xe000e010

08000dec <HAL_NVIC_SetPriority>:
  *         with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
  *         no subpriority supported in Cortex M0+ based products.
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8000dec:	b580      	push	{r7, lr}
 8000dee:	b084      	sub	sp, #16
 8000df0:	af00      	add	r7, sp, #0
 8000df2:	60b9      	str	r1, [r7, #8]
 8000df4:	607a      	str	r2, [r7, #4]
 8000df6:	210f      	movs	r1, #15
 8000df8:	187b      	adds	r3, r7, r1
 8000dfa:	1c02      	adds	r2, r0, #0
 8000dfc:	701a      	strb	r2, [r3, #0]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(SubPriority);

  /* Check the parameters */
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  NVIC_SetPriority(IRQn, PreemptPriority);
 8000dfe:	68ba      	ldr	r2, [r7, #8]
 8000e00:	187b      	adds	r3, r7, r1
 8000e02:	781b      	ldrb	r3, [r3, #0]
 8000e04:	b25b      	sxtb	r3, r3
 8000e06:	0011      	movs	r1, r2
 8000e08:	0018      	movs	r0, r3
 8000e0a:	f7ff ff5d 	bl	8000cc8 <__NVIC_SetPriority>
}
 8000e0e:	46c0      	nop			@ (mov r8, r8)
 8000e10:	46bd      	mov	sp, r7
 8000e12:	b004      	add	sp, #16
 8000e14:	bd80      	pop	{r7, pc}

08000e16 <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 8000e16:	b580      	push	{r7, lr}
 8000e18:	b082      	sub	sp, #8
 8000e1a:	af00      	add	r7, sp, #0
 8000e1c:	0002      	movs	r2, r0
 8000e1e:	1dfb      	adds	r3, r7, #7
 8000e20:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 8000e22:	1dfb      	adds	r3, r7, #7
 8000e24:	781b      	ldrb	r3, [r3, #0]
 8000e26:	b25b      	sxtb	r3, r3
 8000e28:	0018      	movs	r0, r3
 8000e2a:	f7ff ff33 	bl	8000c94 <__NVIC_EnableIRQ>
}
 8000e2e:	46c0      	nop			@ (mov r8, r8)
 8000e30:	46bd      	mov	sp, r7
 8000e32:	b002      	add	sp, #8
 8000e34:	bd80      	pop	{r7, pc}

08000e36 <HAL_SYSTICK_Config>:
  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 8000e36:	b580      	push	{r7, lr}
 8000e38:	b082      	sub	sp, #8
 8000e3a:	af00      	add	r7, sp, #0
 8000e3c:	6078      	str	r0, [r7, #4]
  return SysTick_Config(TicksNumb);
 8000e3e:	687b      	ldr	r3, [r7, #4]
 8000e40:	0018      	movs	r0, r3
 8000e42:	f7ff ffaf 	bl	8000da4 <SysTick_Config>
 8000e46:	0003      	movs	r3, r0
}
 8000e48:	0018      	movs	r0, r3
 8000e4a:	46bd      	mov	sp, r7
 8000e4c:	b002      	add	sp, #8
 8000e4e:	bd80      	pop	{r7, pc}

08000e50 <HAL_DMA_Init>:
  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
  *             the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 8000e50:	b580      	push	{r7, lr}
 8000e52:	b082      	sub	sp, #8
 8000e54:	af00      	add	r7, sp, #0
 8000e56:	6078      	str	r0, [r7, #4]
  /* Check the DMA handle allocation */
  if (hdma == NULL)
 8000e58:	687b      	ldr	r3, [r7, #4]
 8000e5a:	2b00      	cmp	r3, #0
 8000e5c:	d101      	bne.n	8000e62 <HAL_DMA_Init+0x12>
  {
    return HAL_ERROR;
 8000e5e:	2301      	movs	r3, #1
 8000e60:	e077      	b.n	8000f52 <HAL_DMA_Init+0x102>
    /* DMA2 */
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
    hdma->DmaBaseAddress = DMA2;
  }
#else
  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
 8000e62:	687b      	ldr	r3, [r7, #4]
 8000e64:	681b      	ldr	r3, [r3, #0]
 8000e66:	4a3d      	ldr	r2, [pc, #244]	@ (8000f5c <HAL_DMA_Init+0x10c>)
 8000e68:	4694      	mov	ip, r2
 8000e6a:	4463      	add	r3, ip
 8000e6c:	2114      	movs	r1, #20
 8000e6e:	0018      	movs	r0, r3
 8000e70:	f7ff f946 	bl	8000100 <__udivsi3>
 8000e74:	0003      	movs	r3, r0
 8000e76:	009a      	lsls	r2, r3, #2
 8000e78:	687b      	ldr	r3, [r7, #4]
 8000e7a:	641a      	str	r2, [r3, #64]	@ 0x40
#endif /* DMA2 */

  /* Change DMA peripheral state */
  hdma->State = HAL_DMA_STATE_BUSY;
 8000e7c:	687b      	ldr	r3, [r7, #4]
 8000e7e:	2225      	movs	r2, #37	@ 0x25
 8000e80:	2102      	movs	r1, #2
 8000e82:	5499      	strb	r1, [r3, r2]

  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
  CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 8000e84:	687b      	ldr	r3, [r7, #4]
 8000e86:	681b      	ldr	r3, [r3, #0]
 8000e88:	681a      	ldr	r2, [r3, #0]
 8000e8a:	687b      	ldr	r3, [r7, #4]
 8000e8c:	681b      	ldr	r3, [r3, #0]
 8000e8e:	4934      	ldr	r1, [pc, #208]	@ (8000f60 <HAL_DMA_Init+0x110>)
 8000e90:	400a      	ands	r2, r1
 8000e92:	601a      	str	r2, [r3, #0]
                                  DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
                                  DMA_CCR_DIR   | DMA_CCR_MEM2MEM));

  /* Set the DMA Channel configuration */
  SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction           |                               \
 8000e94:	687b      	ldr	r3, [r7, #4]
 8000e96:	681b      	ldr	r3, [r3, #0]
 8000e98:	6819      	ldr	r1, [r3, #0]
 8000e9a:	687b      	ldr	r3, [r7, #4]
 8000e9c:	689a      	ldr	r2, [r3, #8]
 8000e9e:	687b      	ldr	r3, [r7, #4]
 8000ea0:	68db      	ldr	r3, [r3, #12]
 8000ea2:	431a      	orrs	r2, r3
 8000ea4:	687b      	ldr	r3, [r7, #4]
 8000ea6:	691b      	ldr	r3, [r3, #16]
 8000ea8:	431a      	orrs	r2, r3
 8000eaa:	687b      	ldr	r3, [r7, #4]
 8000eac:	695b      	ldr	r3, [r3, #20]
 8000eae:	431a      	orrs	r2, r3
 8000eb0:	687b      	ldr	r3, [r7, #4]
 8000eb2:	699b      	ldr	r3, [r3, #24]
 8000eb4:	431a      	orrs	r2, r3
 8000eb6:	687b      	ldr	r3, [r7, #4]
 8000eb8:	69db      	ldr	r3, [r3, #28]
 8000eba:	431a      	orrs	r2, r3
 8000ebc:	687b      	ldr	r3, [r7, #4]
 8000ebe:	6a1b      	ldr	r3, [r3, #32]
 8000ec0:	431a      	orrs	r2, r3
 8000ec2:	687b      	ldr	r3, [r7, #4]
 8000ec4:	681b      	ldr	r3, [r3, #0]
 8000ec6:	430a      	orrs	r2, r1
 8000ec8:	601a      	str	r2, [r3, #0]
                                hdma->Init.Mode                | hdma->Init.Priority));

  /* Initialize parameters for DMAMUX channel :
     DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
  */
  DMA_CalcDMAMUXChannelBaseAndMask(hdma);
 8000eca:	687b      	ldr	r3, [r7, #4]
 8000ecc:	0018      	movs	r0, r3
 8000ece:	f000 f979 	bl	80011c4 <DMA_CalcDMAMUXChannelBaseAndMask>

  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
 8000ed2:	687b      	ldr	r3, [r7, #4]
 8000ed4:	689a      	ldr	r2, [r3, #8]
 8000ed6:	2380      	movs	r3, #128	@ 0x80
 8000ed8:	01db      	lsls	r3, r3, #7
 8000eda:	429a      	cmp	r2, r3
 8000edc:	d102      	bne.n	8000ee4 <HAL_DMA_Init+0x94>
  {
    /* if memory to memory force the request to 0*/
    hdma->Init.Request = DMA_REQUEST_MEM2MEM;
 8000ede:	687b      	ldr	r3, [r7, #4]
 8000ee0:	2200      	movs	r2, #0
 8000ee2:	605a      	str	r2, [r3, #4]
  }

  /* Set peripheral request  to DMAMUX channel */
  hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
 8000ee4:	687b      	ldr	r3, [r7, #4]
 8000ee6:	685a      	ldr	r2, [r3, #4]
 8000ee8:	687b      	ldr	r3, [r7, #4]
 8000eea:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8000eec:	213f      	movs	r1, #63	@ 0x3f
 8000eee:	400a      	ands	r2, r1
 8000ef0:	601a      	str	r2, [r3, #0]

  /* Clear the DMAMUX synchro overrun flag */
  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 8000ef2:	687b      	ldr	r3, [r7, #4]
 8000ef4:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8000ef6:	687a      	ldr	r2, [r7, #4]
 8000ef8:	6cd2      	ldr	r2, [r2, #76]	@ 0x4c
 8000efa:	605a      	str	r2, [r3, #4]

  if (((hdma->Init.Request >  0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
 8000efc:	687b      	ldr	r3, [r7, #4]
 8000efe:	685b      	ldr	r3, [r3, #4]
 8000f00:	2b00      	cmp	r3, #0
 8000f02:	d011      	beq.n	8000f28 <HAL_DMA_Init+0xd8>
 8000f04:	687b      	ldr	r3, [r7, #4]
 8000f06:	685b      	ldr	r3, [r3, #4]
 8000f08:	2b04      	cmp	r3, #4
 8000f0a:	d80d      	bhi.n	8000f28 <HAL_DMA_Init+0xd8>
  {
    /* Initialize parameters for DMAMUX request generator :
       DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
    */
    DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
 8000f0c:	687b      	ldr	r3, [r7, #4]
 8000f0e:	0018      	movs	r0, r3
 8000f10:	f000 f984 	bl	800121c <DMA_CalcDMAMUXRequestGenBaseAndMask>

    /* Reset the DMAMUX request generator register*/
    hdma->DMAmuxRequestGen->RGCR = 0U;
 8000f14:	687b      	ldr	r3, [r7, #4]
 8000f16:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8000f18:	2200      	movs	r2, #0
 8000f1a:	601a      	str	r2, [r3, #0]

    /* Clear the DMAMUX request generator overrun flag */
    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 8000f1c:	687b      	ldr	r3, [r7, #4]
 8000f1e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8000f20:	687a      	ldr	r2, [r7, #4]
 8000f22:	6d92      	ldr	r2, [r2, #88]	@ 0x58
 8000f24:	605a      	str	r2, [r3, #4]
 8000f26:	e008      	b.n	8000f3a <HAL_DMA_Init+0xea>
  }
  else
  {
    hdma->DMAmuxRequestGen = 0U;
 8000f28:	687b      	ldr	r3, [r7, #4]
 8000f2a:	2200      	movs	r2, #0
 8000f2c:	651a      	str	r2, [r3, #80]	@ 0x50
    hdma->DMAmuxRequestGenStatus = 0U;
 8000f2e:	687b      	ldr	r3, [r7, #4]
 8000f30:	2200      	movs	r2, #0
 8000f32:	655a      	str	r2, [r3, #84]	@ 0x54
    hdma->DMAmuxRequestGenStatusMask = 0U;
 8000f34:	687b      	ldr	r3, [r7, #4]
 8000f36:	2200      	movs	r2, #0
 8000f38:	659a      	str	r2, [r3, #88]	@ 0x58
  }

  /* Initialize the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8000f3a:	687b      	ldr	r3, [r7, #4]
 8000f3c:	2200      	movs	r2, #0
 8000f3e:	63da      	str	r2, [r3, #60]	@ 0x3c

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 8000f40:	687b      	ldr	r3, [r7, #4]
 8000f42:	2225      	movs	r2, #37	@ 0x25
 8000f44:	2101      	movs	r1, #1
 8000f46:	5499      	strb	r1, [r3, r2]

  /* Release Lock */
  __HAL_UNLOCK(hdma);
 8000f48:	687b      	ldr	r3, [r7, #4]
 8000f4a:	2224      	movs	r2, #36	@ 0x24
 8000f4c:	2100      	movs	r1, #0
 8000f4e:	5499      	strb	r1, [r3, r2]

  return HAL_OK;
 8000f50:	2300      	movs	r3, #0
}
 8000f52:	0018      	movs	r0, r3
 8000f54:	46bd      	mov	sp, r7
 8000f56:	b002      	add	sp, #8
 8000f58:	bd80      	pop	{r7, pc}
 8000f5a:	46c0      	nop			@ (mov r8, r8)
 8000f5c:	bffdfff8 	.word	0xbffdfff8
 8000f60:	ffff800f 	.word	0xffff800f

08000f64 <HAL_DMA_Start_IT>:
  * @param DataLength The length of data to be transferred from source to destination
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
                                   uint32_t DataLength)
{
 8000f64:	b580      	push	{r7, lr}
 8000f66:	b086      	sub	sp, #24
 8000f68:	af00      	add	r7, sp, #0
 8000f6a:	60f8      	str	r0, [r7, #12]
 8000f6c:	60b9      	str	r1, [r7, #8]
 8000f6e:	607a      	str	r2, [r7, #4]
 8000f70:	603b      	str	r3, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 8000f72:	2317      	movs	r3, #23
 8000f74:	18fb      	adds	r3, r7, r3
 8000f76:	2200      	movs	r2, #0
 8000f78:	701a      	strb	r2, [r3, #0]

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Process locked */
  __HAL_LOCK(hdma);
 8000f7a:	68fb      	ldr	r3, [r7, #12]
 8000f7c:	2224      	movs	r2, #36	@ 0x24
 8000f7e:	5c9b      	ldrb	r3, [r3, r2]
 8000f80:	2b01      	cmp	r3, #1
 8000f82:	d101      	bne.n	8000f88 <HAL_DMA_Start_IT+0x24>
 8000f84:	2302      	movs	r3, #2
 8000f86:	e06f      	b.n	8001068 <HAL_DMA_Start_IT+0x104>
 8000f88:	68fb      	ldr	r3, [r7, #12]
 8000f8a:	2224      	movs	r2, #36	@ 0x24
 8000f8c:	2101      	movs	r1, #1
 8000f8e:	5499      	strb	r1, [r3, r2]

  if (hdma->State == HAL_DMA_STATE_READY)
 8000f90:	68fb      	ldr	r3, [r7, #12]
 8000f92:	2225      	movs	r2, #37	@ 0x25
 8000f94:	5c9b      	ldrb	r3, [r3, r2]
 8000f96:	b2db      	uxtb	r3, r3
 8000f98:	2b01      	cmp	r3, #1
 8000f9a:	d157      	bne.n	800104c <HAL_DMA_Start_IT+0xe8>
  {
    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 8000f9c:	68fb      	ldr	r3, [r7, #12]
 8000f9e:	2225      	movs	r2, #37	@ 0x25
 8000fa0:	2102      	movs	r1, #2
 8000fa2:	5499      	strb	r1, [r3, r2]
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8000fa4:	68fb      	ldr	r3, [r7, #12]
 8000fa6:	2200      	movs	r2, #0
 8000fa8:	63da      	str	r2, [r3, #60]	@ 0x3c

    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 8000faa:	68fb      	ldr	r3, [r7, #12]
 8000fac:	681b      	ldr	r3, [r3, #0]
 8000fae:	681a      	ldr	r2, [r3, #0]
 8000fb0:	68fb      	ldr	r3, [r7, #12]
 8000fb2:	681b      	ldr	r3, [r3, #0]
 8000fb4:	2101      	movs	r1, #1
 8000fb6:	438a      	bics	r2, r1
 8000fb8:	601a      	str	r2, [r3, #0]

    /* Configure the source, destination address and the data length & clear flags*/
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 8000fba:	683b      	ldr	r3, [r7, #0]
 8000fbc:	687a      	ldr	r2, [r7, #4]
 8000fbe:	68b9      	ldr	r1, [r7, #8]
 8000fc0:	68f8      	ldr	r0, [r7, #12]
 8000fc2:	f000 f8bf 	bl	8001144 <DMA_SetConfig>

    /* Enable the transfer complete interrupt */
    /* Enable the transfer Error interrupt */
    if (NULL != hdma->XferHalfCpltCallback)
 8000fc6:	68fb      	ldr	r3, [r7, #12]
 8000fc8:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8000fca:	2b00      	cmp	r3, #0
 8000fcc:	d008      	beq.n	8000fe0 <HAL_DMA_Start_IT+0x7c>
    {
      /* Enable the Half transfer complete interrupt as well */
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8000fce:	68fb      	ldr	r3, [r7, #12]
 8000fd0:	681b      	ldr	r3, [r3, #0]
 8000fd2:	681a      	ldr	r2, [r3, #0]
 8000fd4:	68fb      	ldr	r3, [r7, #12]
 8000fd6:	681b      	ldr	r3, [r3, #0]
 8000fd8:	210e      	movs	r1, #14
 8000fda:	430a      	orrs	r2, r1
 8000fdc:	601a      	str	r2, [r3, #0]
 8000fde:	e00f      	b.n	8001000 <HAL_DMA_Start_IT+0x9c>
    }
    else
    {
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 8000fe0:	68fb      	ldr	r3, [r7, #12]
 8000fe2:	681b      	ldr	r3, [r3, #0]
 8000fe4:	681a      	ldr	r2, [r3, #0]
 8000fe6:	68fb      	ldr	r3, [r7, #12]
 8000fe8:	681b      	ldr	r3, [r3, #0]
 8000fea:	2104      	movs	r1, #4
 8000fec:	438a      	bics	r2, r1
 8000fee:	601a      	str	r2, [r3, #0]
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 8000ff0:	68fb      	ldr	r3, [r7, #12]
 8000ff2:	681b      	ldr	r3, [r3, #0]
 8000ff4:	681a      	ldr	r2, [r3, #0]
 8000ff6:	68fb      	ldr	r3, [r7, #12]
 8000ff8:	681b      	ldr	r3, [r3, #0]
 8000ffa:	210a      	movs	r1, #10
 8000ffc:	430a      	orrs	r2, r1
 8000ffe:	601a      	str	r2, [r3, #0]
    }

    /* Check if DMAMUX Synchronization is enabled*/
    if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
 8001000:	68fb      	ldr	r3, [r7, #12]
 8001002:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8001004:	681a      	ldr	r2, [r3, #0]
 8001006:	2380      	movs	r3, #128	@ 0x80
 8001008:	025b      	lsls	r3, r3, #9
 800100a:	4013      	ands	r3, r2
 800100c:	d008      	beq.n	8001020 <HAL_DMA_Start_IT+0xbc>
    {
      /* Enable DMAMUX sync overrun IT*/
      hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
 800100e:	68fb      	ldr	r3, [r7, #12]
 8001010:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8001012:	681a      	ldr	r2, [r3, #0]
 8001014:	68fb      	ldr	r3, [r7, #12]
 8001016:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8001018:	2180      	movs	r1, #128	@ 0x80
 800101a:	0049      	lsls	r1, r1, #1
 800101c:	430a      	orrs	r2, r1
 800101e:	601a      	str	r2, [r3, #0]
    }

    if (hdma->DMAmuxRequestGen != 0U)
 8001020:	68fb      	ldr	r3, [r7, #12]
 8001022:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8001024:	2b00      	cmp	r3, #0
 8001026:	d008      	beq.n	800103a <HAL_DMA_Start_IT+0xd6>
    {
      /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
      /* enable the request gen overrun IT*/
      hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
 8001028:	68fb      	ldr	r3, [r7, #12]
 800102a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800102c:	681a      	ldr	r2, [r3, #0]
 800102e:	68fb      	ldr	r3, [r7, #12]
 8001030:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8001032:	2180      	movs	r1, #128	@ 0x80
 8001034:	0049      	lsls	r1, r1, #1
 8001036:	430a      	orrs	r2, r1
 8001038:	601a      	str	r2, [r3, #0]
    }

    /* Enable the Peripheral */
    __HAL_DMA_ENABLE(hdma);
 800103a:	68fb      	ldr	r3, [r7, #12]
 800103c:	681b      	ldr	r3, [r3, #0]
 800103e:	681a      	ldr	r2, [r3, #0]
 8001040:	68fb      	ldr	r3, [r7, #12]
 8001042:	681b      	ldr	r3, [r3, #0]
 8001044:	2101      	movs	r1, #1
 8001046:	430a      	orrs	r2, r1
 8001048:	601a      	str	r2, [r3, #0]
 800104a:	e00a      	b.n	8001062 <HAL_DMA_Start_IT+0xfe>
  }
  else
  {
    /* Change the error code */
    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
 800104c:	68fb      	ldr	r3, [r7, #12]
 800104e:	2280      	movs	r2, #128	@ 0x80
 8001050:	63da      	str	r2, [r3, #60]	@ 0x3c

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8001052:	68fb      	ldr	r3, [r7, #12]
 8001054:	2224      	movs	r2, #36	@ 0x24
 8001056:	2100      	movs	r1, #0
 8001058:	5499      	strb	r1, [r3, r2]

    /* Return error status */
    status = HAL_ERROR;
 800105a:	2317      	movs	r3, #23
 800105c:	18fb      	adds	r3, r7, r3
 800105e:	2201      	movs	r2, #1
 8001060:	701a      	strb	r2, [r3, #0]
  }

  return status;
 8001062:	2317      	movs	r3, #23
 8001064:	18fb      	adds	r3, r7, r3
 8001066:	781b      	ldrb	r3, [r3, #0]
}
 8001068:	0018      	movs	r0, r3
 800106a:	46bd      	mov	sp, r7
 800106c:	b006      	add	sp, #24
 800106e:	bd80      	pop	{r7, pc}

08001070 <HAL_DMA_Abort_IT>:
  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
  *             the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
 8001070:	b580      	push	{r7, lr}
 8001072:	b084      	sub	sp, #16
 8001074:	af00      	add	r7, sp, #0
 8001076:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 8001078:	210f      	movs	r1, #15
 800107a:	187b      	adds	r3, r7, r1
 800107c:	2200      	movs	r2, #0
 800107e:	701a      	strb	r2, [r3, #0]

  if (hdma->State != HAL_DMA_STATE_BUSY)
 8001080:	687b      	ldr	r3, [r7, #4]
 8001082:	2225      	movs	r2, #37	@ 0x25
 8001084:	5c9b      	ldrb	r3, [r3, r2]
 8001086:	b2db      	uxtb	r3, r3
 8001088:	2b02      	cmp	r3, #2
 800108a:	d006      	beq.n	800109a <HAL_DMA_Abort_IT+0x2a>
  {
    /* no transfer ongoing */
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 800108c:	687b      	ldr	r3, [r7, #4]
 800108e:	2204      	movs	r2, #4
 8001090:	63da      	str	r2, [r3, #60]	@ 0x3c

    status = HAL_ERROR;
 8001092:	187b      	adds	r3, r7, r1
 8001094:	2201      	movs	r2, #1
 8001096:	701a      	strb	r2, [r3, #0]
 8001098:	e049      	b.n	800112e <HAL_DMA_Abort_IT+0xbe>
  }
  else
  {
    /* Disable DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 800109a:	687b      	ldr	r3, [r7, #4]
 800109c:	681b      	ldr	r3, [r3, #0]
 800109e:	681a      	ldr	r2, [r3, #0]
 80010a0:	687b      	ldr	r3, [r7, #4]
 80010a2:	681b      	ldr	r3, [r3, #0]
 80010a4:	210e      	movs	r1, #14
 80010a6:	438a      	bics	r2, r1
 80010a8:	601a      	str	r2, [r3, #0]

    /* Disable the channel */
    __HAL_DMA_DISABLE(hdma);
 80010aa:	687b      	ldr	r3, [r7, #4]
 80010ac:	681b      	ldr	r3, [r3, #0]
 80010ae:	681a      	ldr	r2, [r3, #0]
 80010b0:	687b      	ldr	r3, [r7, #4]
 80010b2:	681b      	ldr	r3, [r3, #0]
 80010b4:	2101      	movs	r1, #1
 80010b6:	438a      	bics	r2, r1
 80010b8:	601a      	str	r2, [r3, #0]

    /* disable the DMAMUX sync overrun IT*/
    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
 80010ba:	687b      	ldr	r3, [r7, #4]
 80010bc:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80010be:	681a      	ldr	r2, [r3, #0]
 80010c0:	687b      	ldr	r3, [r7, #4]
 80010c2:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80010c4:	491d      	ldr	r1, [pc, #116]	@ (800113c <HAL_DMA_Abort_IT+0xcc>)
 80010c6:	400a      	ands	r2, r1
 80010c8:	601a      	str	r2, [r3, #0]

    /* Clear all flags */
#if defined(DMA2)
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
    __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
 80010ca:	4b1d      	ldr	r3, [pc, #116]	@ (8001140 <HAL_DMA_Abort_IT+0xd0>)
 80010cc:	6859      	ldr	r1, [r3, #4]
 80010ce:	687b      	ldr	r3, [r7, #4]
 80010d0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80010d2:	221c      	movs	r2, #28
 80010d4:	4013      	ands	r3, r2
 80010d6:	2201      	movs	r2, #1
 80010d8:	409a      	lsls	r2, r3
 80010da:	4b19      	ldr	r3, [pc, #100]	@ (8001140 <HAL_DMA_Abort_IT+0xd0>)
 80010dc:	430a      	orrs	r2, r1
 80010de:	605a      	str	r2, [r3, #4]
#endif /* DMA2 */

    /* Clear the DMAMUX synchro overrun flag */
    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 80010e0:	687b      	ldr	r3, [r7, #4]
 80010e2:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 80010e4:	687a      	ldr	r2, [r7, #4]
 80010e6:	6cd2      	ldr	r2, [r2, #76]	@ 0x4c
 80010e8:	605a      	str	r2, [r3, #4]

    if (hdma->DMAmuxRequestGen != 0U)
 80010ea:	687b      	ldr	r3, [r7, #4]
 80010ec:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80010ee:	2b00      	cmp	r3, #0
 80010f0:	d00c      	beq.n	800110c <HAL_DMA_Abort_IT+0x9c>
    {
      /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
      /* disable the request gen overrun IT*/
      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
 80010f2:	687b      	ldr	r3, [r7, #4]
 80010f4:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80010f6:	681a      	ldr	r2, [r3, #0]
 80010f8:	687b      	ldr	r3, [r7, #4]
 80010fa:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80010fc:	490f      	ldr	r1, [pc, #60]	@ (800113c <HAL_DMA_Abort_IT+0xcc>)
 80010fe:	400a      	ands	r2, r1
 8001100:	601a      	str	r2, [r3, #0]

      /* Clear the DMAMUX request generator overrun flag */
      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 8001102:	687b      	ldr	r3, [r7, #4]
 8001104:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8001106:	687a      	ldr	r2, [r7, #4]
 8001108:	6d92      	ldr	r2, [r2, #88]	@ 0x58
 800110a:	605a      	str	r2, [r3, #4]
    }

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 800110c:	687b      	ldr	r3, [r7, #4]
 800110e:	2225      	movs	r2, #37	@ 0x25
 8001110:	2101      	movs	r1, #1
 8001112:	5499      	strb	r1, [r3, r2]

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8001114:	687b      	ldr	r3, [r7, #4]
 8001116:	2224      	movs	r2, #36	@ 0x24
 8001118:	2100      	movs	r1, #0
 800111a:	5499      	strb	r1, [r3, r2]

    /* Call User Abort callback */
    if (hdma->XferAbortCallback != NULL)
 800111c:	687b      	ldr	r3, [r7, #4]
 800111e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8001120:	2b00      	cmp	r3, #0
 8001122:	d004      	beq.n	800112e <HAL_DMA_Abort_IT+0xbe>
    {
      hdma->XferAbortCallback(hdma);
 8001124:	687b      	ldr	r3, [r7, #4]
 8001126:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8001128:	687a      	ldr	r2, [r7, #4]
 800112a:	0010      	movs	r0, r2
 800112c:	4798      	blx	r3
    }
  }
  return status;
 800112e:	230f      	movs	r3, #15
 8001130:	18fb      	adds	r3, r7, r3
 8001132:	781b      	ldrb	r3, [r3, #0]
}
 8001134:	0018      	movs	r0, r3
 8001136:	46bd      	mov	sp, r7
 8001138:	b004      	add	sp, #16
 800113a:	bd80      	pop	{r7, pc}
 800113c:	fffffeff 	.word	0xfffffeff
 8001140:	40020000 	.word	0x40020000

08001144 <DMA_SetConfig>:
  * @param DstAddress The destination memory Buffer address
  * @param DataLength The length of data to be transferred from source to destination
  * @retval HAL status
  */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 8001144:	b580      	push	{r7, lr}
 8001146:	b084      	sub	sp, #16
 8001148:	af00      	add	r7, sp, #0
 800114a:	60f8      	str	r0, [r7, #12]
 800114c:	60b9      	str	r1, [r7, #8]
 800114e:	607a      	str	r2, [r7, #4]
 8001150:	603b      	str	r3, [r7, #0]
  /* Clear the DMAMUX synchro overrun flag */
  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 8001152:	68fb      	ldr	r3, [r7, #12]
 8001154:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8001156:	68fa      	ldr	r2, [r7, #12]
 8001158:	6cd2      	ldr	r2, [r2, #76]	@ 0x4c
 800115a:	605a      	str	r2, [r3, #4]

  if (hdma->DMAmuxRequestGen != 0U)
 800115c:	68fb      	ldr	r3, [r7, #12]
 800115e:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8001160:	2b00      	cmp	r3, #0
 8001162:	d004      	beq.n	800116e <DMA_SetConfig+0x2a>
  {
    /* Clear the DMAMUX request generator overrun flag */
    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 8001164:	68fb      	ldr	r3, [r7, #12]
 8001166:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8001168:	68fa      	ldr	r2, [r7, #12]
 800116a:	6d92      	ldr	r2, [r2, #88]	@ 0x58
 800116c:	605a      	str	r2, [r3, #4]

  /* Clear all flags */
#if defined(DMA2)
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
  __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
 800116e:	4b14      	ldr	r3, [pc, #80]	@ (80011c0 <DMA_SetConfig+0x7c>)
 8001170:	6859      	ldr	r1, [r3, #4]
 8001172:	68fb      	ldr	r3, [r7, #12]
 8001174:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8001176:	221c      	movs	r2, #28
 8001178:	4013      	ands	r3, r2
 800117a:	2201      	movs	r2, #1
 800117c:	409a      	lsls	r2, r3
 800117e:	4b10      	ldr	r3, [pc, #64]	@ (80011c0 <DMA_SetConfig+0x7c>)
 8001180:	430a      	orrs	r2, r1
 8001182:	605a      	str	r2, [r3, #4]
#endif /* DMA2 */

  /* Configure DMA Channel data length */
  hdma->Instance->CNDTR = DataLength;
 8001184:	68fb      	ldr	r3, [r7, #12]
 8001186:	681b      	ldr	r3, [r3, #0]
 8001188:	683a      	ldr	r2, [r7, #0]
 800118a:	605a      	str	r2, [r3, #4]

  /* Memory to Peripheral */
  if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 800118c:	68fb      	ldr	r3, [r7, #12]
 800118e:	689b      	ldr	r3, [r3, #8]
 8001190:	2b10      	cmp	r3, #16
 8001192:	d108      	bne.n	80011a6 <DMA_SetConfig+0x62>
  {
    /* Configure DMA Channel destination address */
    hdma->Instance->CPAR = DstAddress;
 8001194:	68fb      	ldr	r3, [r7, #12]
 8001196:	681b      	ldr	r3, [r3, #0]
 8001198:	687a      	ldr	r2, [r7, #4]
 800119a:	609a      	str	r2, [r3, #8]

    /* Configure DMA Channel source address */
    hdma->Instance->CMAR = SrcAddress;
 800119c:	68fb      	ldr	r3, [r7, #12]
 800119e:	681b      	ldr	r3, [r3, #0]
 80011a0:	68ba      	ldr	r2, [r7, #8]
 80011a2:	60da      	str	r2, [r3, #12]
    hdma->Instance->CPAR = SrcAddress;

    /* Configure DMA Channel destination address */
    hdma->Instance->CMAR = DstAddress;
  }
}
 80011a4:	e007      	b.n	80011b6 <DMA_SetConfig+0x72>
    hdma->Instance->CPAR = SrcAddress;
 80011a6:	68fb      	ldr	r3, [r7, #12]
 80011a8:	681b      	ldr	r3, [r3, #0]
 80011aa:	68ba      	ldr	r2, [r7, #8]
 80011ac:	609a      	str	r2, [r3, #8]
    hdma->Instance->CMAR = DstAddress;
 80011ae:	68fb      	ldr	r3, [r7, #12]
 80011b0:	681b      	ldr	r3, [r3, #0]
 80011b2:	687a      	ldr	r2, [r7, #4]
 80011b4:	60da      	str	r2, [r3, #12]
}
 80011b6:	46c0      	nop			@ (mov r8, r8)
 80011b8:	46bd      	mov	sp, r7
 80011ba:	b004      	add	sp, #16
 80011bc:	bd80      	pop	{r7, pc}
 80011be:	46c0      	nop			@ (mov r8, r8)
 80011c0:	40020000 	.word	0x40020000

080011c4 <DMA_CalcDMAMUXChannelBaseAndMask>:
  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
  *             the configuration information for the specified DMA Channel.
  * @retval None
  */
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
{
 80011c4:	b580      	push	{r7, lr}
 80011c6:	b084      	sub	sp, #16
 80011c8:	af00      	add	r7, sp, #0
 80011ca:	6078      	str	r0, [r7, #4]
    /* Prepare channel_number used for DMAmuxChannelStatusMask computation */
    channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U);
  }
#else
  /* Associate a DMA Channel to a DMAMUX channel */
  hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
 80011cc:	687b      	ldr	r3, [r7, #4]
 80011ce:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80011d0:	089b      	lsrs	r3, r3, #2
 80011d2:	4a10      	ldr	r2, [pc, #64]	@ (8001214 <DMA_CalcDMAMUXChannelBaseAndMask+0x50>)
 80011d4:	4694      	mov	ip, r2
 80011d6:	4463      	add	r3, ip
 80011d8:	009b      	lsls	r3, r3, #2
 80011da:	001a      	movs	r2, r3
 80011dc:	687b      	ldr	r3, [r7, #4]
 80011de:	645a      	str	r2, [r3, #68]	@ 0x44

  /* Prepare channel_number used for DMAmuxChannelStatusMask computation */
  channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
 80011e0:	687b      	ldr	r3, [r7, #4]
 80011e2:	681b      	ldr	r3, [r3, #0]
 80011e4:	001a      	movs	r2, r3
 80011e6:	23ff      	movs	r3, #255	@ 0xff
 80011e8:	4013      	ands	r3, r2
 80011ea:	3b08      	subs	r3, #8
 80011ec:	2114      	movs	r1, #20
 80011ee:	0018      	movs	r0, r3
 80011f0:	f7fe ff86 	bl	8000100 <__udivsi3>
 80011f4:	0003      	movs	r3, r0
 80011f6:	60fb      	str	r3, [r7, #12]
#endif /* DMA2 */

  /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */
  hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
 80011f8:	687b      	ldr	r3, [r7, #4]
 80011fa:	4a07      	ldr	r2, [pc, #28]	@ (8001218 <DMA_CalcDMAMUXChannelBaseAndMask+0x54>)
 80011fc:	649a      	str	r2, [r3, #72]	@ 0x48

  /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */
  hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
 80011fe:	68fb      	ldr	r3, [r7, #12]
 8001200:	221f      	movs	r2, #31
 8001202:	4013      	ands	r3, r2
 8001204:	2201      	movs	r2, #1
 8001206:	409a      	lsls	r2, r3
 8001208:	687b      	ldr	r3, [r7, #4]
 800120a:	64da      	str	r2, [r3, #76]	@ 0x4c
}
 800120c:	46c0      	nop			@ (mov r8, r8)
 800120e:	46bd      	mov	sp, r7
 8001210:	b004      	add	sp, #16
 8001212:	bd80      	pop	{r7, pc}
 8001214:	10008200 	.word	0x10008200
 8001218:	40020880 	.word	0x40020880

0800121c <DMA_CalcDMAMUXRequestGenBaseAndMask>:
  *             the configuration information for the specified DMA Channel.
  * @retval None
  */

static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
{
 800121c:	b580      	push	{r7, lr}
 800121e:	b084      	sub	sp, #16
 8001220:	af00      	add	r7, sp, #0
 8001222:	6078      	str	r0, [r7, #4]
  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
 8001224:	687b      	ldr	r3, [r7, #4]
 8001226:	685b      	ldr	r3, [r3, #4]
 8001228:	223f      	movs	r2, #63	@ 0x3f
 800122a:	4013      	ands	r3, r2
 800122c:	60fb      	str	r3, [r7, #12]

  /* DMA Channels are connected to DMAMUX1 request generator blocks*/
  hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
 800122e:	68fb      	ldr	r3, [r7, #12]
 8001230:	4a0a      	ldr	r2, [pc, #40]	@ (800125c <DMA_CalcDMAMUXRequestGenBaseAndMask+0x40>)
 8001232:	4694      	mov	ip, r2
 8001234:	4463      	add	r3, ip
 8001236:	009b      	lsls	r3, r3, #2
 8001238:	001a      	movs	r2, r3
 800123a:	687b      	ldr	r3, [r7, #4]
 800123c:	651a      	str	r2, [r3, #80]	@ 0x50

  hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
 800123e:	687b      	ldr	r3, [r7, #4]
 8001240:	4a07      	ldr	r2, [pc, #28]	@ (8001260 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x44>)
 8001242:	655a      	str	r2, [r3, #84]	@ 0x54

  /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
  hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
 8001244:	68fb      	ldr	r3, [r7, #12]
 8001246:	3b01      	subs	r3, #1
 8001248:	2203      	movs	r2, #3
 800124a:	4013      	ands	r3, r2
 800124c:	2201      	movs	r2, #1
 800124e:	409a      	lsls	r2, r3
 8001250:	687b      	ldr	r3, [r7, #4]
 8001252:	659a      	str	r2, [r3, #88]	@ 0x58
}
 8001254:	46c0      	nop			@ (mov r8, r8)
 8001256:	46bd      	mov	sp, r7
 8001258:	b004      	add	sp, #16
 800125a:	bd80      	pop	{r7, pc}
 800125c:	1000823f 	.word	0x1000823f
 8001260:	40020940 	.word	0x40020940

08001264 <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8001264:	b580      	push	{r7, lr}
 8001266:	b086      	sub	sp, #24
 8001268:	af00      	add	r7, sp, #0
 800126a:	6078      	str	r0, [r7, #4]
 800126c:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00u;
 800126e:	2300      	movs	r3, #0
 8001270:	617b      	str	r3, [r7, #20]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8001272:	e147      	b.n	8001504 <HAL_GPIO_Init+0x2a0>
  {
    /* Get current io position */
    iocurrent = (GPIO_Init->Pin) & (1uL << position);
 8001274:	683b      	ldr	r3, [r7, #0]
 8001276:	681b      	ldr	r3, [r3, #0]
 8001278:	2101      	movs	r1, #1
 800127a:	697a      	ldr	r2, [r7, #20]
 800127c:	4091      	lsls	r1, r2
 800127e:	000a      	movs	r2, r1
 8001280:	4013      	ands	r3, r2
 8001282:	60fb      	str	r3, [r7, #12]

    if (iocurrent != 0x00u)
 8001284:	68fb      	ldr	r3, [r7, #12]
 8001286:	2b00      	cmp	r3, #0
 8001288:	d100      	bne.n	800128c <HAL_GPIO_Init+0x28>
 800128a:	e138      	b.n	80014fe <HAL_GPIO_Init+0x29a>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
 800128c:	683b      	ldr	r3, [r7, #0]
 800128e:	685b      	ldr	r3, [r3, #4]
 8001290:	2203      	movs	r2, #3
 8001292:	4013      	ands	r3, r2
 8001294:	2b01      	cmp	r3, #1
 8001296:	d005      	beq.n	80012a4 <HAL_GPIO_Init+0x40>
 8001298:	683b      	ldr	r3, [r7, #0]
 800129a:	685b      	ldr	r3, [r3, #4]
 800129c:	2203      	movs	r2, #3
 800129e:	4013      	ands	r3, r2
 80012a0:	2b02      	cmp	r3, #2
 80012a2:	d130      	bne.n	8001306 <HAL_GPIO_Init+0xa2>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));

        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 80012a4:	687b      	ldr	r3, [r7, #4]
 80012a6:	689b      	ldr	r3, [r3, #8]
 80012a8:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
 80012aa:	697b      	ldr	r3, [r7, #20]
 80012ac:	005b      	lsls	r3, r3, #1
 80012ae:	2203      	movs	r2, #3
 80012b0:	409a      	lsls	r2, r3
 80012b2:	0013      	movs	r3, r2
 80012b4:	43da      	mvns	r2, r3
 80012b6:	693b      	ldr	r3, [r7, #16]
 80012b8:	4013      	ands	r3, r2
 80012ba:	613b      	str	r3, [r7, #16]
        temp |= (GPIO_Init->Speed << (position * 2u));
 80012bc:	683b      	ldr	r3, [r7, #0]
 80012be:	68da      	ldr	r2, [r3, #12]
 80012c0:	697b      	ldr	r3, [r7, #20]
 80012c2:	005b      	lsls	r3, r3, #1
 80012c4:	409a      	lsls	r2, r3
 80012c6:	0013      	movs	r3, r2
 80012c8:	693a      	ldr	r2, [r7, #16]
 80012ca:	4313      	orrs	r3, r2
 80012cc:	613b      	str	r3, [r7, #16]
        GPIOx->OSPEEDR = temp;
 80012ce:	687b      	ldr	r3, [r7, #4]
 80012d0:	693a      	ldr	r2, [r7, #16]
 80012d2:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 80012d4:	687b      	ldr	r3, [r7, #4]
 80012d6:	685b      	ldr	r3, [r3, #4]
 80012d8:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_OTYPER_OT0 << position) ;
 80012da:	2201      	movs	r2, #1
 80012dc:	697b      	ldr	r3, [r7, #20]
 80012de:	409a      	lsls	r2, r3
 80012e0:	0013      	movs	r3, r2
 80012e2:	43da      	mvns	r2, r3
 80012e4:	693b      	ldr	r3, [r7, #16]
 80012e6:	4013      	ands	r3, r2
 80012e8:	613b      	str	r3, [r7, #16]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 80012ea:	683b      	ldr	r3, [r7, #0]
 80012ec:	685b      	ldr	r3, [r3, #4]
 80012ee:	091b      	lsrs	r3, r3, #4
 80012f0:	2201      	movs	r2, #1
 80012f2:	401a      	ands	r2, r3
 80012f4:	697b      	ldr	r3, [r7, #20]
 80012f6:	409a      	lsls	r2, r3
 80012f8:	0013      	movs	r3, r2
 80012fa:	693a      	ldr	r2, [r7, #16]
 80012fc:	4313      	orrs	r3, r2
 80012fe:	613b      	str	r3, [r7, #16]
        GPIOx->OTYPER = temp;
 8001300:	687b      	ldr	r3, [r7, #4]
 8001302:	693a      	ldr	r2, [r7, #16]
 8001304:	605a      	str	r2, [r3, #4]
      }

      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 8001306:	683b      	ldr	r3, [r7, #0]
 8001308:	685b      	ldr	r3, [r3, #4]
 800130a:	2203      	movs	r2, #3
 800130c:	4013      	ands	r3, r2
 800130e:	2b03      	cmp	r3, #3
 8001310:	d017      	beq.n	8001342 <HAL_GPIO_Init+0xde>
      {
        /* Check the Pull parameter */
        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

        /* Activate the Pull-up or Pull down resistor for the current IO */
        temp = GPIOx->PUPDR;
 8001312:	687b      	ldr	r3, [r7, #4]
 8001314:	68db      	ldr	r3, [r3, #12]
 8001316:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
 8001318:	697b      	ldr	r3, [r7, #20]
 800131a:	005b      	lsls	r3, r3, #1
 800131c:	2203      	movs	r2, #3
 800131e:	409a      	lsls	r2, r3
 8001320:	0013      	movs	r3, r2
 8001322:	43da      	mvns	r2, r3
 8001324:	693b      	ldr	r3, [r7, #16]
 8001326:	4013      	ands	r3, r2
 8001328:	613b      	str	r3, [r7, #16]
        temp |= ((GPIO_Init->Pull) << (position * 2u));
 800132a:	683b      	ldr	r3, [r7, #0]
 800132c:	689a      	ldr	r2, [r3, #8]
 800132e:	697b      	ldr	r3, [r7, #20]
 8001330:	005b      	lsls	r3, r3, #1
 8001332:	409a      	lsls	r2, r3
 8001334:	0013      	movs	r3, r2
 8001336:	693a      	ldr	r2, [r7, #16]
 8001338:	4313      	orrs	r3, r2
 800133a:	613b      	str	r3, [r7, #16]
        GPIOx->PUPDR = temp;
 800133c:	687b      	ldr	r3, [r7, #4]
 800133e:	693a      	ldr	r2, [r7, #16]
 8001340:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8001342:	683b      	ldr	r3, [r7, #0]
 8001344:	685b      	ldr	r3, [r3, #4]
 8001346:	2203      	movs	r2, #3
 8001348:	4013      	ands	r3, r2
 800134a:	2b02      	cmp	r3, #2
 800134c:	d123      	bne.n	8001396 <HAL_GPIO_Init+0x132>
        /* Check the Alternate function parameters */
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3u];
 800134e:	697b      	ldr	r3, [r7, #20]
 8001350:	08da      	lsrs	r2, r3, #3
 8001352:	687b      	ldr	r3, [r7, #4]
 8001354:	3208      	adds	r2, #8
 8001356:	0092      	lsls	r2, r2, #2
 8001358:	58d3      	ldr	r3, [r2, r3]
 800135a:	613b      	str	r3, [r7, #16]
        temp &= ~(0xFu << ((position & 0x07u) * 4u));
 800135c:	697b      	ldr	r3, [r7, #20]
 800135e:	2207      	movs	r2, #7
 8001360:	4013      	ands	r3, r2
 8001362:	009b      	lsls	r3, r3, #2
 8001364:	220f      	movs	r2, #15
 8001366:	409a      	lsls	r2, r3
 8001368:	0013      	movs	r3, r2
 800136a:	43da      	mvns	r2, r3
 800136c:	693b      	ldr	r3, [r7, #16]
 800136e:	4013      	ands	r3, r2
 8001370:	613b      	str	r3, [r7, #16]
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
 8001372:	683b      	ldr	r3, [r7, #0]
 8001374:	691a      	ldr	r2, [r3, #16]
 8001376:	697b      	ldr	r3, [r7, #20]
 8001378:	2107      	movs	r1, #7
 800137a:	400b      	ands	r3, r1
 800137c:	009b      	lsls	r3, r3, #2
 800137e:	409a      	lsls	r2, r3
 8001380:	0013      	movs	r3, r2
 8001382:	693a      	ldr	r2, [r7, #16]
 8001384:	4313      	orrs	r3, r2
 8001386:	613b      	str	r3, [r7, #16]
        GPIOx->AFR[position >> 3u] = temp;
 8001388:	697b      	ldr	r3, [r7, #20]
 800138a:	08da      	lsrs	r2, r3, #3
 800138c:	687b      	ldr	r3, [r7, #4]
 800138e:	3208      	adds	r2, #8
 8001390:	0092      	lsls	r2, r2, #2
 8001392:	6939      	ldr	r1, [r7, #16]
 8001394:	50d1      	str	r1, [r2, r3]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 8001396:	687b      	ldr	r3, [r7, #4]
 8001398:	681b      	ldr	r3, [r3, #0]
 800139a:	613b      	str	r3, [r7, #16]
      temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
 800139c:	697b      	ldr	r3, [r7, #20]
 800139e:	005b      	lsls	r3, r3, #1
 80013a0:	2203      	movs	r2, #3
 80013a2:	409a      	lsls	r2, r3
 80013a4:	0013      	movs	r3, r2
 80013a6:	43da      	mvns	r2, r3
 80013a8:	693b      	ldr	r3, [r7, #16]
 80013aa:	4013      	ands	r3, r2
 80013ac:	613b      	str	r3, [r7, #16]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
 80013ae:	683b      	ldr	r3, [r7, #0]
 80013b0:	685b      	ldr	r3, [r3, #4]
 80013b2:	2203      	movs	r2, #3
 80013b4:	401a      	ands	r2, r3
 80013b6:	697b      	ldr	r3, [r7, #20]
 80013b8:	005b      	lsls	r3, r3, #1
 80013ba:	409a      	lsls	r2, r3
 80013bc:	0013      	movs	r3, r2
 80013be:	693a      	ldr	r2, [r7, #16]
 80013c0:	4313      	orrs	r3, r2
 80013c2:	613b      	str	r3, [r7, #16]
      GPIOx->MODER = temp;
 80013c4:	687b      	ldr	r3, [r7, #4]
 80013c6:	693a      	ldr	r2, [r7, #16]
 80013c8:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
 80013ca:	683b      	ldr	r3, [r7, #0]
 80013cc:	685a      	ldr	r2, [r3, #4]
 80013ce:	23c0      	movs	r3, #192	@ 0xc0
 80013d0:	029b      	lsls	r3, r3, #10
 80013d2:	4013      	ands	r3, r2
 80013d4:	d100      	bne.n	80013d8 <HAL_GPIO_Init+0x174>
 80013d6:	e092      	b.n	80014fe <HAL_GPIO_Init+0x29a>
      {
        temp = EXTI->EXTICR[position >> 2u];
 80013d8:	4a50      	ldr	r2, [pc, #320]	@ (800151c <HAL_GPIO_Init+0x2b8>)
 80013da:	697b      	ldr	r3, [r7, #20]
 80013dc:	089b      	lsrs	r3, r3, #2
 80013de:	3318      	adds	r3, #24
 80013e0:	009b      	lsls	r3, r3, #2
 80013e2:	589b      	ldr	r3, [r3, r2]
 80013e4:	613b      	str	r3, [r7, #16]
        temp &= ~(0x0FuL << (8u * (position & 0x03u)));
 80013e6:	697b      	ldr	r3, [r7, #20]
 80013e8:	2203      	movs	r2, #3
 80013ea:	4013      	ands	r3, r2
 80013ec:	00db      	lsls	r3, r3, #3
 80013ee:	220f      	movs	r2, #15
 80013f0:	409a      	lsls	r2, r3
 80013f2:	0013      	movs	r3, r2
 80013f4:	43da      	mvns	r2, r3
 80013f6:	693b      	ldr	r3, [r7, #16]
 80013f8:	4013      	ands	r3, r2
 80013fa:	613b      	str	r3, [r7, #16]
        temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)));
 80013fc:	687a      	ldr	r2, [r7, #4]
 80013fe:	23a0      	movs	r3, #160	@ 0xa0
 8001400:	05db      	lsls	r3, r3, #23
 8001402:	429a      	cmp	r2, r3
 8001404:	d013      	beq.n	800142e <HAL_GPIO_Init+0x1ca>
 8001406:	687b      	ldr	r3, [r7, #4]
 8001408:	4a45      	ldr	r2, [pc, #276]	@ (8001520 <HAL_GPIO_Init+0x2bc>)
 800140a:	4293      	cmp	r3, r2
 800140c:	d00d      	beq.n	800142a <HAL_GPIO_Init+0x1c6>
 800140e:	687b      	ldr	r3, [r7, #4]
 8001410:	4a44      	ldr	r2, [pc, #272]	@ (8001524 <HAL_GPIO_Init+0x2c0>)
 8001412:	4293      	cmp	r3, r2
 8001414:	d007      	beq.n	8001426 <HAL_GPIO_Init+0x1c2>
 8001416:	687b      	ldr	r3, [r7, #4]
 8001418:	4a43      	ldr	r2, [pc, #268]	@ (8001528 <HAL_GPIO_Init+0x2c4>)
 800141a:	4293      	cmp	r3, r2
 800141c:	d101      	bne.n	8001422 <HAL_GPIO_Init+0x1be>
 800141e:	2303      	movs	r3, #3
 8001420:	e006      	b.n	8001430 <HAL_GPIO_Init+0x1cc>
 8001422:	2305      	movs	r3, #5
 8001424:	e004      	b.n	8001430 <HAL_GPIO_Init+0x1cc>
 8001426:	2302      	movs	r3, #2
 8001428:	e002      	b.n	8001430 <HAL_GPIO_Init+0x1cc>
 800142a:	2301      	movs	r3, #1
 800142c:	e000      	b.n	8001430 <HAL_GPIO_Init+0x1cc>
 800142e:	2300      	movs	r3, #0
 8001430:	697a      	ldr	r2, [r7, #20]
 8001432:	2103      	movs	r1, #3
 8001434:	400a      	ands	r2, r1
 8001436:	00d2      	lsls	r2, r2, #3
 8001438:	4093      	lsls	r3, r2
 800143a:	693a      	ldr	r2, [r7, #16]
 800143c:	4313      	orrs	r3, r2
 800143e:	613b      	str	r3, [r7, #16]
        EXTI->EXTICR[position >> 2u] = temp;
 8001440:	4936      	ldr	r1, [pc, #216]	@ (800151c <HAL_GPIO_Init+0x2b8>)
 8001442:	697b      	ldr	r3, [r7, #20]
 8001444:	089b      	lsrs	r3, r3, #2
 8001446:	3318      	adds	r3, #24
 8001448:	009b      	lsls	r3, r3, #2
 800144a:	693a      	ldr	r2, [r7, #16]
 800144c:	505a      	str	r2, [r3, r1]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR1;
 800144e:	4b33      	ldr	r3, [pc, #204]	@ (800151c <HAL_GPIO_Init+0x2b8>)
 8001450:	681b      	ldr	r3, [r3, #0]
 8001452:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001454:	68fb      	ldr	r3, [r7, #12]
 8001456:	43da      	mvns	r2, r3
 8001458:	693b      	ldr	r3, [r7, #16]
 800145a:	4013      	ands	r3, r2
 800145c:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
 800145e:	683b      	ldr	r3, [r7, #0]
 8001460:	685a      	ldr	r2, [r3, #4]
 8001462:	2380      	movs	r3, #128	@ 0x80
 8001464:	035b      	lsls	r3, r3, #13
 8001466:	4013      	ands	r3, r2
 8001468:	d003      	beq.n	8001472 <HAL_GPIO_Init+0x20e>
        {
          temp |= iocurrent;
 800146a:	693a      	ldr	r2, [r7, #16]
 800146c:	68fb      	ldr	r3, [r7, #12]
 800146e:	4313      	orrs	r3, r2
 8001470:	613b      	str	r3, [r7, #16]
        }
        EXTI->RTSR1 = temp;
 8001472:	4b2a      	ldr	r3, [pc, #168]	@ (800151c <HAL_GPIO_Init+0x2b8>)
 8001474:	693a      	ldr	r2, [r7, #16]
 8001476:	601a      	str	r2, [r3, #0]

        temp = EXTI->FTSR1;
 8001478:	4b28      	ldr	r3, [pc, #160]	@ (800151c <HAL_GPIO_Init+0x2b8>)
 800147a:	685b      	ldr	r3, [r3, #4]
 800147c:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 800147e:	68fb      	ldr	r3, [r7, #12]
 8001480:	43da      	mvns	r2, r3
 8001482:	693b      	ldr	r3, [r7, #16]
 8001484:	4013      	ands	r3, r2
 8001486:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
 8001488:	683b      	ldr	r3, [r7, #0]
 800148a:	685a      	ldr	r2, [r3, #4]
 800148c:	2380      	movs	r3, #128	@ 0x80
 800148e:	039b      	lsls	r3, r3, #14
 8001490:	4013      	ands	r3, r2
 8001492:	d003      	beq.n	800149c <HAL_GPIO_Init+0x238>
        {
          temp |= iocurrent;
 8001494:	693a      	ldr	r2, [r7, #16]
 8001496:	68fb      	ldr	r3, [r7, #12]
 8001498:	4313      	orrs	r3, r2
 800149a:	613b      	str	r3, [r7, #16]
        }
        EXTI->FTSR1 = temp;
 800149c:	4b1f      	ldr	r3, [pc, #124]	@ (800151c <HAL_GPIO_Init+0x2b8>)
 800149e:	693a      	ldr	r2, [r7, #16]
 80014a0:	605a      	str	r2, [r3, #4]

        /* Clear EXTI line configuration */
        temp = EXTI->EMR1;
 80014a2:	4a1e      	ldr	r2, [pc, #120]	@ (800151c <HAL_GPIO_Init+0x2b8>)
 80014a4:	2384      	movs	r3, #132	@ 0x84
 80014a6:	58d3      	ldr	r3, [r2, r3]
 80014a8:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 80014aa:	68fb      	ldr	r3, [r7, #12]
 80014ac:	43da      	mvns	r2, r3
 80014ae:	693b      	ldr	r3, [r7, #16]
 80014b0:	4013      	ands	r3, r2
 80014b2:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
 80014b4:	683b      	ldr	r3, [r7, #0]
 80014b6:	685a      	ldr	r2, [r3, #4]
 80014b8:	2380      	movs	r3, #128	@ 0x80
 80014ba:	029b      	lsls	r3, r3, #10
 80014bc:	4013      	ands	r3, r2
 80014be:	d003      	beq.n	80014c8 <HAL_GPIO_Init+0x264>
        {
          temp |= iocurrent;
 80014c0:	693a      	ldr	r2, [r7, #16]
 80014c2:	68fb      	ldr	r3, [r7, #12]
 80014c4:	4313      	orrs	r3, r2
 80014c6:	613b      	str	r3, [r7, #16]
        }
        EXTI->EMR1 = temp;
 80014c8:	4914      	ldr	r1, [pc, #80]	@ (800151c <HAL_GPIO_Init+0x2b8>)
 80014ca:	2284      	movs	r2, #132	@ 0x84
 80014cc:	693b      	ldr	r3, [r7, #16]
 80014ce:	508b      	str	r3, [r1, r2]

        temp = EXTI->IMR1;
 80014d0:	4a12      	ldr	r2, [pc, #72]	@ (800151c <HAL_GPIO_Init+0x2b8>)
 80014d2:	2380      	movs	r3, #128	@ 0x80
 80014d4:	58d3      	ldr	r3, [r2, r3]
 80014d6:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 80014d8:	68fb      	ldr	r3, [r7, #12]
 80014da:	43da      	mvns	r2, r3
 80014dc:	693b      	ldr	r3, [r7, #16]
 80014de:	4013      	ands	r3, r2
 80014e0:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
 80014e2:	683b      	ldr	r3, [r7, #0]
 80014e4:	685a      	ldr	r2, [r3, #4]
 80014e6:	2380      	movs	r3, #128	@ 0x80
 80014e8:	025b      	lsls	r3, r3, #9
 80014ea:	4013      	ands	r3, r2
 80014ec:	d003      	beq.n	80014f6 <HAL_GPIO_Init+0x292>
        {
          temp |= iocurrent;
 80014ee:	693a      	ldr	r2, [r7, #16]
 80014f0:	68fb      	ldr	r3, [r7, #12]
 80014f2:	4313      	orrs	r3, r2
 80014f4:	613b      	str	r3, [r7, #16]
        }
        EXTI->IMR1 = temp;
 80014f6:	4909      	ldr	r1, [pc, #36]	@ (800151c <HAL_GPIO_Init+0x2b8>)
 80014f8:	2280      	movs	r2, #128	@ 0x80
 80014fa:	693b      	ldr	r3, [r7, #16]
 80014fc:	508b      	str	r3, [r1, r2]
      }
    }

    position++;
 80014fe:	697b      	ldr	r3, [r7, #20]
 8001500:	3301      	adds	r3, #1
 8001502:	617b      	str	r3, [r7, #20]
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8001504:	683b      	ldr	r3, [r7, #0]
 8001506:	681a      	ldr	r2, [r3, #0]
 8001508:	697b      	ldr	r3, [r7, #20]
 800150a:	40da      	lsrs	r2, r3
 800150c:	1e13      	subs	r3, r2, #0
 800150e:	d000      	beq.n	8001512 <HAL_GPIO_Init+0x2ae>
 8001510:	e6b0      	b.n	8001274 <HAL_GPIO_Init+0x10>
  }
}
 8001512:	46c0      	nop			@ (mov r8, r8)
 8001514:	46c0      	nop			@ (mov r8, r8)
 8001516:	46bd      	mov	sp, r7
 8001518:	b006      	add	sp, #24
 800151a:	bd80      	pop	{r7, pc}
 800151c:	40021800 	.word	0x40021800
 8001520:	50000400 	.word	0x50000400
 8001524:	50000800 	.word	0x50000800
 8001528:	50000c00 	.word	0x50000c00

0800152c <HAL_PWREx_ControlVoltageScaling>:
  *        cleared before returning the status. If the flag is not cleared within
  *        6 microseconds, HAL_TIMEOUT status is reported.
  * @retval HAL Status
  */
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
 800152c:	b580      	push	{r7, lr}
 800152e:	b084      	sub	sp, #16
 8001530:	af00      	add	r7, sp, #0
 8001532:	6078      	str	r0, [r7, #4]
  uint32_t wait_loop_index;

  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));

  /* Modify voltage scaling range */
  MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
 8001534:	4b19      	ldr	r3, [pc, #100]	@ (800159c <HAL_PWREx_ControlVoltageScaling+0x70>)
 8001536:	681b      	ldr	r3, [r3, #0]
 8001538:	4a19      	ldr	r2, [pc, #100]	@ (80015a0 <HAL_PWREx_ControlVoltageScaling+0x74>)
 800153a:	4013      	ands	r3, r2
 800153c:	0019      	movs	r1, r3
 800153e:	4b17      	ldr	r3, [pc, #92]	@ (800159c <HAL_PWREx_ControlVoltageScaling+0x70>)
 8001540:	687a      	ldr	r2, [r7, #4]
 8001542:	430a      	orrs	r2, r1
 8001544:	601a      	str	r2, [r3, #0]

  /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */
  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
 8001546:	687a      	ldr	r2, [r7, #4]
 8001548:	2380      	movs	r3, #128	@ 0x80
 800154a:	009b      	lsls	r3, r3, #2
 800154c:	429a      	cmp	r2, r3
 800154e:	d11f      	bne.n	8001590 <HAL_PWREx_ControlVoltageScaling+0x64>
  {
    /* Set timeout value */
    wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
 8001550:	4b14      	ldr	r3, [pc, #80]	@ (80015a4 <HAL_PWREx_ControlVoltageScaling+0x78>)
 8001552:	681a      	ldr	r2, [r3, #0]
 8001554:	0013      	movs	r3, r2
 8001556:	005b      	lsls	r3, r3, #1
 8001558:	189b      	adds	r3, r3, r2
 800155a:	005b      	lsls	r3, r3, #1
 800155c:	4912      	ldr	r1, [pc, #72]	@ (80015a8 <HAL_PWREx_ControlVoltageScaling+0x7c>)
 800155e:	0018      	movs	r0, r3
 8001560:	f7fe fdce 	bl	8000100 <__udivsi3>
 8001564:	0003      	movs	r3, r0
 8001566:	3301      	adds	r3, #1
 8001568:	60fb      	str	r3, [r7, #12]

    /* Wait until VOSF is reset */
    while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
 800156a:	e008      	b.n	800157e <HAL_PWREx_ControlVoltageScaling+0x52>
    {
      if (wait_loop_index != 0U)
 800156c:	68fb      	ldr	r3, [r7, #12]
 800156e:	2b00      	cmp	r3, #0
 8001570:	d003      	beq.n	800157a <HAL_PWREx_ControlVoltageScaling+0x4e>
      {
        wait_loop_index--;
 8001572:	68fb      	ldr	r3, [r7, #12]
 8001574:	3b01      	subs	r3, #1
 8001576:	60fb      	str	r3, [r7, #12]
 8001578:	e001      	b.n	800157e <HAL_PWREx_ControlVoltageScaling+0x52>
      }
      else
      {
        return HAL_TIMEOUT;
 800157a:	2303      	movs	r3, #3
 800157c:	e009      	b.n	8001592 <HAL_PWREx_ControlVoltageScaling+0x66>
    while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
 800157e:	4b07      	ldr	r3, [pc, #28]	@ (800159c <HAL_PWREx_ControlVoltageScaling+0x70>)
 8001580:	695a      	ldr	r2, [r3, #20]
 8001582:	2380      	movs	r3, #128	@ 0x80
 8001584:	00db      	lsls	r3, r3, #3
 8001586:	401a      	ands	r2, r3
 8001588:	2380      	movs	r3, #128	@ 0x80
 800158a:	00db      	lsls	r3, r3, #3
 800158c:	429a      	cmp	r2, r3
 800158e:	d0ed      	beq.n	800156c <HAL_PWREx_ControlVoltageScaling+0x40>
      }
    }
  }

  return HAL_OK;
 8001590:	2300      	movs	r3, #0
}
 8001592:	0018      	movs	r0, r3
 8001594:	46bd      	mov	sp, r7
 8001596:	b004      	add	sp, #16
 8001598:	bd80      	pop	{r7, pc}
 800159a:	46c0      	nop			@ (mov r8, r8)
 800159c:	40007000 	.word	0x40007000
 80015a0:	fffff9ff 	.word	0xfffff9ff
 80015a4:	20000000 	.word	0x20000000
 80015a8:	000f4240 	.word	0x000f4240

080015ac <HAL_RCC_OscConfig>:
  *         supported by this function. User should request a transition to LSE Off
  *         first and then to LSE On or LSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 80015ac:	b580      	push	{r7, lr}
 80015ae:	b088      	sub	sp, #32
 80015b0:	af00      	add	r7, sp, #0
 80015b2:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  uint32_t temp_sysclksrc;
  uint32_t temp_pllckcfg;

  /* Check Null pointer */
  if (RCC_OscInitStruct == NULL)
 80015b4:	687b      	ldr	r3, [r7, #4]
 80015b6:	2b00      	cmp	r3, #0
 80015b8:	d101      	bne.n	80015be <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 80015ba:	2301      	movs	r3, #1
 80015bc:	e2f3      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  /*------------------------------- HSE Configuration ------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 80015be:	687b      	ldr	r3, [r7, #4]
 80015c0:	681b      	ldr	r3, [r3, #0]
 80015c2:	2201      	movs	r2, #1
 80015c4:	4013      	ands	r3, r2
 80015c6:	d100      	bne.n	80015ca <HAL_RCC_OscConfig+0x1e>
 80015c8:	e07c      	b.n	80016c4 <HAL_RCC_OscConfig+0x118>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 80015ca:	4bc3      	ldr	r3, [pc, #780]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80015cc:	689b      	ldr	r3, [r3, #8]
 80015ce:	2238      	movs	r2, #56	@ 0x38
 80015d0:	4013      	ands	r3, r2
 80015d2:	61bb      	str	r3, [r7, #24]
    temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
 80015d4:	4bc0      	ldr	r3, [pc, #768]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80015d6:	68db      	ldr	r3, [r3, #12]
 80015d8:	2203      	movs	r2, #3
 80015da:	4013      	ands	r3, r2
 80015dc:	617b      	str	r3, [r7, #20]

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE))
 80015de:	69bb      	ldr	r3, [r7, #24]
 80015e0:	2b10      	cmp	r3, #16
 80015e2:	d102      	bne.n	80015ea <HAL_RCC_OscConfig+0x3e>
 80015e4:	697b      	ldr	r3, [r7, #20]
 80015e6:	2b03      	cmp	r3, #3
 80015e8:	d002      	beq.n	80015f0 <HAL_RCC_OscConfig+0x44>
        || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
 80015ea:	69bb      	ldr	r3, [r7, #24]
 80015ec:	2b08      	cmp	r3, #8
 80015ee:	d10b      	bne.n	8001608 <HAL_RCC_OscConfig+0x5c>
    {
      if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80015f0:	4bb9      	ldr	r3, [pc, #740]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80015f2:	681a      	ldr	r2, [r3, #0]
 80015f4:	2380      	movs	r3, #128	@ 0x80
 80015f6:	029b      	lsls	r3, r3, #10
 80015f8:	4013      	ands	r3, r2
 80015fa:	d062      	beq.n	80016c2 <HAL_RCC_OscConfig+0x116>
 80015fc:	687b      	ldr	r3, [r7, #4]
 80015fe:	685b      	ldr	r3, [r3, #4]
 8001600:	2b00      	cmp	r3, #0
 8001602:	d15e      	bne.n	80016c2 <HAL_RCC_OscConfig+0x116>
      {
        return HAL_ERROR;
 8001604:	2301      	movs	r3, #1
 8001606:	e2ce      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8001608:	687b      	ldr	r3, [r7, #4]
 800160a:	685a      	ldr	r2, [r3, #4]
 800160c:	2380      	movs	r3, #128	@ 0x80
 800160e:	025b      	lsls	r3, r3, #9
 8001610:	429a      	cmp	r2, r3
 8001612:	d107      	bne.n	8001624 <HAL_RCC_OscConfig+0x78>
 8001614:	4bb0      	ldr	r3, [pc, #704]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001616:	681a      	ldr	r2, [r3, #0]
 8001618:	4baf      	ldr	r3, [pc, #700]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800161a:	2180      	movs	r1, #128	@ 0x80
 800161c:	0249      	lsls	r1, r1, #9
 800161e:	430a      	orrs	r2, r1
 8001620:	601a      	str	r2, [r3, #0]
 8001622:	e020      	b.n	8001666 <HAL_RCC_OscConfig+0xba>
 8001624:	687b      	ldr	r3, [r7, #4]
 8001626:	685a      	ldr	r2, [r3, #4]
 8001628:	23a0      	movs	r3, #160	@ 0xa0
 800162a:	02db      	lsls	r3, r3, #11
 800162c:	429a      	cmp	r2, r3
 800162e:	d10e      	bne.n	800164e <HAL_RCC_OscConfig+0xa2>
 8001630:	4ba9      	ldr	r3, [pc, #676]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001632:	681a      	ldr	r2, [r3, #0]
 8001634:	4ba8      	ldr	r3, [pc, #672]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001636:	2180      	movs	r1, #128	@ 0x80
 8001638:	02c9      	lsls	r1, r1, #11
 800163a:	430a      	orrs	r2, r1
 800163c:	601a      	str	r2, [r3, #0]
 800163e:	4ba6      	ldr	r3, [pc, #664]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001640:	681a      	ldr	r2, [r3, #0]
 8001642:	4ba5      	ldr	r3, [pc, #660]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001644:	2180      	movs	r1, #128	@ 0x80
 8001646:	0249      	lsls	r1, r1, #9
 8001648:	430a      	orrs	r2, r1
 800164a:	601a      	str	r2, [r3, #0]
 800164c:	e00b      	b.n	8001666 <HAL_RCC_OscConfig+0xba>
 800164e:	4ba2      	ldr	r3, [pc, #648]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001650:	681a      	ldr	r2, [r3, #0]
 8001652:	4ba1      	ldr	r3, [pc, #644]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001654:	49a1      	ldr	r1, [pc, #644]	@ (80018dc <HAL_RCC_OscConfig+0x330>)
 8001656:	400a      	ands	r2, r1
 8001658:	601a      	str	r2, [r3, #0]
 800165a:	4b9f      	ldr	r3, [pc, #636]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800165c:	681a      	ldr	r2, [r3, #0]
 800165e:	4b9e      	ldr	r3, [pc, #632]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001660:	499f      	ldr	r1, [pc, #636]	@ (80018e0 <HAL_RCC_OscConfig+0x334>)
 8001662:	400a      	ands	r2, r1
 8001664:	601a      	str	r2, [r3, #0]

      /* Check the HSE State */
      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 8001666:	687b      	ldr	r3, [r7, #4]
 8001668:	685b      	ldr	r3, [r3, #4]
 800166a:	2b00      	cmp	r3, #0
 800166c:	d014      	beq.n	8001698 <HAL_RCC_OscConfig+0xec>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800166e:	f7ff fae3 	bl	8000c38 <HAL_GetTick>
 8001672:	0003      	movs	r3, r0
 8001674:	613b      	str	r3, [r7, #16]

        /* Wait till HSE is ready */
        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8001676:	e008      	b.n	800168a <HAL_RCC_OscConfig+0xde>
        {
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8001678:	f7ff fade 	bl	8000c38 <HAL_GetTick>
 800167c:	0002      	movs	r2, r0
 800167e:	693b      	ldr	r3, [r7, #16]
 8001680:	1ad3      	subs	r3, r2, r3
 8001682:	2b64      	cmp	r3, #100	@ 0x64
 8001684:	d901      	bls.n	800168a <HAL_RCC_OscConfig+0xde>
          {
            return HAL_TIMEOUT;
 8001686:	2303      	movs	r3, #3
 8001688:	e28d      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 800168a:	4b93      	ldr	r3, [pc, #588]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800168c:	681a      	ldr	r2, [r3, #0]
 800168e:	2380      	movs	r3, #128	@ 0x80
 8001690:	029b      	lsls	r3, r3, #10
 8001692:	4013      	ands	r3, r2
 8001694:	d0f0      	beq.n	8001678 <HAL_RCC_OscConfig+0xcc>
 8001696:	e015      	b.n	80016c4 <HAL_RCC_OscConfig+0x118>
        }
      }
      else
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001698:	f7ff face 	bl	8000c38 <HAL_GetTick>
 800169c:	0003      	movs	r3, r0
 800169e:	613b      	str	r3, [r7, #16]

        /* Wait till HSE is disabled */
        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 80016a0:	e008      	b.n	80016b4 <HAL_RCC_OscConfig+0x108>
        {
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 80016a2:	f7ff fac9 	bl	8000c38 <HAL_GetTick>
 80016a6:	0002      	movs	r2, r0
 80016a8:	693b      	ldr	r3, [r7, #16]
 80016aa:	1ad3      	subs	r3, r2, r3
 80016ac:	2b64      	cmp	r3, #100	@ 0x64
 80016ae:	d901      	bls.n	80016b4 <HAL_RCC_OscConfig+0x108>
          {
            return HAL_TIMEOUT;
 80016b0:	2303      	movs	r3, #3
 80016b2:	e278      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 80016b4:	4b88      	ldr	r3, [pc, #544]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80016b6:	681a      	ldr	r2, [r3, #0]
 80016b8:	2380      	movs	r3, #128	@ 0x80
 80016ba:	029b      	lsls	r3, r3, #10
 80016bc:	4013      	ands	r3, r2
 80016be:	d1f0      	bne.n	80016a2 <HAL_RCC_OscConfig+0xf6>
 80016c0:	e000      	b.n	80016c4 <HAL_RCC_OscConfig+0x118>
      if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80016c2:	46c0      	nop			@ (mov r8, r8)
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 80016c4:	687b      	ldr	r3, [r7, #4]
 80016c6:	681b      	ldr	r3, [r3, #0]
 80016c8:	2202      	movs	r2, #2
 80016ca:	4013      	ands	r3, r2
 80016cc:	d100      	bne.n	80016d0 <HAL_RCC_OscConfig+0x124>
 80016ce:	e099      	b.n	8001804 <HAL_RCC_OscConfig+0x258>
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
    assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));

    /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */
    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 80016d0:	4b81      	ldr	r3, [pc, #516]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80016d2:	689b      	ldr	r3, [r3, #8]
 80016d4:	2238      	movs	r2, #56	@ 0x38
 80016d6:	4013      	ands	r3, r2
 80016d8:	61bb      	str	r3, [r7, #24]
    temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
 80016da:	4b7f      	ldr	r3, [pc, #508]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80016dc:	68db      	ldr	r3, [r3, #12]
 80016de:	2203      	movs	r2, #3
 80016e0:	4013      	ands	r3, r2
 80016e2:	617b      	str	r3, [r7, #20]
    if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI))
 80016e4:	69bb      	ldr	r3, [r7, #24]
 80016e6:	2b10      	cmp	r3, #16
 80016e8:	d102      	bne.n	80016f0 <HAL_RCC_OscConfig+0x144>
 80016ea:	697b      	ldr	r3, [r7, #20]
 80016ec:	2b02      	cmp	r3, #2
 80016ee:	d002      	beq.n	80016f6 <HAL_RCC_OscConfig+0x14a>
        || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
 80016f0:	69bb      	ldr	r3, [r7, #24]
 80016f2:	2b00      	cmp	r3, #0
 80016f4:	d135      	bne.n	8001762 <HAL_RCC_OscConfig+0x1b6>
    {
      /* When HSI is used as system clock or as PLL input clock it can not be disabled */
      if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 80016f6:	4b78      	ldr	r3, [pc, #480]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80016f8:	681a      	ldr	r2, [r3, #0]
 80016fa:	2380      	movs	r3, #128	@ 0x80
 80016fc:	00db      	lsls	r3, r3, #3
 80016fe:	4013      	ands	r3, r2
 8001700:	d005      	beq.n	800170e <HAL_RCC_OscConfig+0x162>
 8001702:	687b      	ldr	r3, [r7, #4]
 8001704:	68db      	ldr	r3, [r3, #12]
 8001706:	2b00      	cmp	r3, #0
 8001708:	d101      	bne.n	800170e <HAL_RCC_OscConfig+0x162>
      {
        return HAL_ERROR;
 800170a:	2301      	movs	r3, #1
 800170c:	e24b      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 800170e:	4b72      	ldr	r3, [pc, #456]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001710:	685b      	ldr	r3, [r3, #4]
 8001712:	4a74      	ldr	r2, [pc, #464]	@ (80018e4 <HAL_RCC_OscConfig+0x338>)
 8001714:	4013      	ands	r3, r2
 8001716:	0019      	movs	r1, r3
 8001718:	687b      	ldr	r3, [r7, #4]
 800171a:	695b      	ldr	r3, [r3, #20]
 800171c:	021a      	lsls	r2, r3, #8
 800171e:	4b6e      	ldr	r3, [pc, #440]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001720:	430a      	orrs	r2, r1
 8001722:	605a      	str	r2, [r3, #4]

        if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
 8001724:	69bb      	ldr	r3, [r7, #24]
 8001726:	2b00      	cmp	r3, #0
 8001728:	d112      	bne.n	8001750 <HAL_RCC_OscConfig+0x1a4>
        {
          /* Adjust the HSI16 division factor */
          __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
 800172a:	4b6b      	ldr	r3, [pc, #428]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800172c:	681b      	ldr	r3, [r3, #0]
 800172e:	4a6e      	ldr	r2, [pc, #440]	@ (80018e8 <HAL_RCC_OscConfig+0x33c>)
 8001730:	4013      	ands	r3, r2
 8001732:	0019      	movs	r1, r3
 8001734:	687b      	ldr	r3, [r7, #4]
 8001736:	691a      	ldr	r2, [r3, #16]
 8001738:	4b67      	ldr	r3, [pc, #412]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800173a:	430a      	orrs	r2, r1
 800173c:	601a      	str	r2, [r3, #0]

          /* Update the SystemCoreClock global variable with HSISYS value  */
          SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
 800173e:	4b66      	ldr	r3, [pc, #408]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001740:	681b      	ldr	r3, [r3, #0]
 8001742:	0adb      	lsrs	r3, r3, #11
 8001744:	2207      	movs	r2, #7
 8001746:	4013      	ands	r3, r2
 8001748:	4a68      	ldr	r2, [pc, #416]	@ (80018ec <HAL_RCC_OscConfig+0x340>)
 800174a:	40da      	lsrs	r2, r3
 800174c:	4b68      	ldr	r3, [pc, #416]	@ (80018f0 <HAL_RCC_OscConfig+0x344>)
 800174e:	601a      	str	r2, [r3, #0]
        }

        /* Adapt Systick interrupt period */
        if (HAL_InitTick(uwTickPrio) != HAL_OK)
 8001750:	4b68      	ldr	r3, [pc, #416]	@ (80018f4 <HAL_RCC_OscConfig+0x348>)
 8001752:	681b      	ldr	r3, [r3, #0]
 8001754:	0018      	movs	r0, r3
 8001756:	f7ff fa13 	bl	8000b80 <HAL_InitTick>
 800175a:	1e03      	subs	r3, r0, #0
 800175c:	d051      	beq.n	8001802 <HAL_RCC_OscConfig+0x256>
        {
          return HAL_ERROR;
 800175e:	2301      	movs	r3, #1
 8001760:	e221      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
      }
    }
    else
    {
      /* Check the HSI State */
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8001762:	687b      	ldr	r3, [r7, #4]
 8001764:	68db      	ldr	r3, [r3, #12]
 8001766:	2b00      	cmp	r3, #0
 8001768:	d030      	beq.n	80017cc <HAL_RCC_OscConfig+0x220>
      {
        /* Configure the HSI16 division factor */
        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
 800176a:	4b5b      	ldr	r3, [pc, #364]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800176c:	681b      	ldr	r3, [r3, #0]
 800176e:	4a5e      	ldr	r2, [pc, #376]	@ (80018e8 <HAL_RCC_OscConfig+0x33c>)
 8001770:	4013      	ands	r3, r2
 8001772:	0019      	movs	r1, r3
 8001774:	687b      	ldr	r3, [r7, #4]
 8001776:	691a      	ldr	r2, [r3, #16]
 8001778:	4b57      	ldr	r3, [pc, #348]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800177a:	430a      	orrs	r2, r1
 800177c:	601a      	str	r2, [r3, #0]

        /* Enable the Internal High Speed oscillator (HSI16). */
        __HAL_RCC_HSI_ENABLE();
 800177e:	4b56      	ldr	r3, [pc, #344]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001780:	681a      	ldr	r2, [r3, #0]
 8001782:	4b55      	ldr	r3, [pc, #340]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001784:	2180      	movs	r1, #128	@ 0x80
 8001786:	0049      	lsls	r1, r1, #1
 8001788:	430a      	orrs	r2, r1
 800178a:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800178c:	f7ff fa54 	bl	8000c38 <HAL_GetTick>
 8001790:	0003      	movs	r3, r0
 8001792:	613b      	str	r3, [r7, #16]

        /* Wait till HSI is ready */
        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8001794:	e008      	b.n	80017a8 <HAL_RCC_OscConfig+0x1fc>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 8001796:	f7ff fa4f 	bl	8000c38 <HAL_GetTick>
 800179a:	0002      	movs	r2, r0
 800179c:	693b      	ldr	r3, [r7, #16]
 800179e:	1ad3      	subs	r3, r2, r3
 80017a0:	2b02      	cmp	r3, #2
 80017a2:	d901      	bls.n	80017a8 <HAL_RCC_OscConfig+0x1fc>
          {
            return HAL_TIMEOUT;
 80017a4:	2303      	movs	r3, #3
 80017a6:	e1fe      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 80017a8:	4b4b      	ldr	r3, [pc, #300]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80017aa:	681a      	ldr	r2, [r3, #0]
 80017ac:	2380      	movs	r3, #128	@ 0x80
 80017ae:	00db      	lsls	r3, r3, #3
 80017b0:	4013      	ands	r3, r2
 80017b2:	d0f0      	beq.n	8001796 <HAL_RCC_OscConfig+0x1ea>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80017b4:	4b48      	ldr	r3, [pc, #288]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80017b6:	685b      	ldr	r3, [r3, #4]
 80017b8:	4a4a      	ldr	r2, [pc, #296]	@ (80018e4 <HAL_RCC_OscConfig+0x338>)
 80017ba:	4013      	ands	r3, r2
 80017bc:	0019      	movs	r1, r3
 80017be:	687b      	ldr	r3, [r7, #4]
 80017c0:	695b      	ldr	r3, [r3, #20]
 80017c2:	021a      	lsls	r2, r3, #8
 80017c4:	4b44      	ldr	r3, [pc, #272]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80017c6:	430a      	orrs	r2, r1
 80017c8:	605a      	str	r2, [r3, #4]
 80017ca:	e01b      	b.n	8001804 <HAL_RCC_OscConfig+0x258>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI16). */
        __HAL_RCC_HSI_DISABLE();
 80017cc:	4b42      	ldr	r3, [pc, #264]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80017ce:	681a      	ldr	r2, [r3, #0]
 80017d0:	4b41      	ldr	r3, [pc, #260]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80017d2:	4949      	ldr	r1, [pc, #292]	@ (80018f8 <HAL_RCC_OscConfig+0x34c>)
 80017d4:	400a      	ands	r2, r1
 80017d6:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80017d8:	f7ff fa2e 	bl	8000c38 <HAL_GetTick>
 80017dc:	0003      	movs	r3, r0
 80017de:	613b      	str	r3, [r7, #16]

        /* Wait till HSI is disabled */
        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 80017e0:	e008      	b.n	80017f4 <HAL_RCC_OscConfig+0x248>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 80017e2:	f7ff fa29 	bl	8000c38 <HAL_GetTick>
 80017e6:	0002      	movs	r2, r0
 80017e8:	693b      	ldr	r3, [r7, #16]
 80017ea:	1ad3      	subs	r3, r2, r3
 80017ec:	2b02      	cmp	r3, #2
 80017ee:	d901      	bls.n	80017f4 <HAL_RCC_OscConfig+0x248>
          {
            return HAL_TIMEOUT;
 80017f0:	2303      	movs	r3, #3
 80017f2:	e1d8      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 80017f4:	4b38      	ldr	r3, [pc, #224]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80017f6:	681a      	ldr	r2, [r3, #0]
 80017f8:	2380      	movs	r3, #128	@ 0x80
 80017fa:	00db      	lsls	r3, r3, #3
 80017fc:	4013      	ands	r3, r2
 80017fe:	d1f0      	bne.n	80017e2 <HAL_RCC_OscConfig+0x236>
 8001800:	e000      	b.n	8001804 <HAL_RCC_OscConfig+0x258>
      if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 8001802:	46c0      	nop			@ (mov r8, r8)
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8001804:	687b      	ldr	r3, [r7, #4]
 8001806:	681b      	ldr	r3, [r3, #0]
 8001808:	2208      	movs	r2, #8
 800180a:	4013      	ands	r3, r2
 800180c:	d047      	beq.n	800189e <HAL_RCC_OscConfig+0x2f2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check if LSI is used as system clock */
    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
 800180e:	4b32      	ldr	r3, [pc, #200]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001810:	689b      	ldr	r3, [r3, #8]
 8001812:	2238      	movs	r2, #56	@ 0x38
 8001814:	4013      	ands	r3, r2
 8001816:	2b18      	cmp	r3, #24
 8001818:	d10a      	bne.n	8001830 <HAL_RCC_OscConfig+0x284>
    {
      /* When LSI is used as system clock it will not be disabled */
      if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF))
 800181a:	4b2f      	ldr	r3, [pc, #188]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800181c:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800181e:	2202      	movs	r2, #2
 8001820:	4013      	ands	r3, r2
 8001822:	d03c      	beq.n	800189e <HAL_RCC_OscConfig+0x2f2>
 8001824:	687b      	ldr	r3, [r7, #4]
 8001826:	699b      	ldr	r3, [r3, #24]
 8001828:	2b00      	cmp	r3, #0
 800182a:	d138      	bne.n	800189e <HAL_RCC_OscConfig+0x2f2>
      {
        return HAL_ERROR;
 800182c:	2301      	movs	r3, #1
 800182e:	e1ba      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
      }
    }
    else
    {
      /* Check the LSI State */
      if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8001830:	687b      	ldr	r3, [r7, #4]
 8001832:	699b      	ldr	r3, [r3, #24]
 8001834:	2b00      	cmp	r3, #0
 8001836:	d019      	beq.n	800186c <HAL_RCC_OscConfig+0x2c0>
      {
        /* Enable the Internal Low Speed oscillator (LSI). */
        __HAL_RCC_LSI_ENABLE();
 8001838:	4b27      	ldr	r3, [pc, #156]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800183a:	6e1a      	ldr	r2, [r3, #96]	@ 0x60
 800183c:	4b26      	ldr	r3, [pc, #152]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800183e:	2101      	movs	r1, #1
 8001840:	430a      	orrs	r2, r1
 8001842:	661a      	str	r2, [r3, #96]	@ 0x60

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001844:	f7ff f9f8 	bl	8000c38 <HAL_GetTick>
 8001848:	0003      	movs	r3, r0
 800184a:	613b      	str	r3, [r7, #16]

        /* Wait till LSI is ready */
        while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 800184c:	e008      	b.n	8001860 <HAL_RCC_OscConfig+0x2b4>
        {
          if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 800184e:	f7ff f9f3 	bl	8000c38 <HAL_GetTick>
 8001852:	0002      	movs	r2, r0
 8001854:	693b      	ldr	r3, [r7, #16]
 8001856:	1ad3      	subs	r3, r2, r3
 8001858:	2b02      	cmp	r3, #2
 800185a:	d901      	bls.n	8001860 <HAL_RCC_OscConfig+0x2b4>
          {
            return HAL_TIMEOUT;
 800185c:	2303      	movs	r3, #3
 800185e:	e1a2      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8001860:	4b1d      	ldr	r3, [pc, #116]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001862:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001864:	2202      	movs	r2, #2
 8001866:	4013      	ands	r3, r2
 8001868:	d0f1      	beq.n	800184e <HAL_RCC_OscConfig+0x2a2>
 800186a:	e018      	b.n	800189e <HAL_RCC_OscConfig+0x2f2>
        }
      }
      else
      {
        /* Disable the Internal Low Speed oscillator (LSI). */
        __HAL_RCC_LSI_DISABLE();
 800186c:	4b1a      	ldr	r3, [pc, #104]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 800186e:	6e1a      	ldr	r2, [r3, #96]	@ 0x60
 8001870:	4b19      	ldr	r3, [pc, #100]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001872:	2101      	movs	r1, #1
 8001874:	438a      	bics	r2, r1
 8001876:	661a      	str	r2, [r3, #96]	@ 0x60

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001878:	f7ff f9de 	bl	8000c38 <HAL_GetTick>
 800187c:	0003      	movs	r3, r0
 800187e:	613b      	str	r3, [r7, #16]

        /* Wait till LSI is disabled */
        while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 8001880:	e008      	b.n	8001894 <HAL_RCC_OscConfig+0x2e8>
        {
          if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8001882:	f7ff f9d9 	bl	8000c38 <HAL_GetTick>
 8001886:	0002      	movs	r2, r0
 8001888:	693b      	ldr	r3, [r7, #16]
 800188a:	1ad3      	subs	r3, r2, r3
 800188c:	2b02      	cmp	r3, #2
 800188e:	d901      	bls.n	8001894 <HAL_RCC_OscConfig+0x2e8>
          {
            return HAL_TIMEOUT;
 8001890:	2303      	movs	r3, #3
 8001892:	e188      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 8001894:	4b10      	ldr	r3, [pc, #64]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 8001896:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001898:	2202      	movs	r2, #2
 800189a:	4013      	ands	r3, r2
 800189c:	d1f1      	bne.n	8001882 <HAL_RCC_OscConfig+0x2d6>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 800189e:	687b      	ldr	r3, [r7, #4]
 80018a0:	681b      	ldr	r3, [r3, #0]
 80018a2:	2204      	movs	r2, #4
 80018a4:	4013      	ands	r3, r2
 80018a6:	d100      	bne.n	80018aa <HAL_RCC_OscConfig+0x2fe>
 80018a8:	e0c6      	b.n	8001a38 <HAL_RCC_OscConfig+0x48c>
  {
    FlagStatus       pwrclkchanged = RESET;
 80018aa:	231f      	movs	r3, #31
 80018ac:	18fb      	adds	r3, r7, r3
 80018ae:	2200      	movs	r2, #0
 80018b0:	701a      	strb	r2, [r3, #0]

    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* When the LSE is used as system clock, it is not allowed disable it */
    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
 80018b2:	4b09      	ldr	r3, [pc, #36]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80018b4:	689b      	ldr	r3, [r3, #8]
 80018b6:	2238      	movs	r2, #56	@ 0x38
 80018b8:	4013      	ands	r3, r2
 80018ba:	2b20      	cmp	r3, #32
 80018bc:	d11e      	bne.n	80018fc <HAL_RCC_OscConfig+0x350>
    {
      if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF))
 80018be:	4b06      	ldr	r3, [pc, #24]	@ (80018d8 <HAL_RCC_OscConfig+0x32c>)
 80018c0:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80018c2:	2202      	movs	r2, #2
 80018c4:	4013      	ands	r3, r2
 80018c6:	d100      	bne.n	80018ca <HAL_RCC_OscConfig+0x31e>
 80018c8:	e0b6      	b.n	8001a38 <HAL_RCC_OscConfig+0x48c>
 80018ca:	687b      	ldr	r3, [r7, #4]
 80018cc:	689b      	ldr	r3, [r3, #8]
 80018ce:	2b00      	cmp	r3, #0
 80018d0:	d000      	beq.n	80018d4 <HAL_RCC_OscConfig+0x328>
 80018d2:	e0b1      	b.n	8001a38 <HAL_RCC_OscConfig+0x48c>
      {
        return HAL_ERROR;
 80018d4:	2301      	movs	r3, #1
 80018d6:	e166      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
 80018d8:	40021000 	.word	0x40021000
 80018dc:	fffeffff 	.word	0xfffeffff
 80018e0:	fffbffff 	.word	0xfffbffff
 80018e4:	ffff80ff 	.word	0xffff80ff
 80018e8:	ffffc7ff 	.word	0xffffc7ff
 80018ec:	00f42400 	.word	0x00f42400
 80018f0:	20000000 	.word	0x20000000
 80018f4:	20000004 	.word	0x20000004
 80018f8:	fffffeff 	.word	0xfffffeff
    }
    else
    {
      /* Update LSE configuration in Backup Domain control register    */
      /* Requires to enable write access to Backup Domain of necessary */
      if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
 80018fc:	4bac      	ldr	r3, [pc, #688]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 80018fe:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 8001900:	2380      	movs	r3, #128	@ 0x80
 8001902:	055b      	lsls	r3, r3, #21
 8001904:	4013      	ands	r3, r2
 8001906:	d101      	bne.n	800190c <HAL_RCC_OscConfig+0x360>
 8001908:	2301      	movs	r3, #1
 800190a:	e000      	b.n	800190e <HAL_RCC_OscConfig+0x362>
 800190c:	2300      	movs	r3, #0
 800190e:	2b00      	cmp	r3, #0
 8001910:	d011      	beq.n	8001936 <HAL_RCC_OscConfig+0x38a>
      {
        __HAL_RCC_PWR_CLK_ENABLE();
 8001912:	4ba7      	ldr	r3, [pc, #668]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001914:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 8001916:	4ba6      	ldr	r3, [pc, #664]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001918:	2180      	movs	r1, #128	@ 0x80
 800191a:	0549      	lsls	r1, r1, #21
 800191c:	430a      	orrs	r2, r1
 800191e:	63da      	str	r2, [r3, #60]	@ 0x3c
 8001920:	4ba3      	ldr	r3, [pc, #652]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001922:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 8001924:	2380      	movs	r3, #128	@ 0x80
 8001926:	055b      	lsls	r3, r3, #21
 8001928:	4013      	ands	r3, r2
 800192a:	60fb      	str	r3, [r7, #12]
 800192c:	68fb      	ldr	r3, [r7, #12]
        pwrclkchanged = SET;
 800192e:	231f      	movs	r3, #31
 8001930:	18fb      	adds	r3, r7, r3
 8001932:	2201      	movs	r2, #1
 8001934:	701a      	strb	r2, [r3, #0]
      }

      if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8001936:	4b9f      	ldr	r3, [pc, #636]	@ (8001bb4 <HAL_RCC_OscConfig+0x608>)
 8001938:	681a      	ldr	r2, [r3, #0]
 800193a:	2380      	movs	r3, #128	@ 0x80
 800193c:	005b      	lsls	r3, r3, #1
 800193e:	4013      	ands	r3, r2
 8001940:	d11a      	bne.n	8001978 <HAL_RCC_OscConfig+0x3cc>
      {
        /* Enable write access to Backup domain */
        SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8001942:	4b9c      	ldr	r3, [pc, #624]	@ (8001bb4 <HAL_RCC_OscConfig+0x608>)
 8001944:	681a      	ldr	r2, [r3, #0]
 8001946:	4b9b      	ldr	r3, [pc, #620]	@ (8001bb4 <HAL_RCC_OscConfig+0x608>)
 8001948:	2180      	movs	r1, #128	@ 0x80
 800194a:	0049      	lsls	r1, r1, #1
 800194c:	430a      	orrs	r2, r1
 800194e:	601a      	str	r2, [r3, #0]

        /* Wait for Backup domain Write protection disable */
        tickstart = HAL_GetTick();
 8001950:	f7ff f972 	bl	8000c38 <HAL_GetTick>
 8001954:	0003      	movs	r3, r0
 8001956:	613b      	str	r3, [r7, #16]

        while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8001958:	e008      	b.n	800196c <HAL_RCC_OscConfig+0x3c0>
        {
          if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 800195a:	f7ff f96d 	bl	8000c38 <HAL_GetTick>
 800195e:	0002      	movs	r2, r0
 8001960:	693b      	ldr	r3, [r7, #16]
 8001962:	1ad3      	subs	r3, r2, r3
 8001964:	2b02      	cmp	r3, #2
 8001966:	d901      	bls.n	800196c <HAL_RCC_OscConfig+0x3c0>
          {
            return HAL_TIMEOUT;
 8001968:	2303      	movs	r3, #3
 800196a:	e11c      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 800196c:	4b91      	ldr	r3, [pc, #580]	@ (8001bb4 <HAL_RCC_OscConfig+0x608>)
 800196e:	681a      	ldr	r2, [r3, #0]
 8001970:	2380      	movs	r3, #128	@ 0x80
 8001972:	005b      	lsls	r3, r3, #1
 8001974:	4013      	ands	r3, r2
 8001976:	d0f0      	beq.n	800195a <HAL_RCC_OscConfig+0x3ae>
          }
        }
      }

      /* Set the new LSE configuration -----------------------------------------*/
      __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8001978:	687b      	ldr	r3, [r7, #4]
 800197a:	689b      	ldr	r3, [r3, #8]
 800197c:	2b01      	cmp	r3, #1
 800197e:	d106      	bne.n	800198e <HAL_RCC_OscConfig+0x3e2>
 8001980:	4b8b      	ldr	r3, [pc, #556]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001982:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
 8001984:	4b8a      	ldr	r3, [pc, #552]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001986:	2101      	movs	r1, #1
 8001988:	430a      	orrs	r2, r1
 800198a:	65da      	str	r2, [r3, #92]	@ 0x5c
 800198c:	e01c      	b.n	80019c8 <HAL_RCC_OscConfig+0x41c>
 800198e:	687b      	ldr	r3, [r7, #4]
 8001990:	689b      	ldr	r3, [r3, #8]
 8001992:	2b05      	cmp	r3, #5
 8001994:	d10c      	bne.n	80019b0 <HAL_RCC_OscConfig+0x404>
 8001996:	4b86      	ldr	r3, [pc, #536]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001998:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
 800199a:	4b85      	ldr	r3, [pc, #532]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 800199c:	2104      	movs	r1, #4
 800199e:	430a      	orrs	r2, r1
 80019a0:	65da      	str	r2, [r3, #92]	@ 0x5c
 80019a2:	4b83      	ldr	r3, [pc, #524]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 80019a4:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
 80019a6:	4b82      	ldr	r3, [pc, #520]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 80019a8:	2101      	movs	r1, #1
 80019aa:	430a      	orrs	r2, r1
 80019ac:	65da      	str	r2, [r3, #92]	@ 0x5c
 80019ae:	e00b      	b.n	80019c8 <HAL_RCC_OscConfig+0x41c>
 80019b0:	4b7f      	ldr	r3, [pc, #508]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 80019b2:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
 80019b4:	4b7e      	ldr	r3, [pc, #504]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 80019b6:	2101      	movs	r1, #1
 80019b8:	438a      	bics	r2, r1
 80019ba:	65da      	str	r2, [r3, #92]	@ 0x5c
 80019bc:	4b7c      	ldr	r3, [pc, #496]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 80019be:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
 80019c0:	4b7b      	ldr	r3, [pc, #492]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 80019c2:	2104      	movs	r1, #4
 80019c4:	438a      	bics	r2, r1
 80019c6:	65da      	str	r2, [r3, #92]	@ 0x5c

      /* Check the LSE State */
      if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 80019c8:	687b      	ldr	r3, [r7, #4]
 80019ca:	689b      	ldr	r3, [r3, #8]
 80019cc:	2b00      	cmp	r3, #0
 80019ce:	d014      	beq.n	80019fa <HAL_RCC_OscConfig+0x44e>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80019d0:	f7ff f932 	bl	8000c38 <HAL_GetTick>
 80019d4:	0003      	movs	r3, r0
 80019d6:	613b      	str	r3, [r7, #16]

        /* Wait till LSE is ready */
        while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 80019d8:	e009      	b.n	80019ee <HAL_RCC_OscConfig+0x442>
        {
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80019da:	f7ff f92d 	bl	8000c38 <HAL_GetTick>
 80019de:	0002      	movs	r2, r0
 80019e0:	693b      	ldr	r3, [r7, #16]
 80019e2:	1ad3      	subs	r3, r2, r3
 80019e4:	4a74      	ldr	r2, [pc, #464]	@ (8001bb8 <HAL_RCC_OscConfig+0x60c>)
 80019e6:	4293      	cmp	r3, r2
 80019e8:	d901      	bls.n	80019ee <HAL_RCC_OscConfig+0x442>
          {
            return HAL_TIMEOUT;
 80019ea:	2303      	movs	r3, #3
 80019ec:	e0db      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 80019ee:	4b70      	ldr	r3, [pc, #448]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 80019f0:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80019f2:	2202      	movs	r2, #2
 80019f4:	4013      	ands	r3, r2
 80019f6:	d0f0      	beq.n	80019da <HAL_RCC_OscConfig+0x42e>
 80019f8:	e013      	b.n	8001a22 <HAL_RCC_OscConfig+0x476>
        }
      }
      else
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80019fa:	f7ff f91d 	bl	8000c38 <HAL_GetTick>
 80019fe:	0003      	movs	r3, r0
 8001a00:	613b      	str	r3, [r7, #16]

        /* Wait till LSE is disabled */
        while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 8001a02:	e009      	b.n	8001a18 <HAL_RCC_OscConfig+0x46c>
        {
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8001a04:	f7ff f918 	bl	8000c38 <HAL_GetTick>
 8001a08:	0002      	movs	r2, r0
 8001a0a:	693b      	ldr	r3, [r7, #16]
 8001a0c:	1ad3      	subs	r3, r2, r3
 8001a0e:	4a6a      	ldr	r2, [pc, #424]	@ (8001bb8 <HAL_RCC_OscConfig+0x60c>)
 8001a10:	4293      	cmp	r3, r2
 8001a12:	d901      	bls.n	8001a18 <HAL_RCC_OscConfig+0x46c>
          {
            return HAL_TIMEOUT;
 8001a14:	2303      	movs	r3, #3
 8001a16:	e0c6      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 8001a18:	4b65      	ldr	r3, [pc, #404]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001a1a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8001a1c:	2202      	movs	r2, #2
 8001a1e:	4013      	ands	r3, r2
 8001a20:	d1f0      	bne.n	8001a04 <HAL_RCC_OscConfig+0x458>
          }
        }
      }

      /* Restore clock configuration if changed */
      if (pwrclkchanged == SET)
 8001a22:	231f      	movs	r3, #31
 8001a24:	18fb      	adds	r3, r7, r3
 8001a26:	781b      	ldrb	r3, [r3, #0]
 8001a28:	2b01      	cmp	r3, #1
 8001a2a:	d105      	bne.n	8001a38 <HAL_RCC_OscConfig+0x48c>
      {
        __HAL_RCC_PWR_CLK_DISABLE();
 8001a2c:	4b60      	ldr	r3, [pc, #384]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001a2e:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 8001a30:	4b5f      	ldr	r3, [pc, #380]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001a32:	4962      	ldr	r1, [pc, #392]	@ (8001bbc <HAL_RCC_OscConfig+0x610>)
 8001a34:	400a      	ands	r2, r1
 8001a36:	63da      	str	r2, [r3, #60]	@ 0x3c
#endif /* RCC_HSI48_SUPPORT */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));

  if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
 8001a38:	687b      	ldr	r3, [r7, #4]
 8001a3a:	69db      	ldr	r3, [r3, #28]
 8001a3c:	2b00      	cmp	r3, #0
 8001a3e:	d100      	bne.n	8001a42 <HAL_RCC_OscConfig+0x496>
 8001a40:	e0b0      	b.n	8001ba4 <HAL_RCC_OscConfig+0x5f8>
  {
    /* Check if the PLL is used as system clock or not */
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8001a42:	4b5b      	ldr	r3, [pc, #364]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001a44:	689b      	ldr	r3, [r3, #8]
 8001a46:	2238      	movs	r2, #56	@ 0x38
 8001a48:	4013      	ands	r3, r2
 8001a4a:	2b10      	cmp	r3, #16
 8001a4c:	d100      	bne.n	8001a50 <HAL_RCC_OscConfig+0x4a4>
 8001a4e:	e078      	b.n	8001b42 <HAL_RCC_OscConfig+0x596>
    {
      if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
 8001a50:	687b      	ldr	r3, [r7, #4]
 8001a52:	69db      	ldr	r3, [r3, #28]
 8001a54:	2b02      	cmp	r3, #2
 8001a56:	d153      	bne.n	8001b00 <HAL_RCC_OscConfig+0x554>
        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
#endif /* RCC_PLLQ_SUPPORT */
        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8001a58:	4b55      	ldr	r3, [pc, #340]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001a5a:	681a      	ldr	r2, [r3, #0]
 8001a5c:	4b54      	ldr	r3, [pc, #336]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001a5e:	4958      	ldr	r1, [pc, #352]	@ (8001bc0 <HAL_RCC_OscConfig+0x614>)
 8001a60:	400a      	ands	r2, r1
 8001a62:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001a64:	f7ff f8e8 	bl	8000c38 <HAL_GetTick>
 8001a68:	0003      	movs	r3, r0
 8001a6a:	613b      	str	r3, [r7, #16]

        /* Wait till PLL is ready */
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8001a6c:	e008      	b.n	8001a80 <HAL_RCC_OscConfig+0x4d4>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8001a6e:	f7ff f8e3 	bl	8000c38 <HAL_GetTick>
 8001a72:	0002      	movs	r2, r0
 8001a74:	693b      	ldr	r3, [r7, #16]
 8001a76:	1ad3      	subs	r3, r2, r3
 8001a78:	2b02      	cmp	r3, #2
 8001a7a:	d901      	bls.n	8001a80 <HAL_RCC_OscConfig+0x4d4>
          {
            return HAL_TIMEOUT;
 8001a7c:	2303      	movs	r3, #3
 8001a7e:	e092      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8001a80:	4b4b      	ldr	r3, [pc, #300]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001a82:	681a      	ldr	r2, [r3, #0]
 8001a84:	2380      	movs	r3, #128	@ 0x80
 8001a86:	049b      	lsls	r3, r3, #18
 8001a88:	4013      	ands	r3, r2
 8001a8a:	d1f0      	bne.n	8001a6e <HAL_RCC_OscConfig+0x4c2>
                             RCC_OscInitStruct->PLL.PLLN,
                             RCC_OscInitStruct->PLL.PLLP,
                             RCC_OscInitStruct->PLL.PLLQ,
                             RCC_OscInitStruct->PLL.PLLR);
#else /* !RCC_PLLQ_SUPPORT */
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8001a8c:	4b48      	ldr	r3, [pc, #288]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001a8e:	68db      	ldr	r3, [r3, #12]
 8001a90:	4a4c      	ldr	r2, [pc, #304]	@ (8001bc4 <HAL_RCC_OscConfig+0x618>)
 8001a92:	4013      	ands	r3, r2
 8001a94:	0019      	movs	r1, r3
 8001a96:	687b      	ldr	r3, [r7, #4]
 8001a98:	6a1a      	ldr	r2, [r3, #32]
 8001a9a:	687b      	ldr	r3, [r7, #4]
 8001a9c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8001a9e:	431a      	orrs	r2, r3
 8001aa0:	687b      	ldr	r3, [r7, #4]
 8001aa2:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8001aa4:	021b      	lsls	r3, r3, #8
 8001aa6:	431a      	orrs	r2, r3
 8001aa8:	687b      	ldr	r3, [r7, #4]
 8001aaa:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8001aac:	431a      	orrs	r2, r3
 8001aae:	687b      	ldr	r3, [r7, #4]
 8001ab0:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8001ab2:	431a      	orrs	r2, r3
 8001ab4:	4b3e      	ldr	r3, [pc, #248]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001ab6:	430a      	orrs	r2, r1
 8001ab8:	60da      	str	r2, [r3, #12]
                             RCC_OscInitStruct->PLL.PLLP,
                             RCC_OscInitStruct->PLL.PLLR);
#endif /* RCC_PLLQ_SUPPORT */

        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 8001aba:	4b3d      	ldr	r3, [pc, #244]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001abc:	681a      	ldr	r2, [r3, #0]
 8001abe:	4b3c      	ldr	r3, [pc, #240]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001ac0:	2180      	movs	r1, #128	@ 0x80
 8001ac2:	0449      	lsls	r1, r1, #17
 8001ac4:	430a      	orrs	r2, r1
 8001ac6:	601a      	str	r2, [r3, #0]

        /* Enable PLLR Clock output. */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK);
 8001ac8:	4b39      	ldr	r3, [pc, #228]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001aca:	68da      	ldr	r2, [r3, #12]
 8001acc:	4b38      	ldr	r3, [pc, #224]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001ace:	2180      	movs	r1, #128	@ 0x80
 8001ad0:	0549      	lsls	r1, r1, #21
 8001ad2:	430a      	orrs	r2, r1
 8001ad4:	60da      	str	r2, [r3, #12]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001ad6:	f7ff f8af 	bl	8000c38 <HAL_GetTick>
 8001ada:	0003      	movs	r3, r0
 8001adc:	613b      	str	r3, [r7, #16]

        /* Wait till PLL is ready */
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001ade:	e008      	b.n	8001af2 <HAL_RCC_OscConfig+0x546>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8001ae0:	f7ff f8aa 	bl	8000c38 <HAL_GetTick>
 8001ae4:	0002      	movs	r2, r0
 8001ae6:	693b      	ldr	r3, [r7, #16]
 8001ae8:	1ad3      	subs	r3, r2, r3
 8001aea:	2b02      	cmp	r3, #2
 8001aec:	d901      	bls.n	8001af2 <HAL_RCC_OscConfig+0x546>
          {
            return HAL_TIMEOUT;
 8001aee:	2303      	movs	r3, #3
 8001af0:	e059      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001af2:	4b2f      	ldr	r3, [pc, #188]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001af4:	681a      	ldr	r2, [r3, #0]
 8001af6:	2380      	movs	r3, #128	@ 0x80
 8001af8:	049b      	lsls	r3, r3, #18
 8001afa:	4013      	ands	r3, r2
 8001afc:	d0f0      	beq.n	8001ae0 <HAL_RCC_OscConfig+0x534>
 8001afe:	e051      	b.n	8001ba4 <HAL_RCC_OscConfig+0x5f8>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8001b00:	4b2b      	ldr	r3, [pc, #172]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001b02:	681a      	ldr	r2, [r3, #0]
 8001b04:	4b2a      	ldr	r3, [pc, #168]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001b06:	492e      	ldr	r1, [pc, #184]	@ (8001bc0 <HAL_RCC_OscConfig+0x614>)
 8001b08:	400a      	ands	r2, r1
 8001b0a:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001b0c:	f7ff f894 	bl	8000c38 <HAL_GetTick>
 8001b10:	0003      	movs	r3, r0
 8001b12:	613b      	str	r3, [r7, #16]

        /* Wait till PLL is disabled */
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8001b14:	e008      	b.n	8001b28 <HAL_RCC_OscConfig+0x57c>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8001b16:	f7ff f88f 	bl	8000c38 <HAL_GetTick>
 8001b1a:	0002      	movs	r2, r0
 8001b1c:	693b      	ldr	r3, [r7, #16]
 8001b1e:	1ad3      	subs	r3, r2, r3
 8001b20:	2b02      	cmp	r3, #2
 8001b22:	d901      	bls.n	8001b28 <HAL_RCC_OscConfig+0x57c>
          {
            return HAL_TIMEOUT;
 8001b24:	2303      	movs	r3, #3
 8001b26:	e03e      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8001b28:	4b21      	ldr	r3, [pc, #132]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001b2a:	681a      	ldr	r2, [r3, #0]
 8001b2c:	2380      	movs	r3, #128	@ 0x80
 8001b2e:	049b      	lsls	r3, r3, #18
 8001b30:	4013      	ands	r3, r2
 8001b32:	d1f0      	bne.n	8001b16 <HAL_RCC_OscConfig+0x56a>
        }
        /* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLQ_SUPPORT)
        RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN);
#else
        RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN);
 8001b34:	4b1e      	ldr	r3, [pc, #120]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001b36:	68da      	ldr	r2, [r3, #12]
 8001b38:	4b1d      	ldr	r3, [pc, #116]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001b3a:	4923      	ldr	r1, [pc, #140]	@ (8001bc8 <HAL_RCC_OscConfig+0x61c>)
 8001b3c:	400a      	ands	r2, r1
 8001b3e:	60da      	str	r2, [r3, #12]
 8001b40:	e030      	b.n	8001ba4 <HAL_RCC_OscConfig+0x5f8>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8001b42:	687b      	ldr	r3, [r7, #4]
 8001b44:	69db      	ldr	r3, [r3, #28]
 8001b46:	2b01      	cmp	r3, #1
 8001b48:	d101      	bne.n	8001b4e <HAL_RCC_OscConfig+0x5a2>
      {
        return HAL_ERROR;
 8001b4a:	2301      	movs	r3, #1
 8001b4c:	e02b      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        temp_pllckcfg = RCC->PLLCFGR;
 8001b4e:	4b18      	ldr	r3, [pc, #96]	@ (8001bb0 <HAL_RCC_OscConfig+0x604>)
 8001b50:	68db      	ldr	r3, [r3, #12]
 8001b52:	617b      	str	r3, [r7, #20]
        if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8001b54:	697b      	ldr	r3, [r7, #20]
 8001b56:	2203      	movs	r2, #3
 8001b58:	401a      	ands	r2, r3
 8001b5a:	687b      	ldr	r3, [r7, #4]
 8001b5c:	6a1b      	ldr	r3, [r3, #32]
 8001b5e:	429a      	cmp	r2, r3
 8001b60:	d11e      	bne.n	8001ba0 <HAL_RCC_OscConfig+0x5f4>
            (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
 8001b62:	697b      	ldr	r3, [r7, #20]
 8001b64:	2270      	movs	r2, #112	@ 0x70
 8001b66:	401a      	ands	r2, r3
 8001b68:	687b      	ldr	r3, [r7, #4]
 8001b6a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
        if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8001b6c:	429a      	cmp	r2, r3
 8001b6e:	d117      	bne.n	8001ba0 <HAL_RCC_OscConfig+0x5f4>
            (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
 8001b70:	697a      	ldr	r2, [r7, #20]
 8001b72:	23fe      	movs	r3, #254	@ 0xfe
 8001b74:	01db      	lsls	r3, r3, #7
 8001b76:	401a      	ands	r2, r3
 8001b78:	687b      	ldr	r3, [r7, #4]
 8001b7a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8001b7c:	021b      	lsls	r3, r3, #8
            (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
 8001b7e:	429a      	cmp	r2, r3
 8001b80:	d10e      	bne.n	8001ba0 <HAL_RCC_OscConfig+0x5f4>
            (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
 8001b82:	697a      	ldr	r2, [r7, #20]
 8001b84:	23f8      	movs	r3, #248	@ 0xf8
 8001b86:	039b      	lsls	r3, r3, #14
 8001b88:	401a      	ands	r2, r3
 8001b8a:	687b      	ldr	r3, [r7, #4]
 8001b8c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
            (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
 8001b8e:	429a      	cmp	r2, r3
 8001b90:	d106      	bne.n	8001ba0 <HAL_RCC_OscConfig+0x5f4>
#if defined (RCC_PLLQ_SUPPORT)
            (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
#endif /* RCC_PLLQ_SUPPORT */
            (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
 8001b92:	697b      	ldr	r3, [r7, #20]
 8001b94:	0f5b      	lsrs	r3, r3, #29
 8001b96:	075a      	lsls	r2, r3, #29
 8001b98:	687b      	ldr	r3, [r7, #4]
 8001b9a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
            (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
 8001b9c:	429a      	cmp	r2, r3
 8001b9e:	d001      	beq.n	8001ba4 <HAL_RCC_OscConfig+0x5f8>
        {
          return HAL_ERROR;
 8001ba0:	2301      	movs	r3, #1
 8001ba2:	e000      	b.n	8001ba6 <HAL_RCC_OscConfig+0x5fa>
        }
      }
    }
  }
  return HAL_OK;
 8001ba4:	2300      	movs	r3, #0
}
 8001ba6:	0018      	movs	r0, r3
 8001ba8:	46bd      	mov	sp, r7
 8001baa:	b008      	add	sp, #32
 8001bac:	bd80      	pop	{r7, pc}
 8001bae:	46c0      	nop			@ (mov r8, r8)
 8001bb0:	40021000 	.word	0x40021000
 8001bb4:	40007000 	.word	0x40007000
 8001bb8:	00001388 	.word	0x00001388
 8001bbc:	efffffff 	.word	0xefffffff
 8001bc0:	feffffff 	.word	0xfeffffff
 8001bc4:	1fc1808c 	.word	0x1fc1808c
 8001bc8:	effefffc 	.word	0xeffefffc

08001bcc <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 8001bcc:	b580      	push	{r7, lr}
 8001bce:	b084      	sub	sp, #16
 8001bd0:	af00      	add	r7, sp, #0
 8001bd2:	6078      	str	r0, [r7, #4]
 8001bd4:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;

  /* Check Null pointer */
  if (RCC_ClkInitStruct == NULL)
 8001bd6:	687b      	ldr	r3, [r7, #4]
 8001bd8:	2b00      	cmp	r3, #0
 8001bda:	d101      	bne.n	8001be0 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8001bdc:	2301      	movs	r3, #1
 8001bde:	e0e9      	b.n	8001db4 <HAL_RCC_ClockConfig+0x1e8>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the FLASH clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if (FLatency > __HAL_FLASH_GET_LATENCY())
 8001be0:	4b76      	ldr	r3, [pc, #472]	@ (8001dbc <HAL_RCC_ClockConfig+0x1f0>)
 8001be2:	681b      	ldr	r3, [r3, #0]
 8001be4:	2207      	movs	r2, #7
 8001be6:	4013      	ands	r3, r2
 8001be8:	683a      	ldr	r2, [r7, #0]
 8001bea:	429a      	cmp	r2, r3
 8001bec:	d91e      	bls.n	8001c2c <HAL_RCC_ClockConfig+0x60>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8001bee:	4b73      	ldr	r3, [pc, #460]	@ (8001dbc <HAL_RCC_ClockConfig+0x1f0>)
 8001bf0:	681b      	ldr	r3, [r3, #0]
 8001bf2:	2207      	movs	r2, #7
 8001bf4:	4393      	bics	r3, r2
 8001bf6:	0019      	movs	r1, r3
 8001bf8:	4b70      	ldr	r3, [pc, #448]	@ (8001dbc <HAL_RCC_ClockConfig+0x1f0>)
 8001bfa:	683a      	ldr	r2, [r7, #0]
 8001bfc:	430a      	orrs	r2, r1
 8001bfe:	601a      	str	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by polling the FLASH_ACR register */
    tickstart = HAL_GetTick();
 8001c00:	f7ff f81a 	bl	8000c38 <HAL_GetTick>
 8001c04:	0003      	movs	r3, r0
 8001c06:	60fb      	str	r3, [r7, #12]

    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8001c08:	e009      	b.n	8001c1e <HAL_RCC_ClockConfig+0x52>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001c0a:	f7ff f815 	bl	8000c38 <HAL_GetTick>
 8001c0e:	0002      	movs	r2, r0
 8001c10:	68fb      	ldr	r3, [r7, #12]
 8001c12:	1ad3      	subs	r3, r2, r3
 8001c14:	4a6a      	ldr	r2, [pc, #424]	@ (8001dc0 <HAL_RCC_ClockConfig+0x1f4>)
 8001c16:	4293      	cmp	r3, r2
 8001c18:	d901      	bls.n	8001c1e <HAL_RCC_ClockConfig+0x52>
      {
        return HAL_TIMEOUT;
 8001c1a:	2303      	movs	r3, #3
 8001c1c:	e0ca      	b.n	8001db4 <HAL_RCC_ClockConfig+0x1e8>
    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8001c1e:	4b67      	ldr	r3, [pc, #412]	@ (8001dbc <HAL_RCC_ClockConfig+0x1f0>)
 8001c20:	681b      	ldr	r3, [r3, #0]
 8001c22:	2207      	movs	r2, #7
 8001c24:	4013      	ands	r3, r2
 8001c26:	683a      	ldr	r2, [r7, #0]
 8001c28:	429a      	cmp	r2, r3
 8001c2a:	d1ee      	bne.n	8001c0a <HAL_RCC_ClockConfig+0x3e>
      }
    }
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8001c2c:	687b      	ldr	r3, [r7, #4]
 8001c2e:	681b      	ldr	r3, [r3, #0]
 8001c30:	2202      	movs	r2, #2
 8001c32:	4013      	ands	r3, r2
 8001c34:	d015      	beq.n	8001c62 <HAL_RCC_ClockConfig+0x96>
  {
    /* Set the highest APB divider in order to ensure that we do not go through
       a non-spec phase whatever we decrease or increase HCLK. */
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8001c36:	687b      	ldr	r3, [r7, #4]
 8001c38:	681b      	ldr	r3, [r3, #0]
 8001c3a:	2204      	movs	r2, #4
 8001c3c:	4013      	ands	r3, r2
 8001c3e:	d006      	beq.n	8001c4e <HAL_RCC_ClockConfig+0x82>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
 8001c40:	4b60      	ldr	r3, [pc, #384]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001c42:	689a      	ldr	r2, [r3, #8]
 8001c44:	4b5f      	ldr	r3, [pc, #380]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001c46:	21e0      	movs	r1, #224	@ 0xe0
 8001c48:	01c9      	lsls	r1, r1, #7
 8001c4a:	430a      	orrs	r2, r1
 8001c4c:	609a      	str	r2, [r3, #8]
    }

    /* Set the new HCLK clock divider */
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8001c4e:	4b5d      	ldr	r3, [pc, #372]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001c50:	689b      	ldr	r3, [r3, #8]
 8001c52:	4a5d      	ldr	r2, [pc, #372]	@ (8001dc8 <HAL_RCC_ClockConfig+0x1fc>)
 8001c54:	4013      	ands	r3, r2
 8001c56:	0019      	movs	r1, r3
 8001c58:	687b      	ldr	r3, [r7, #4]
 8001c5a:	689a      	ldr	r2, [r3, #8]
 8001c5c:	4b59      	ldr	r3, [pc, #356]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001c5e:	430a      	orrs	r2, r1
 8001c60:	609a      	str	r2, [r3, #8]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8001c62:	687b      	ldr	r3, [r7, #4]
 8001c64:	681b      	ldr	r3, [r3, #0]
 8001c66:	2201      	movs	r2, #1
 8001c68:	4013      	ands	r3, r2
 8001c6a:	d057      	beq.n	8001d1c <HAL_RCC_ClockConfig+0x150>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8001c6c:	687b      	ldr	r3, [r7, #4]
 8001c6e:	685b      	ldr	r3, [r3, #4]
 8001c70:	2b01      	cmp	r3, #1
 8001c72:	d107      	bne.n	8001c84 <HAL_RCC_ClockConfig+0xb8>
    {
      /* Check the HSE ready flag */
      if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8001c74:	4b53      	ldr	r3, [pc, #332]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001c76:	681a      	ldr	r2, [r3, #0]
 8001c78:	2380      	movs	r3, #128	@ 0x80
 8001c7a:	029b      	lsls	r3, r3, #10
 8001c7c:	4013      	ands	r3, r2
 8001c7e:	d12b      	bne.n	8001cd8 <HAL_RCC_ClockConfig+0x10c>
      {
        return HAL_ERROR;
 8001c80:	2301      	movs	r3, #1
 8001c82:	e097      	b.n	8001db4 <HAL_RCC_ClockConfig+0x1e8>
      }
    }
    /* PLL is selected as System Clock Source */
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8001c84:	687b      	ldr	r3, [r7, #4]
 8001c86:	685b      	ldr	r3, [r3, #4]
 8001c88:	2b02      	cmp	r3, #2
 8001c8a:	d107      	bne.n	8001c9c <HAL_RCC_ClockConfig+0xd0>
    {
      /* Check the PLL ready flag */
      if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001c8c:	4b4d      	ldr	r3, [pc, #308]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001c8e:	681a      	ldr	r2, [r3, #0]
 8001c90:	2380      	movs	r3, #128	@ 0x80
 8001c92:	049b      	lsls	r3, r3, #18
 8001c94:	4013      	ands	r3, r2
 8001c96:	d11f      	bne.n	8001cd8 <HAL_RCC_ClockConfig+0x10c>
      {
        return HAL_ERROR;
 8001c98:	2301      	movs	r3, #1
 8001c9a:	e08b      	b.n	8001db4 <HAL_RCC_ClockConfig+0x1e8>
      }
    }
    /* HSI is selected as System Clock Source */
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
 8001c9c:	687b      	ldr	r3, [r7, #4]
 8001c9e:	685b      	ldr	r3, [r3, #4]
 8001ca0:	2b00      	cmp	r3, #0
 8001ca2:	d107      	bne.n	8001cb4 <HAL_RCC_ClockConfig+0xe8>
    {
      /* Check the HSI ready flag */
      if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8001ca4:	4b47      	ldr	r3, [pc, #284]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001ca6:	681a      	ldr	r2, [r3, #0]
 8001ca8:	2380      	movs	r3, #128	@ 0x80
 8001caa:	00db      	lsls	r3, r3, #3
 8001cac:	4013      	ands	r3, r2
 8001cae:	d113      	bne.n	8001cd8 <HAL_RCC_ClockConfig+0x10c>
      {
        return HAL_ERROR;
 8001cb0:	2301      	movs	r3, #1
 8001cb2:	e07f      	b.n	8001db4 <HAL_RCC_ClockConfig+0x1e8>
      }
    }
    /* LSI is selected as System Clock Source */
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
 8001cb4:	687b      	ldr	r3, [r7, #4]
 8001cb6:	685b      	ldr	r3, [r3, #4]
 8001cb8:	2b03      	cmp	r3, #3
 8001cba:	d106      	bne.n	8001cca <HAL_RCC_ClockConfig+0xfe>
    {
      /* Check the LSI ready flag */
      if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8001cbc:	4b41      	ldr	r3, [pc, #260]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001cbe:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001cc0:	2202      	movs	r2, #2
 8001cc2:	4013      	ands	r3, r2
 8001cc4:	d108      	bne.n	8001cd8 <HAL_RCC_ClockConfig+0x10c>
      {
        return HAL_ERROR;
 8001cc6:	2301      	movs	r3, #1
 8001cc8:	e074      	b.n	8001db4 <HAL_RCC_ClockConfig+0x1e8>
    }
    /* LSE is selected as System Clock Source */
    else
    {
      /* Check the LSE ready flag */
      if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8001cca:	4b3e      	ldr	r3, [pc, #248]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001ccc:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8001cce:	2202      	movs	r2, #2
 8001cd0:	4013      	ands	r3, r2
 8001cd2:	d101      	bne.n	8001cd8 <HAL_RCC_ClockConfig+0x10c>
      {
        return HAL_ERROR;
 8001cd4:	2301      	movs	r3, #1
 8001cd6:	e06d      	b.n	8001db4 <HAL_RCC_ClockConfig+0x1e8>
      }
    }
    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 8001cd8:	4b3a      	ldr	r3, [pc, #232]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001cda:	689b      	ldr	r3, [r3, #8]
 8001cdc:	2207      	movs	r2, #7
 8001cde:	4393      	bics	r3, r2
 8001ce0:	0019      	movs	r1, r3
 8001ce2:	687b      	ldr	r3, [r7, #4]
 8001ce4:	685a      	ldr	r2, [r3, #4]
 8001ce6:	4b37      	ldr	r3, [pc, #220]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001ce8:	430a      	orrs	r2, r1
 8001cea:	609a      	str	r2, [r3, #8]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 8001cec:	f7fe ffa4 	bl	8000c38 <HAL_GetTick>
 8001cf0:	0003      	movs	r3, r0
 8001cf2:	60fb      	str	r3, [r7, #12]

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8001cf4:	e009      	b.n	8001d0a <HAL_RCC_ClockConfig+0x13e>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001cf6:	f7fe ff9f 	bl	8000c38 <HAL_GetTick>
 8001cfa:	0002      	movs	r2, r0
 8001cfc:	68fb      	ldr	r3, [r7, #12]
 8001cfe:	1ad3      	subs	r3, r2, r3
 8001d00:	4a2f      	ldr	r2, [pc, #188]	@ (8001dc0 <HAL_RCC_ClockConfig+0x1f4>)
 8001d02:	4293      	cmp	r3, r2
 8001d04:	d901      	bls.n	8001d0a <HAL_RCC_ClockConfig+0x13e>
      {
        return HAL_TIMEOUT;
 8001d06:	2303      	movs	r3, #3
 8001d08:	e054      	b.n	8001db4 <HAL_RCC_ClockConfig+0x1e8>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8001d0a:	4b2e      	ldr	r3, [pc, #184]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001d0c:	689b      	ldr	r3, [r3, #8]
 8001d0e:	2238      	movs	r2, #56	@ 0x38
 8001d10:	401a      	ands	r2, r3
 8001d12:	687b      	ldr	r3, [r7, #4]
 8001d14:	685b      	ldr	r3, [r3, #4]
 8001d16:	00db      	lsls	r3, r3, #3
 8001d18:	429a      	cmp	r2, r3
 8001d1a:	d1ec      	bne.n	8001cf6 <HAL_RCC_ClockConfig+0x12a>
      }
    }
  }

  /* Decreasing the number of wait states because of lower CPU frequency */
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 8001d1c:	4b27      	ldr	r3, [pc, #156]	@ (8001dbc <HAL_RCC_ClockConfig+0x1f0>)
 8001d1e:	681b      	ldr	r3, [r3, #0]
 8001d20:	2207      	movs	r2, #7
 8001d22:	4013      	ands	r3, r2
 8001d24:	683a      	ldr	r2, [r7, #0]
 8001d26:	429a      	cmp	r2, r3
 8001d28:	d21e      	bcs.n	8001d68 <HAL_RCC_ClockConfig+0x19c>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8001d2a:	4b24      	ldr	r3, [pc, #144]	@ (8001dbc <HAL_RCC_ClockConfig+0x1f0>)
 8001d2c:	681b      	ldr	r3, [r3, #0]
 8001d2e:	2207      	movs	r2, #7
 8001d30:	4393      	bics	r3, r2
 8001d32:	0019      	movs	r1, r3
 8001d34:	4b21      	ldr	r3, [pc, #132]	@ (8001dbc <HAL_RCC_ClockConfig+0x1f0>)
 8001d36:	683a      	ldr	r2, [r7, #0]
 8001d38:	430a      	orrs	r2, r1
 8001d3a:	601a      	str	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by polling the FLASH_ACR register */
    tickstart = HAL_GetTick();
 8001d3c:	f7fe ff7c 	bl	8000c38 <HAL_GetTick>
 8001d40:	0003      	movs	r3, r0
 8001d42:	60fb      	str	r3, [r7, #12]

    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8001d44:	e009      	b.n	8001d5a <HAL_RCC_ClockConfig+0x18e>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001d46:	f7fe ff77 	bl	8000c38 <HAL_GetTick>
 8001d4a:	0002      	movs	r2, r0
 8001d4c:	68fb      	ldr	r3, [r7, #12]
 8001d4e:	1ad3      	subs	r3, r2, r3
 8001d50:	4a1b      	ldr	r2, [pc, #108]	@ (8001dc0 <HAL_RCC_ClockConfig+0x1f4>)
 8001d52:	4293      	cmp	r3, r2
 8001d54:	d901      	bls.n	8001d5a <HAL_RCC_ClockConfig+0x18e>
      {
        return HAL_TIMEOUT;
 8001d56:	2303      	movs	r3, #3
 8001d58:	e02c      	b.n	8001db4 <HAL_RCC_ClockConfig+0x1e8>
    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8001d5a:	4b18      	ldr	r3, [pc, #96]	@ (8001dbc <HAL_RCC_ClockConfig+0x1f0>)
 8001d5c:	681b      	ldr	r3, [r3, #0]
 8001d5e:	2207      	movs	r2, #7
 8001d60:	4013      	ands	r3, r2
 8001d62:	683a      	ldr	r2, [r7, #0]
 8001d64:	429a      	cmp	r2, r3
 8001d66:	d1ee      	bne.n	8001d46 <HAL_RCC_ClockConfig+0x17a>
      }
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8001d68:	687b      	ldr	r3, [r7, #4]
 8001d6a:	681b      	ldr	r3, [r3, #0]
 8001d6c:	2204      	movs	r2, #4
 8001d6e:	4013      	ands	r3, r2
 8001d70:	d009      	beq.n	8001d86 <HAL_RCC_ClockConfig+0x1ba>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
 8001d72:	4b14      	ldr	r3, [pc, #80]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001d74:	689b      	ldr	r3, [r3, #8]
 8001d76:	4a15      	ldr	r2, [pc, #84]	@ (8001dcc <HAL_RCC_ClockConfig+0x200>)
 8001d78:	4013      	ands	r3, r2
 8001d7a:	0019      	movs	r1, r3
 8001d7c:	687b      	ldr	r3, [r7, #4]
 8001d7e:	68da      	ldr	r2, [r3, #12]
 8001d80:	4b10      	ldr	r3, [pc, #64]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001d82:	430a      	orrs	r2, r1
 8001d84:	609a      	str	r2, [r3, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
 8001d86:	f000 f829 	bl	8001ddc <HAL_RCC_GetSysClockFreq>
 8001d8a:	0001      	movs	r1, r0
 8001d8c:	4b0d      	ldr	r3, [pc, #52]	@ (8001dc4 <HAL_RCC_ClockConfig+0x1f8>)
 8001d8e:	689b      	ldr	r3, [r3, #8]
 8001d90:	0a1b      	lsrs	r3, r3, #8
 8001d92:	220f      	movs	r2, #15
 8001d94:	401a      	ands	r2, r3
 8001d96:	4b0e      	ldr	r3, [pc, #56]	@ (8001dd0 <HAL_RCC_ClockConfig+0x204>)
 8001d98:	0092      	lsls	r2, r2, #2
 8001d9a:	58d3      	ldr	r3, [r2, r3]
 8001d9c:	221f      	movs	r2, #31
 8001d9e:	4013      	ands	r3, r2
 8001da0:	000a      	movs	r2, r1
 8001da2:	40da      	lsrs	r2, r3
 8001da4:	4b0b      	ldr	r3, [pc, #44]	@ (8001dd4 <HAL_RCC_ClockConfig+0x208>)
 8001da6:	601a      	str	r2, [r3, #0]

  /* Configure the source of time base considering new system clocks settings*/
  return HAL_InitTick(uwTickPrio);
 8001da8:	4b0b      	ldr	r3, [pc, #44]	@ (8001dd8 <HAL_RCC_ClockConfig+0x20c>)
 8001daa:	681b      	ldr	r3, [r3, #0]
 8001dac:	0018      	movs	r0, r3
 8001dae:	f7fe fee7 	bl	8000b80 <HAL_InitTick>
 8001db2:	0003      	movs	r3, r0
}
 8001db4:	0018      	movs	r0, r3
 8001db6:	46bd      	mov	sp, r7
 8001db8:	b004      	add	sp, #16
 8001dba:	bd80      	pop	{r7, pc}
 8001dbc:	40022000 	.word	0x40022000
 8001dc0:	00001388 	.word	0x00001388
 8001dc4:	40021000 	.word	0x40021000
 8001dc8:	fffff0ff 	.word	0xfffff0ff
 8001dcc:	ffff8fff 	.word	0xffff8fff
 8001dd0:	08003098 	.word	0x08003098
 8001dd4:	20000000 	.word	0x20000000
 8001dd8:	20000004 	.word	0x20000004

08001ddc <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8001ddc:	b580      	push	{r7, lr}
 8001dde:	b086      	sub	sp, #24
 8001de0:	af00      	add	r7, sp, #0
  uint32_t pllvco, pllsource, pllr, pllm, hsidiv;
  uint32_t sysclockfreq;

  if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
 8001de2:	4b3c      	ldr	r3, [pc, #240]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001de4:	689b      	ldr	r3, [r3, #8]
 8001de6:	2238      	movs	r2, #56	@ 0x38
 8001de8:	4013      	ands	r3, r2
 8001dea:	d10f      	bne.n	8001e0c <HAL_RCC_GetSysClockFreq+0x30>
  {
    /* HSISYS can be derived for HSI16 */
    hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
 8001dec:	4b39      	ldr	r3, [pc, #228]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001dee:	681b      	ldr	r3, [r3, #0]
 8001df0:	0adb      	lsrs	r3, r3, #11
 8001df2:	2207      	movs	r2, #7
 8001df4:	4013      	ands	r3, r2
 8001df6:	2201      	movs	r2, #1
 8001df8:	409a      	lsls	r2, r3
 8001dfa:	0013      	movs	r3, r2
 8001dfc:	603b      	str	r3, [r7, #0]

    /* HSI used as system clock source */
    sysclockfreq = (HSI_VALUE / hsidiv);
 8001dfe:	6839      	ldr	r1, [r7, #0]
 8001e00:	4835      	ldr	r0, [pc, #212]	@ (8001ed8 <HAL_RCC_GetSysClockFreq+0xfc>)
 8001e02:	f7fe f97d 	bl	8000100 <__udivsi3>
 8001e06:	0003      	movs	r3, r0
 8001e08:	613b      	str	r3, [r7, #16]
 8001e0a:	e05d      	b.n	8001ec8 <HAL_RCC_GetSysClockFreq+0xec>
  }
  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
 8001e0c:	4b31      	ldr	r3, [pc, #196]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001e0e:	689b      	ldr	r3, [r3, #8]
 8001e10:	2238      	movs	r2, #56	@ 0x38
 8001e12:	4013      	ands	r3, r2
 8001e14:	2b08      	cmp	r3, #8
 8001e16:	d102      	bne.n	8001e1e <HAL_RCC_GetSysClockFreq+0x42>
  {
    /* HSE used as system clock source */
    sysclockfreq = HSE_VALUE;
 8001e18:	4b30      	ldr	r3, [pc, #192]	@ (8001edc <HAL_RCC_GetSysClockFreq+0x100>)
 8001e1a:	613b      	str	r3, [r7, #16]
 8001e1c:	e054      	b.n	8001ec8 <HAL_RCC_GetSysClockFreq+0xec>
  }
  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8001e1e:	4b2d      	ldr	r3, [pc, #180]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001e20:	689b      	ldr	r3, [r3, #8]
 8001e22:	2238      	movs	r2, #56	@ 0x38
 8001e24:	4013      	ands	r3, r2
 8001e26:	2b10      	cmp	r3, #16
 8001e28:	d138      	bne.n	8001e9c <HAL_RCC_GetSysClockFreq+0xc0>
    /* PLL used as system clock  source */

    /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
    SYSCLK = PLL_VCO / PLLR
    */
    pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
 8001e2a:	4b2a      	ldr	r3, [pc, #168]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001e2c:	68db      	ldr	r3, [r3, #12]
 8001e2e:	2203      	movs	r2, #3
 8001e30:	4013      	ands	r3, r2
 8001e32:	60fb      	str	r3, [r7, #12]
    pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
 8001e34:	4b27      	ldr	r3, [pc, #156]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001e36:	68db      	ldr	r3, [r3, #12]
 8001e38:	091b      	lsrs	r3, r3, #4
 8001e3a:	2207      	movs	r2, #7
 8001e3c:	4013      	ands	r3, r2
 8001e3e:	3301      	adds	r3, #1
 8001e40:	60bb      	str	r3, [r7, #8]

    switch (pllsource)
 8001e42:	68fb      	ldr	r3, [r7, #12]
 8001e44:	2b03      	cmp	r3, #3
 8001e46:	d10d      	bne.n	8001e64 <HAL_RCC_GetSysClockFreq+0x88>
    {
      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001e48:	68b9      	ldr	r1, [r7, #8]
 8001e4a:	4824      	ldr	r0, [pc, #144]	@ (8001edc <HAL_RCC_GetSysClockFreq+0x100>)
 8001e4c:	f7fe f958 	bl	8000100 <__udivsi3>
 8001e50:	0003      	movs	r3, r0
 8001e52:	0019      	movs	r1, r3
 8001e54:	4b1f      	ldr	r3, [pc, #124]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001e56:	68db      	ldr	r3, [r3, #12]
 8001e58:	0a1b      	lsrs	r3, r3, #8
 8001e5a:	227f      	movs	r2, #127	@ 0x7f
 8001e5c:	4013      	ands	r3, r2
 8001e5e:	434b      	muls	r3, r1
 8001e60:	617b      	str	r3, [r7, #20]
        break;
 8001e62:	e00d      	b.n	8001e80 <HAL_RCC_GetSysClockFreq+0xa4>

      case RCC_PLLSOURCE_HSI:  /* HSI16 used as PLL clock source */
      default:                 /* HSI16 used as PLL clock source */
        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ;
 8001e64:	68b9      	ldr	r1, [r7, #8]
 8001e66:	481c      	ldr	r0, [pc, #112]	@ (8001ed8 <HAL_RCC_GetSysClockFreq+0xfc>)
 8001e68:	f7fe f94a 	bl	8000100 <__udivsi3>
 8001e6c:	0003      	movs	r3, r0
 8001e6e:	0019      	movs	r1, r3
 8001e70:	4b18      	ldr	r3, [pc, #96]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001e72:	68db      	ldr	r3, [r3, #12]
 8001e74:	0a1b      	lsrs	r3, r3, #8
 8001e76:	227f      	movs	r2, #127	@ 0x7f
 8001e78:	4013      	ands	r3, r2
 8001e7a:	434b      	muls	r3, r1
 8001e7c:	617b      	str	r3, [r7, #20]
        break;
 8001e7e:	46c0      	nop			@ (mov r8, r8)
    }
    pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
 8001e80:	4b14      	ldr	r3, [pc, #80]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001e82:	68db      	ldr	r3, [r3, #12]
 8001e84:	0f5b      	lsrs	r3, r3, #29
 8001e86:	2207      	movs	r2, #7
 8001e88:	4013      	ands	r3, r2
 8001e8a:	3301      	adds	r3, #1
 8001e8c:	607b      	str	r3, [r7, #4]
    sysclockfreq = pllvco / pllr;
 8001e8e:	6879      	ldr	r1, [r7, #4]
 8001e90:	6978      	ldr	r0, [r7, #20]
 8001e92:	f7fe f935 	bl	8000100 <__udivsi3>
 8001e96:	0003      	movs	r3, r0
 8001e98:	613b      	str	r3, [r7, #16]
 8001e9a:	e015      	b.n	8001ec8 <HAL_RCC_GetSysClockFreq+0xec>
  }
  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
 8001e9c:	4b0d      	ldr	r3, [pc, #52]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001e9e:	689b      	ldr	r3, [r3, #8]
 8001ea0:	2238      	movs	r2, #56	@ 0x38
 8001ea2:	4013      	ands	r3, r2
 8001ea4:	2b20      	cmp	r3, #32
 8001ea6:	d103      	bne.n	8001eb0 <HAL_RCC_GetSysClockFreq+0xd4>
  {
    /* LSE used as system clock source */
    sysclockfreq = LSE_VALUE;
 8001ea8:	2380      	movs	r3, #128	@ 0x80
 8001eaa:	021b      	lsls	r3, r3, #8
 8001eac:	613b      	str	r3, [r7, #16]
 8001eae:	e00b      	b.n	8001ec8 <HAL_RCC_GetSysClockFreq+0xec>
  }
  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
 8001eb0:	4b08      	ldr	r3, [pc, #32]	@ (8001ed4 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001eb2:	689b      	ldr	r3, [r3, #8]
 8001eb4:	2238      	movs	r2, #56	@ 0x38
 8001eb6:	4013      	ands	r3, r2
 8001eb8:	2b18      	cmp	r3, #24
 8001eba:	d103      	bne.n	8001ec4 <HAL_RCC_GetSysClockFreq+0xe8>
  {
    /* LSI used as system clock source */
    sysclockfreq = LSI_VALUE;
 8001ebc:	23fa      	movs	r3, #250	@ 0xfa
 8001ebe:	01db      	lsls	r3, r3, #7
 8001ec0:	613b      	str	r3, [r7, #16]
 8001ec2:	e001      	b.n	8001ec8 <HAL_RCC_GetSysClockFreq+0xec>
  }
  else
  {
    sysclockfreq = 0U;
 8001ec4:	2300      	movs	r3, #0
 8001ec6:	613b      	str	r3, [r7, #16]
  }

  return sysclockfreq;
 8001ec8:	693b      	ldr	r3, [r7, #16]
}
 8001eca:	0018      	movs	r0, r3
 8001ecc:	46bd      	mov	sp, r7
 8001ece:	b006      	add	sp, #24
 8001ed0:	bd80      	pop	{r7, pc}
 8001ed2:	46c0      	nop			@ (mov r8, r8)
 8001ed4:	40021000 	.word	0x40021000
 8001ed8:	00f42400 	.word	0x00f42400
 8001edc:	007a1200 	.word	0x007a1200

08001ee0 <HAL_TIM_Base_Init>:
  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
 8001ee0:	b580      	push	{r7, lr}
 8001ee2:	b082      	sub	sp, #8
 8001ee4:	af00      	add	r7, sp, #0
 8001ee6:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 8001ee8:	687b      	ldr	r3, [r7, #4]
 8001eea:	2b00      	cmp	r3, #0
 8001eec:	d101      	bne.n	8001ef2 <HAL_TIM_Base_Init+0x12>
  {
    return HAL_ERROR;
 8001eee:	2301      	movs	r3, #1
 8001ef0:	e04a      	b.n	8001f88 <HAL_TIM_Base_Init+0xa8>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 8001ef2:	687b      	ldr	r3, [r7, #4]
 8001ef4:	223d      	movs	r2, #61	@ 0x3d
 8001ef6:	5c9b      	ldrb	r3, [r3, r2]
 8001ef8:	b2db      	uxtb	r3, r3
 8001efa:	2b00      	cmp	r3, #0
 8001efc:	d107      	bne.n	8001f0e <HAL_TIM_Base_Init+0x2e>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 8001efe:	687b      	ldr	r3, [r7, #4]
 8001f00:	223c      	movs	r2, #60	@ 0x3c
 8001f02:	2100      	movs	r1, #0
 8001f04:	5499      	strb	r1, [r3, r2]
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
 8001f06:	687b      	ldr	r3, [r7, #4]
 8001f08:	0018      	movs	r0, r3
 8001f0a:	f7fe fcf7 	bl	80008fc <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8001f0e:	687b      	ldr	r3, [r7, #4]
 8001f10:	223d      	movs	r2, #61	@ 0x3d
 8001f12:	2102      	movs	r1, #2
 8001f14:	5499      	strb	r1, [r3, r2]

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8001f16:	687b      	ldr	r3, [r7, #4]
 8001f18:	681a      	ldr	r2, [r3, #0]
 8001f1a:	687b      	ldr	r3, [r7, #4]
 8001f1c:	3304      	adds	r3, #4
 8001f1e:	0019      	movs	r1, r3
 8001f20:	0010      	movs	r0, r2
 8001f22:	f000 fdcb 	bl	8002abc <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 8001f26:	687b      	ldr	r3, [r7, #4]
 8001f28:	2248      	movs	r2, #72	@ 0x48
 8001f2a:	2101      	movs	r1, #1
 8001f2c:	5499      	strb	r1, [r3, r2]

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8001f2e:	687b      	ldr	r3, [r7, #4]
 8001f30:	223e      	movs	r2, #62	@ 0x3e
 8001f32:	2101      	movs	r1, #1
 8001f34:	5499      	strb	r1, [r3, r2]
 8001f36:	687b      	ldr	r3, [r7, #4]
 8001f38:	223f      	movs	r2, #63	@ 0x3f
 8001f3a:	2101      	movs	r1, #1
 8001f3c:	5499      	strb	r1, [r3, r2]
 8001f3e:	687b      	ldr	r3, [r7, #4]
 8001f40:	2240      	movs	r2, #64	@ 0x40
 8001f42:	2101      	movs	r1, #1
 8001f44:	5499      	strb	r1, [r3, r2]
 8001f46:	687b      	ldr	r3, [r7, #4]
 8001f48:	2241      	movs	r2, #65	@ 0x41
 8001f4a:	2101      	movs	r1, #1
 8001f4c:	5499      	strb	r1, [r3, r2]
 8001f4e:	687b      	ldr	r3, [r7, #4]
 8001f50:	2242      	movs	r2, #66	@ 0x42
 8001f52:	2101      	movs	r1, #1
 8001f54:	5499      	strb	r1, [r3, r2]
 8001f56:	687b      	ldr	r3, [r7, #4]
 8001f58:	2243      	movs	r2, #67	@ 0x43
 8001f5a:	2101      	movs	r1, #1
 8001f5c:	5499      	strb	r1, [r3, r2]
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8001f5e:	687b      	ldr	r3, [r7, #4]
 8001f60:	2244      	movs	r2, #68	@ 0x44
 8001f62:	2101      	movs	r1, #1
 8001f64:	5499      	strb	r1, [r3, r2]
 8001f66:	687b      	ldr	r3, [r7, #4]
 8001f68:	2245      	movs	r2, #69	@ 0x45
 8001f6a:	2101      	movs	r1, #1
 8001f6c:	5499      	strb	r1, [r3, r2]
 8001f6e:	687b      	ldr	r3, [r7, #4]
 8001f70:	2246      	movs	r2, #70	@ 0x46
 8001f72:	2101      	movs	r1, #1
 8001f74:	5499      	strb	r1, [r3, r2]
 8001f76:	687b      	ldr	r3, [r7, #4]
 8001f78:	2247      	movs	r2, #71	@ 0x47
 8001f7a:	2101      	movs	r1, #1
 8001f7c:	5499      	strb	r1, [r3, r2]

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 8001f7e:	687b      	ldr	r3, [r7, #4]
 8001f80:	223d      	movs	r2, #61	@ 0x3d
 8001f82:	2101      	movs	r1, #1
 8001f84:	5499      	strb	r1, [r3, r2]

  return HAL_OK;
 8001f86:	2300      	movs	r3, #0
}
 8001f88:	0018      	movs	r0, r3
 8001f8a:	46bd      	mov	sp, r7
 8001f8c:	b002      	add	sp, #8
 8001f8e:	bd80      	pop	{r7, pc}

08001f90 <HAL_TIM_IC_Init>:
  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
  * @param  htim TIM Input Capture handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
{
 8001f90:	b580      	push	{r7, lr}
 8001f92:	b082      	sub	sp, #8
 8001f94:	af00      	add	r7, sp, #0
 8001f96:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 8001f98:	687b      	ldr	r3, [r7, #4]
 8001f9a:	2b00      	cmp	r3, #0
 8001f9c:	d101      	bne.n	8001fa2 <HAL_TIM_IC_Init+0x12>
  {
    return HAL_ERROR;
 8001f9e:	2301      	movs	r3, #1
 8001fa0:	e04a      	b.n	8002038 <HAL_TIM_IC_Init+0xa8>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 8001fa2:	687b      	ldr	r3, [r7, #4]
 8001fa4:	223d      	movs	r2, #61	@ 0x3d
 8001fa6:	5c9b      	ldrb	r3, [r3, r2]
 8001fa8:	b2db      	uxtb	r3, r3
 8001faa:	2b00      	cmp	r3, #0
 8001fac:	d107      	bne.n	8001fbe <HAL_TIM_IC_Init+0x2e>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 8001fae:	687b      	ldr	r3, [r7, #4]
 8001fb0:	223c      	movs	r2, #60	@ 0x3c
 8001fb2:	2100      	movs	r1, #0
 8001fb4:	5499      	strb	r1, [r3, r2]
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->IC_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIM_IC_MspInit(htim);
 8001fb6:	687b      	ldr	r3, [r7, #4]
 8001fb8:	0018      	movs	r0, r3
 8001fba:	f000 f841 	bl	8002040 <HAL_TIM_IC_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8001fbe:	687b      	ldr	r3, [r7, #4]
 8001fc0:	223d      	movs	r2, #61	@ 0x3d
 8001fc2:	2102      	movs	r1, #2
 8001fc4:	5499      	strb	r1, [r3, r2]

  /* Init the base time for the input capture */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8001fc6:	687b      	ldr	r3, [r7, #4]
 8001fc8:	681a      	ldr	r2, [r3, #0]
 8001fca:	687b      	ldr	r3, [r7, #4]
 8001fcc:	3304      	adds	r3, #4
 8001fce:	0019      	movs	r1, r3
 8001fd0:	0010      	movs	r0, r2
 8001fd2:	f000 fd73 	bl	8002abc <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 8001fd6:	687b      	ldr	r3, [r7, #4]
 8001fd8:	2248      	movs	r2, #72	@ 0x48
 8001fda:	2101      	movs	r1, #1
 8001fdc:	5499      	strb	r1, [r3, r2]

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8001fde:	687b      	ldr	r3, [r7, #4]
 8001fe0:	223e      	movs	r2, #62	@ 0x3e
 8001fe2:	2101      	movs	r1, #1
 8001fe4:	5499      	strb	r1, [r3, r2]
 8001fe6:	687b      	ldr	r3, [r7, #4]
 8001fe8:	223f      	movs	r2, #63	@ 0x3f
 8001fea:	2101      	movs	r1, #1
 8001fec:	5499      	strb	r1, [r3, r2]
 8001fee:	687b      	ldr	r3, [r7, #4]
 8001ff0:	2240      	movs	r2, #64	@ 0x40
 8001ff2:	2101      	movs	r1, #1
 8001ff4:	5499      	strb	r1, [r3, r2]
 8001ff6:	687b      	ldr	r3, [r7, #4]
 8001ff8:	2241      	movs	r2, #65	@ 0x41
 8001ffa:	2101      	movs	r1, #1
 8001ffc:	5499      	strb	r1, [r3, r2]
 8001ffe:	687b      	ldr	r3, [r7, #4]
 8002000:	2242      	movs	r2, #66	@ 0x42
 8002002:	2101      	movs	r1, #1
 8002004:	5499      	strb	r1, [r3, r2]
 8002006:	687b      	ldr	r3, [r7, #4]
 8002008:	2243      	movs	r2, #67	@ 0x43
 800200a:	2101      	movs	r1, #1
 800200c:	5499      	strb	r1, [r3, r2]
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800200e:	687b      	ldr	r3, [r7, #4]
 8002010:	2244      	movs	r2, #68	@ 0x44
 8002012:	2101      	movs	r1, #1
 8002014:	5499      	strb	r1, [r3, r2]
 8002016:	687b      	ldr	r3, [r7, #4]
 8002018:	2245      	movs	r2, #69	@ 0x45
 800201a:	2101      	movs	r1, #1
 800201c:	5499      	strb	r1, [r3, r2]
 800201e:	687b      	ldr	r3, [r7, #4]
 8002020:	2246      	movs	r2, #70	@ 0x46
 8002022:	2101      	movs	r1, #1
 8002024:	5499      	strb	r1, [r3, r2]
 8002026:	687b      	ldr	r3, [r7, #4]
 8002028:	2247      	movs	r2, #71	@ 0x47
 800202a:	2101      	movs	r1, #1
 800202c:	5499      	strb	r1, [r3, r2]

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 800202e:	687b      	ldr	r3, [r7, #4]
 8002030:	223d      	movs	r2, #61	@ 0x3d
 8002032:	2101      	movs	r1, #1
 8002034:	5499      	strb	r1, [r3, r2]

  return HAL_OK;
 8002036:	2300      	movs	r3, #0
}
 8002038:	0018      	movs	r0, r3
 800203a:	46bd      	mov	sp, r7
 800203c:	b002      	add	sp, #8
 800203e:	bd80      	pop	{r7, pc}

08002040 <HAL_TIM_IC_MspInit>:
  * @brief  Initializes the TIM Input Capture MSP.
  * @param  htim TIM Input Capture handle
  * @retval None
  */
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
{
 8002040:	b580      	push	{r7, lr}
 8002042:	b082      	sub	sp, #8
 8002044:	af00      	add	r7, sp, #0
 8002046:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_MspInit could be implemented in the user file
   */
}
 8002048:	46c0      	nop			@ (mov r8, r8)
 800204a:	46bd      	mov	sp, r7
 800204c:	b002      	add	sp, #8
 800204e:	bd80      	pop	{r7, pc}

08002050 <HAL_TIM_IC_Start_DMA>:
  * @param  pData The destination Buffer address.
  * @param  Length The length of data to be transferred from TIM peripheral to memory.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
 8002050:	b580      	push	{r7, lr}
 8002052:	b086      	sub	sp, #24
 8002054:	af00      	add	r7, sp, #0
 8002056:	60f8      	str	r0, [r7, #12]
 8002058:	60b9      	str	r1, [r7, #8]
 800205a:	607a      	str	r2, [r7, #4]
 800205c:	001a      	movs	r2, r3
 800205e:	1cbb      	adds	r3, r7, #2
 8002060:	801a      	strh	r2, [r3, #0]
  HAL_StatusTypeDef status = HAL_OK;
 8002062:	2317      	movs	r3, #23
 8002064:	18fb      	adds	r3, r7, r3
 8002066:	2200      	movs	r2, #0
 8002068:	701a      	strb	r2, [r3, #0]
  uint32_t tmpsmcr;

  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
 800206a:	68bb      	ldr	r3, [r7, #8]
 800206c:	2b00      	cmp	r3, #0
 800206e:	d104      	bne.n	800207a <HAL_TIM_IC_Start_DMA+0x2a>
 8002070:	68fb      	ldr	r3, [r7, #12]
 8002072:	223e      	movs	r2, #62	@ 0x3e
 8002074:	5c9b      	ldrb	r3, [r3, r2]
 8002076:	b2db      	uxtb	r3, r3
 8002078:	e023      	b.n	80020c2 <HAL_TIM_IC_Start_DMA+0x72>
 800207a:	68bb      	ldr	r3, [r7, #8]
 800207c:	2b04      	cmp	r3, #4
 800207e:	d104      	bne.n	800208a <HAL_TIM_IC_Start_DMA+0x3a>
 8002080:	68fb      	ldr	r3, [r7, #12]
 8002082:	223f      	movs	r2, #63	@ 0x3f
 8002084:	5c9b      	ldrb	r3, [r3, r2]
 8002086:	b2db      	uxtb	r3, r3
 8002088:	e01b      	b.n	80020c2 <HAL_TIM_IC_Start_DMA+0x72>
 800208a:	68bb      	ldr	r3, [r7, #8]
 800208c:	2b08      	cmp	r3, #8
 800208e:	d104      	bne.n	800209a <HAL_TIM_IC_Start_DMA+0x4a>
 8002090:	68fb      	ldr	r3, [r7, #12]
 8002092:	2240      	movs	r2, #64	@ 0x40
 8002094:	5c9b      	ldrb	r3, [r3, r2]
 8002096:	b2db      	uxtb	r3, r3
 8002098:	e013      	b.n	80020c2 <HAL_TIM_IC_Start_DMA+0x72>
 800209a:	68bb      	ldr	r3, [r7, #8]
 800209c:	2b0c      	cmp	r3, #12
 800209e:	d104      	bne.n	80020aa <HAL_TIM_IC_Start_DMA+0x5a>
 80020a0:	68fb      	ldr	r3, [r7, #12]
 80020a2:	2241      	movs	r2, #65	@ 0x41
 80020a4:	5c9b      	ldrb	r3, [r3, r2]
 80020a6:	b2db      	uxtb	r3, r3
 80020a8:	e00b      	b.n	80020c2 <HAL_TIM_IC_Start_DMA+0x72>
 80020aa:	68bb      	ldr	r3, [r7, #8]
 80020ac:	2b10      	cmp	r3, #16
 80020ae:	d104      	bne.n	80020ba <HAL_TIM_IC_Start_DMA+0x6a>
 80020b0:	68fb      	ldr	r3, [r7, #12]
 80020b2:	2242      	movs	r2, #66	@ 0x42
 80020b4:	5c9b      	ldrb	r3, [r3, r2]
 80020b6:	b2db      	uxtb	r3, r3
 80020b8:	e003      	b.n	80020c2 <HAL_TIM_IC_Start_DMA+0x72>
 80020ba:	68fb      	ldr	r3, [r7, #12]
 80020bc:	2243      	movs	r2, #67	@ 0x43
 80020be:	5c9b      	ldrb	r3, [r3, r2]
 80020c0:	b2db      	uxtb	r3, r3
 80020c2:	2216      	movs	r2, #22
 80020c4:	18ba      	adds	r2, r7, r2
 80020c6:	7013      	strb	r3, [r2, #0]
  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
 80020c8:	68bb      	ldr	r3, [r7, #8]
 80020ca:	2b00      	cmp	r3, #0
 80020cc:	d104      	bne.n	80020d8 <HAL_TIM_IC_Start_DMA+0x88>
 80020ce:	68fb      	ldr	r3, [r7, #12]
 80020d0:	2244      	movs	r2, #68	@ 0x44
 80020d2:	5c9b      	ldrb	r3, [r3, r2]
 80020d4:	b2db      	uxtb	r3, r3
 80020d6:	e013      	b.n	8002100 <HAL_TIM_IC_Start_DMA+0xb0>
 80020d8:	68bb      	ldr	r3, [r7, #8]
 80020da:	2b04      	cmp	r3, #4
 80020dc:	d104      	bne.n	80020e8 <HAL_TIM_IC_Start_DMA+0x98>
 80020de:	68fb      	ldr	r3, [r7, #12]
 80020e0:	2245      	movs	r2, #69	@ 0x45
 80020e2:	5c9b      	ldrb	r3, [r3, r2]
 80020e4:	b2db      	uxtb	r3, r3
 80020e6:	e00b      	b.n	8002100 <HAL_TIM_IC_Start_DMA+0xb0>
 80020e8:	68bb      	ldr	r3, [r7, #8]
 80020ea:	2b08      	cmp	r3, #8
 80020ec:	d104      	bne.n	80020f8 <HAL_TIM_IC_Start_DMA+0xa8>
 80020ee:	68fb      	ldr	r3, [r7, #12]
 80020f0:	2246      	movs	r2, #70	@ 0x46
 80020f2:	5c9b      	ldrb	r3, [r3, r2]
 80020f4:	b2db      	uxtb	r3, r3
 80020f6:	e003      	b.n	8002100 <HAL_TIM_IC_Start_DMA+0xb0>
 80020f8:	68fb      	ldr	r3, [r7, #12]
 80020fa:	2247      	movs	r2, #71	@ 0x47
 80020fc:	5c9b      	ldrb	r3, [r3, r2]
 80020fe:	b2db      	uxtb	r3, r3
 8002100:	2115      	movs	r1, #21
 8002102:	187a      	adds	r2, r7, r1
 8002104:	7013      	strb	r3, [r2, #0]
  /* Check the parameters */
  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));

  /* Set the TIM channel state */
  if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
 8002106:	2316      	movs	r3, #22
 8002108:	18fb      	adds	r3, r7, r3
 800210a:	781b      	ldrb	r3, [r3, #0]
 800210c:	2b02      	cmp	r3, #2
 800210e:	d003      	beq.n	8002118 <HAL_TIM_IC_Start_DMA+0xc8>
      || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
 8002110:	187b      	adds	r3, r7, r1
 8002112:	781b      	ldrb	r3, [r3, #0]
 8002114:	2b02      	cmp	r3, #2
 8002116:	d101      	bne.n	800211c <HAL_TIM_IC_Start_DMA+0xcc>
  {
    return HAL_BUSY;
 8002118:	2302      	movs	r3, #2
 800211a:	e141      	b.n	80023a0 <HAL_TIM_IC_Start_DMA+0x350>
  }
  else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
 800211c:	2316      	movs	r3, #22
 800211e:	18fb      	adds	r3, r7, r3
 8002120:	781b      	ldrb	r3, [r3, #0]
 8002122:	2b01      	cmp	r3, #1
 8002124:	d156      	bne.n	80021d4 <HAL_TIM_IC_Start_DMA+0x184>
           && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
 8002126:	2315      	movs	r3, #21
 8002128:	18fb      	adds	r3, r7, r3
 800212a:	781b      	ldrb	r3, [r3, #0]
 800212c:	2b01      	cmp	r3, #1
 800212e:	d151      	bne.n	80021d4 <HAL_TIM_IC_Start_DMA+0x184>
  {
    if ((pData == NULL) || (Length == 0U))
 8002130:	687b      	ldr	r3, [r7, #4]
 8002132:	2b00      	cmp	r3, #0
 8002134:	d003      	beq.n	800213e <HAL_TIM_IC_Start_DMA+0xee>
 8002136:	1cbb      	adds	r3, r7, #2
 8002138:	881b      	ldrh	r3, [r3, #0]
 800213a:	2b00      	cmp	r3, #0
 800213c:	d101      	bne.n	8002142 <HAL_TIM_IC_Start_DMA+0xf2>
    {
      return HAL_ERROR;
 800213e:	2301      	movs	r3, #1
 8002140:	e12e      	b.n	80023a0 <HAL_TIM_IC_Start_DMA+0x350>
    }
    else
    {
      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 8002142:	68bb      	ldr	r3, [r7, #8]
 8002144:	2b00      	cmp	r3, #0
 8002146:	d104      	bne.n	8002152 <HAL_TIM_IC_Start_DMA+0x102>
 8002148:	68fb      	ldr	r3, [r7, #12]
 800214a:	223e      	movs	r2, #62	@ 0x3e
 800214c:	2102      	movs	r1, #2
 800214e:	5499      	strb	r1, [r3, r2]
 8002150:	e023      	b.n	800219a <HAL_TIM_IC_Start_DMA+0x14a>
 8002152:	68bb      	ldr	r3, [r7, #8]
 8002154:	2b04      	cmp	r3, #4
 8002156:	d104      	bne.n	8002162 <HAL_TIM_IC_Start_DMA+0x112>
 8002158:	68fb      	ldr	r3, [r7, #12]
 800215a:	223f      	movs	r2, #63	@ 0x3f
 800215c:	2102      	movs	r1, #2
 800215e:	5499      	strb	r1, [r3, r2]
 8002160:	e01b      	b.n	800219a <HAL_TIM_IC_Start_DMA+0x14a>
 8002162:	68bb      	ldr	r3, [r7, #8]
 8002164:	2b08      	cmp	r3, #8
 8002166:	d104      	bne.n	8002172 <HAL_TIM_IC_Start_DMA+0x122>
 8002168:	68fb      	ldr	r3, [r7, #12]
 800216a:	2240      	movs	r2, #64	@ 0x40
 800216c:	2102      	movs	r1, #2
 800216e:	5499      	strb	r1, [r3, r2]
 8002170:	e013      	b.n	800219a <HAL_TIM_IC_Start_DMA+0x14a>
 8002172:	68bb      	ldr	r3, [r7, #8]
 8002174:	2b0c      	cmp	r3, #12
 8002176:	d104      	bne.n	8002182 <HAL_TIM_IC_Start_DMA+0x132>
 8002178:	68fb      	ldr	r3, [r7, #12]
 800217a:	2241      	movs	r2, #65	@ 0x41
 800217c:	2102      	movs	r1, #2
 800217e:	5499      	strb	r1, [r3, r2]
 8002180:	e00b      	b.n	800219a <HAL_TIM_IC_Start_DMA+0x14a>
 8002182:	68bb      	ldr	r3, [r7, #8]
 8002184:	2b10      	cmp	r3, #16
 8002186:	d104      	bne.n	8002192 <HAL_TIM_IC_Start_DMA+0x142>
 8002188:	68fb      	ldr	r3, [r7, #12]
 800218a:	2242      	movs	r2, #66	@ 0x42
 800218c:	2102      	movs	r1, #2
 800218e:	5499      	strb	r1, [r3, r2]
 8002190:	e003      	b.n	800219a <HAL_TIM_IC_Start_DMA+0x14a>
 8002192:	68fb      	ldr	r3, [r7, #12]
 8002194:	2243      	movs	r2, #67	@ 0x43
 8002196:	2102      	movs	r1, #2
 8002198:	5499      	strb	r1, [r3, r2]
      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 800219a:	68bb      	ldr	r3, [r7, #8]
 800219c:	2b00      	cmp	r3, #0
 800219e:	d104      	bne.n	80021aa <HAL_TIM_IC_Start_DMA+0x15a>
 80021a0:	68fb      	ldr	r3, [r7, #12]
 80021a2:	2244      	movs	r2, #68	@ 0x44
 80021a4:	2102      	movs	r1, #2
 80021a6:	5499      	strb	r1, [r3, r2]
    if ((pData == NULL) || (Length == 0U))
 80021a8:	e016      	b.n	80021d8 <HAL_TIM_IC_Start_DMA+0x188>
      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 80021aa:	68bb      	ldr	r3, [r7, #8]
 80021ac:	2b04      	cmp	r3, #4
 80021ae:	d104      	bne.n	80021ba <HAL_TIM_IC_Start_DMA+0x16a>
 80021b0:	68fb      	ldr	r3, [r7, #12]
 80021b2:	2245      	movs	r2, #69	@ 0x45
 80021b4:	2102      	movs	r1, #2
 80021b6:	5499      	strb	r1, [r3, r2]
    if ((pData == NULL) || (Length == 0U))
 80021b8:	e00e      	b.n	80021d8 <HAL_TIM_IC_Start_DMA+0x188>
      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 80021ba:	68bb      	ldr	r3, [r7, #8]
 80021bc:	2b08      	cmp	r3, #8
 80021be:	d104      	bne.n	80021ca <HAL_TIM_IC_Start_DMA+0x17a>
 80021c0:	68fb      	ldr	r3, [r7, #12]
 80021c2:	2246      	movs	r2, #70	@ 0x46
 80021c4:	2102      	movs	r1, #2
 80021c6:	5499      	strb	r1, [r3, r2]
    if ((pData == NULL) || (Length == 0U))
 80021c8:	e006      	b.n	80021d8 <HAL_TIM_IC_Start_DMA+0x188>
      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 80021ca:	68fb      	ldr	r3, [r7, #12]
 80021cc:	2247      	movs	r2, #71	@ 0x47
 80021ce:	2102      	movs	r1, #2
 80021d0:	5499      	strb	r1, [r3, r2]
    if ((pData == NULL) || (Length == 0U))
 80021d2:	e001      	b.n	80021d8 <HAL_TIM_IC_Start_DMA+0x188>
    }
  }
  else
  {
    return HAL_ERROR;
 80021d4:	2301      	movs	r3, #1
 80021d6:	e0e3      	b.n	80023a0 <HAL_TIM_IC_Start_DMA+0x350>
  }

  /* Enable the Input Capture channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 80021d8:	68fb      	ldr	r3, [r7, #12]
 80021da:	681b      	ldr	r3, [r3, #0]
 80021dc:	68b9      	ldr	r1, [r7, #8]
 80021de:	2201      	movs	r2, #1
 80021e0:	0018      	movs	r0, r3
 80021e2:	f000 fe9b 	bl	8002f1c <TIM_CCxChannelCmd>

  switch (Channel)
 80021e6:	68bb      	ldr	r3, [r7, #8]
 80021e8:	2b0c      	cmp	r3, #12
 80021ea:	d100      	bne.n	80021ee <HAL_TIM_IC_Start_DMA+0x19e>
 80021ec:	e080      	b.n	80022f0 <HAL_TIM_IC_Start_DMA+0x2a0>
 80021ee:	68bb      	ldr	r3, [r7, #8]
 80021f0:	2b0c      	cmp	r3, #12
 80021f2:	d900      	bls.n	80021f6 <HAL_TIM_IC_Start_DMA+0x1a6>
 80021f4:	e0a1      	b.n	800233a <HAL_TIM_IC_Start_DMA+0x2ea>
 80021f6:	68bb      	ldr	r3, [r7, #8]
 80021f8:	2b08      	cmp	r3, #8
 80021fa:	d054      	beq.n	80022a6 <HAL_TIM_IC_Start_DMA+0x256>
 80021fc:	68bb      	ldr	r3, [r7, #8]
 80021fe:	2b08      	cmp	r3, #8
 8002200:	d900      	bls.n	8002204 <HAL_TIM_IC_Start_DMA+0x1b4>
 8002202:	e09a      	b.n	800233a <HAL_TIM_IC_Start_DMA+0x2ea>
 8002204:	68bb      	ldr	r3, [r7, #8]
 8002206:	2b00      	cmp	r3, #0
 8002208:	d003      	beq.n	8002212 <HAL_TIM_IC_Start_DMA+0x1c2>
 800220a:	68bb      	ldr	r3, [r7, #8]
 800220c:	2b04      	cmp	r3, #4
 800220e:	d025      	beq.n	800225c <HAL_TIM_IC_Start_DMA+0x20c>
 8002210:	e093      	b.n	800233a <HAL_TIM_IC_Start_DMA+0x2ea>
  {
    case TIM_CHANNEL_1:
    {
      /* Set the DMA capture callbacks */
      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
 8002212:	68fb      	ldr	r3, [r7, #12]
 8002214:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8002216:	4a64      	ldr	r2, [pc, #400]	@ (80023a8 <HAL_TIM_IC_Start_DMA+0x358>)
 8002218:	62da      	str	r2, [r3, #44]	@ 0x2c
      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
 800221a:	68fb      	ldr	r3, [r7, #12]
 800221c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800221e:	4a63      	ldr	r2, [pc, #396]	@ (80023ac <HAL_TIM_IC_Start_DMA+0x35c>)
 8002220:	631a      	str	r2, [r3, #48]	@ 0x30

      /* Set the DMA error callback */
      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
 8002222:	68fb      	ldr	r3, [r7, #12]
 8002224:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8002226:	4a62      	ldr	r2, [pc, #392]	@ (80023b0 <HAL_TIM_IC_Start_DMA+0x360>)
 8002228:	635a      	str	r2, [r3, #52]	@ 0x34

      /* Enable the DMA channel */
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
 800222a:	68fb      	ldr	r3, [r7, #12]
 800222c:	6a58      	ldr	r0, [r3, #36]	@ 0x24
 800222e:	68fb      	ldr	r3, [r7, #12]
 8002230:	681b      	ldr	r3, [r3, #0]
 8002232:	3334      	adds	r3, #52	@ 0x34
 8002234:	0019      	movs	r1, r3
 8002236:	687a      	ldr	r2, [r7, #4]
 8002238:	1cbb      	adds	r3, r7, #2
 800223a:	881b      	ldrh	r3, [r3, #0]
 800223c:	f7fe fe92 	bl	8000f64 <HAL_DMA_Start_IT>
 8002240:	1e03      	subs	r3, r0, #0
 8002242:	d001      	beq.n	8002248 <HAL_TIM_IC_Start_DMA+0x1f8>
                           Length) != HAL_OK)
      {
        /* Return error status */
        return HAL_ERROR;
 8002244:	2301      	movs	r3, #1
 8002246:	e0ab      	b.n	80023a0 <HAL_TIM_IC_Start_DMA+0x350>
      }
      /* Enable the TIM Capture/Compare 1 DMA request */
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
 8002248:	68fb      	ldr	r3, [r7, #12]
 800224a:	681b      	ldr	r3, [r3, #0]
 800224c:	68da      	ldr	r2, [r3, #12]
 800224e:	68fb      	ldr	r3, [r7, #12]
 8002250:	681b      	ldr	r3, [r3, #0]
 8002252:	2180      	movs	r1, #128	@ 0x80
 8002254:	0089      	lsls	r1, r1, #2
 8002256:	430a      	orrs	r2, r1
 8002258:	60da      	str	r2, [r3, #12]
      break;
 800225a:	e073      	b.n	8002344 <HAL_TIM_IC_Start_DMA+0x2f4>
    }

    case TIM_CHANNEL_2:
    {
      /* Set the DMA capture callbacks */
      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
 800225c:	68fb      	ldr	r3, [r7, #12]
 800225e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002260:	4a51      	ldr	r2, [pc, #324]	@ (80023a8 <HAL_TIM_IC_Start_DMA+0x358>)
 8002262:	62da      	str	r2, [r3, #44]	@ 0x2c
      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
 8002264:	68fb      	ldr	r3, [r7, #12]
 8002266:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002268:	4a50      	ldr	r2, [pc, #320]	@ (80023ac <HAL_TIM_IC_Start_DMA+0x35c>)
 800226a:	631a      	str	r2, [r3, #48]	@ 0x30

      /* Set the DMA error callback */
      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
 800226c:	68fb      	ldr	r3, [r7, #12]
 800226e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002270:	4a4f      	ldr	r2, [pc, #316]	@ (80023b0 <HAL_TIM_IC_Start_DMA+0x360>)
 8002272:	635a      	str	r2, [r3, #52]	@ 0x34

      /* Enable the DMA channel */
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
 8002274:	68fb      	ldr	r3, [r7, #12]
 8002276:	6a98      	ldr	r0, [r3, #40]	@ 0x28
 8002278:	68fb      	ldr	r3, [r7, #12]
 800227a:	681b      	ldr	r3, [r3, #0]
 800227c:	3338      	adds	r3, #56	@ 0x38
 800227e:	0019      	movs	r1, r3
 8002280:	687a      	ldr	r2, [r7, #4]
 8002282:	1cbb      	adds	r3, r7, #2
 8002284:	881b      	ldrh	r3, [r3, #0]
 8002286:	f7fe fe6d 	bl	8000f64 <HAL_DMA_Start_IT>
 800228a:	1e03      	subs	r3, r0, #0
 800228c:	d001      	beq.n	8002292 <HAL_TIM_IC_Start_DMA+0x242>
                           Length) != HAL_OK)
      {
        /* Return error status */
        return HAL_ERROR;
 800228e:	2301      	movs	r3, #1
 8002290:	e086      	b.n	80023a0 <HAL_TIM_IC_Start_DMA+0x350>
      }
      /* Enable the TIM Capture/Compare 2  DMA request */
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
 8002292:	68fb      	ldr	r3, [r7, #12]
 8002294:	681b      	ldr	r3, [r3, #0]
 8002296:	68da      	ldr	r2, [r3, #12]
 8002298:	68fb      	ldr	r3, [r7, #12]
 800229a:	681b      	ldr	r3, [r3, #0]
 800229c:	2180      	movs	r1, #128	@ 0x80
 800229e:	00c9      	lsls	r1, r1, #3
 80022a0:	430a      	orrs	r2, r1
 80022a2:	60da      	str	r2, [r3, #12]
      break;
 80022a4:	e04e      	b.n	8002344 <HAL_TIM_IC_Start_DMA+0x2f4>
    }

    case TIM_CHANNEL_3:
    {
      /* Set the DMA capture callbacks */
      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
 80022a6:	68fb      	ldr	r3, [r7, #12]
 80022a8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80022aa:	4a3f      	ldr	r2, [pc, #252]	@ (80023a8 <HAL_TIM_IC_Start_DMA+0x358>)
 80022ac:	62da      	str	r2, [r3, #44]	@ 0x2c
      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
 80022ae:	68fb      	ldr	r3, [r7, #12]
 80022b0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80022b2:	4a3e      	ldr	r2, [pc, #248]	@ (80023ac <HAL_TIM_IC_Start_DMA+0x35c>)
 80022b4:	631a      	str	r2, [r3, #48]	@ 0x30

      /* Set the DMA error callback */
      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
 80022b6:	68fb      	ldr	r3, [r7, #12]
 80022b8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80022ba:	4a3d      	ldr	r2, [pc, #244]	@ (80023b0 <HAL_TIM_IC_Start_DMA+0x360>)
 80022bc:	635a      	str	r2, [r3, #52]	@ 0x34

      /* Enable the DMA channel */
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
 80022be:	68fb      	ldr	r3, [r7, #12]
 80022c0:	6ad8      	ldr	r0, [r3, #44]	@ 0x2c
 80022c2:	68fb      	ldr	r3, [r7, #12]
 80022c4:	681b      	ldr	r3, [r3, #0]
 80022c6:	333c      	adds	r3, #60	@ 0x3c
 80022c8:	0019      	movs	r1, r3
 80022ca:	687a      	ldr	r2, [r7, #4]
 80022cc:	1cbb      	adds	r3, r7, #2
 80022ce:	881b      	ldrh	r3, [r3, #0]
 80022d0:	f7fe fe48 	bl	8000f64 <HAL_DMA_Start_IT>
 80022d4:	1e03      	subs	r3, r0, #0
 80022d6:	d001      	beq.n	80022dc <HAL_TIM_IC_Start_DMA+0x28c>
                           Length) != HAL_OK)
      {
        /* Return error status */
        return HAL_ERROR;
 80022d8:	2301      	movs	r3, #1
 80022da:	e061      	b.n	80023a0 <HAL_TIM_IC_Start_DMA+0x350>
      }
      /* Enable the TIM Capture/Compare 3  DMA request */
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
 80022dc:	68fb      	ldr	r3, [r7, #12]
 80022de:	681b      	ldr	r3, [r3, #0]
 80022e0:	68da      	ldr	r2, [r3, #12]
 80022e2:	68fb      	ldr	r3, [r7, #12]
 80022e4:	681b      	ldr	r3, [r3, #0]
 80022e6:	2180      	movs	r1, #128	@ 0x80
 80022e8:	0109      	lsls	r1, r1, #4
 80022ea:	430a      	orrs	r2, r1
 80022ec:	60da      	str	r2, [r3, #12]
      break;
 80022ee:	e029      	b.n	8002344 <HAL_TIM_IC_Start_DMA+0x2f4>
    }

    case TIM_CHANNEL_4:
    {
      /* Set the DMA capture callbacks */
      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
 80022f0:	68fb      	ldr	r3, [r7, #12]
 80022f2:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 80022f4:	4a2c      	ldr	r2, [pc, #176]	@ (80023a8 <HAL_TIM_IC_Start_DMA+0x358>)
 80022f6:	62da      	str	r2, [r3, #44]	@ 0x2c
      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
 80022f8:	68fb      	ldr	r3, [r7, #12]
 80022fa:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 80022fc:	4a2b      	ldr	r2, [pc, #172]	@ (80023ac <HAL_TIM_IC_Start_DMA+0x35c>)
 80022fe:	631a      	str	r2, [r3, #48]	@ 0x30

      /* Set the DMA error callback */
      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
 8002300:	68fb      	ldr	r3, [r7, #12]
 8002302:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8002304:	4a2a      	ldr	r2, [pc, #168]	@ (80023b0 <HAL_TIM_IC_Start_DMA+0x360>)
 8002306:	635a      	str	r2, [r3, #52]	@ 0x34

      /* Enable the DMA channel */
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
 8002308:	68fb      	ldr	r3, [r7, #12]
 800230a:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 800230c:	68fb      	ldr	r3, [r7, #12]
 800230e:	681b      	ldr	r3, [r3, #0]
 8002310:	3340      	adds	r3, #64	@ 0x40
 8002312:	0019      	movs	r1, r3
 8002314:	687a      	ldr	r2, [r7, #4]
 8002316:	1cbb      	adds	r3, r7, #2
 8002318:	881b      	ldrh	r3, [r3, #0]
 800231a:	f7fe fe23 	bl	8000f64 <HAL_DMA_Start_IT>
 800231e:	1e03      	subs	r3, r0, #0
 8002320:	d001      	beq.n	8002326 <HAL_TIM_IC_Start_DMA+0x2d6>
                           Length) != HAL_OK)
      {
        /* Return error status */
        return HAL_ERROR;
 8002322:	2301      	movs	r3, #1
 8002324:	e03c      	b.n	80023a0 <HAL_TIM_IC_Start_DMA+0x350>
      }
      /* Enable the TIM Capture/Compare 4  DMA request */
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
 8002326:	68fb      	ldr	r3, [r7, #12]
 8002328:	681b      	ldr	r3, [r3, #0]
 800232a:	68da      	ldr	r2, [r3, #12]
 800232c:	68fb      	ldr	r3, [r7, #12]
 800232e:	681b      	ldr	r3, [r3, #0]
 8002330:	2180      	movs	r1, #128	@ 0x80
 8002332:	0149      	lsls	r1, r1, #5
 8002334:	430a      	orrs	r2, r1
 8002336:	60da      	str	r2, [r3, #12]
      break;
 8002338:	e004      	b.n	8002344 <HAL_TIM_IC_Start_DMA+0x2f4>
    }

    default:
      status = HAL_ERROR;
 800233a:	2317      	movs	r3, #23
 800233c:	18fb      	adds	r3, r7, r3
 800233e:	2201      	movs	r2, #1
 8002340:	701a      	strb	r2, [r3, #0]
      break;
 8002342:	46c0      	nop			@ (mov r8, r8)
  }

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8002344:	68fb      	ldr	r3, [r7, #12]
 8002346:	681b      	ldr	r3, [r3, #0]
 8002348:	4a1a      	ldr	r2, [pc, #104]	@ (80023b4 <HAL_TIM_IC_Start_DMA+0x364>)
 800234a:	4293      	cmp	r3, r2
 800234c:	d004      	beq.n	8002358 <HAL_TIM_IC_Start_DMA+0x308>
 800234e:	68fb      	ldr	r3, [r7, #12]
 8002350:	681b      	ldr	r3, [r3, #0]
 8002352:	4a19      	ldr	r2, [pc, #100]	@ (80023b8 <HAL_TIM_IC_Start_DMA+0x368>)
 8002354:	4293      	cmp	r3, r2
 8002356:	d116      	bne.n	8002386 <HAL_TIM_IC_Start_DMA+0x336>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 8002358:	68fb      	ldr	r3, [r7, #12]
 800235a:	681b      	ldr	r3, [r3, #0]
 800235c:	689b      	ldr	r3, [r3, #8]
 800235e:	4a17      	ldr	r2, [pc, #92]	@ (80023bc <HAL_TIM_IC_Start_DMA+0x36c>)
 8002360:	4013      	ands	r3, r2
 8002362:	613b      	str	r3, [r7, #16]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8002364:	693b      	ldr	r3, [r7, #16]
 8002366:	2b06      	cmp	r3, #6
 8002368:	d016      	beq.n	8002398 <HAL_TIM_IC_Start_DMA+0x348>
 800236a:	693a      	ldr	r2, [r7, #16]
 800236c:	2380      	movs	r3, #128	@ 0x80
 800236e:	025b      	lsls	r3, r3, #9
 8002370:	429a      	cmp	r2, r3
 8002372:	d011      	beq.n	8002398 <HAL_TIM_IC_Start_DMA+0x348>
    {
      __HAL_TIM_ENABLE(htim);
 8002374:	68fb      	ldr	r3, [r7, #12]
 8002376:	681b      	ldr	r3, [r3, #0]
 8002378:	681a      	ldr	r2, [r3, #0]
 800237a:	68fb      	ldr	r3, [r7, #12]
 800237c:	681b      	ldr	r3, [r3, #0]
 800237e:	2101      	movs	r1, #1
 8002380:	430a      	orrs	r2, r1
 8002382:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8002384:	e008      	b.n	8002398 <HAL_TIM_IC_Start_DMA+0x348>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 8002386:	68fb      	ldr	r3, [r7, #12]
 8002388:	681b      	ldr	r3, [r3, #0]
 800238a:	681a      	ldr	r2, [r3, #0]
 800238c:	68fb      	ldr	r3, [r7, #12]
 800238e:	681b      	ldr	r3, [r3, #0]
 8002390:	2101      	movs	r1, #1
 8002392:	430a      	orrs	r2, r1
 8002394:	601a      	str	r2, [r3, #0]
 8002396:	e000      	b.n	800239a <HAL_TIM_IC_Start_DMA+0x34a>
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8002398:	46c0      	nop			@ (mov r8, r8)
  }

  /* Return function status */
  return status;
 800239a:	2317      	movs	r3, #23
 800239c:	18fb      	adds	r3, r7, r3
 800239e:	781b      	ldrb	r3, [r3, #0]
}
 80023a0:	0018      	movs	r0, r3
 80023a2:	46bd      	mov	sp, r7
 80023a4:	b006      	add	sp, #24
 80023a6:	bd80      	pop	{r7, pc}
 80023a8:	08002989 	.word	0x08002989
 80023ac:	08002a53 	.word	0x08002a53
 80023b0:	080028f5 	.word	0x080028f5
 80023b4:	40012c00 	.word	0x40012c00
 80023b8:	40000400 	.word	0x40000400
 80023bc:	00010007 	.word	0x00010007

080023c0 <HAL_TIM_IC_Stop_DMA>:
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
 80023c0:	b580      	push	{r7, lr}
 80023c2:	b084      	sub	sp, #16
 80023c4:	af00      	add	r7, sp, #0
 80023c6:	6078      	str	r0, [r7, #4]
 80023c8:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 80023ca:	230f      	movs	r3, #15
 80023cc:	18fb      	adds	r3, r7, r3
 80023ce:	2200      	movs	r2, #0
 80023d0:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));

  /* Disable the Input Capture channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
 80023d2:	687b      	ldr	r3, [r7, #4]
 80023d4:	681b      	ldr	r3, [r3, #0]
 80023d6:	6839      	ldr	r1, [r7, #0]
 80023d8:	2200      	movs	r2, #0
 80023da:	0018      	movs	r0, r3
 80023dc:	f000 fd9e 	bl	8002f1c <TIM_CCxChannelCmd>

  switch (Channel)
 80023e0:	683b      	ldr	r3, [r7, #0]
 80023e2:	2b0c      	cmp	r3, #12
 80023e4:	d039      	beq.n	800245a <HAL_TIM_IC_Stop_DMA+0x9a>
 80023e6:	683b      	ldr	r3, [r7, #0]
 80023e8:	2b0c      	cmp	r3, #12
 80023ea:	d844      	bhi.n	8002476 <HAL_TIM_IC_Stop_DMA+0xb6>
 80023ec:	683b      	ldr	r3, [r7, #0]
 80023ee:	2b08      	cmp	r3, #8
 80023f0:	d025      	beq.n	800243e <HAL_TIM_IC_Stop_DMA+0x7e>
 80023f2:	683b      	ldr	r3, [r7, #0]
 80023f4:	2b08      	cmp	r3, #8
 80023f6:	d83e      	bhi.n	8002476 <HAL_TIM_IC_Stop_DMA+0xb6>
 80023f8:	683b      	ldr	r3, [r7, #0]
 80023fa:	2b00      	cmp	r3, #0
 80023fc:	d003      	beq.n	8002406 <HAL_TIM_IC_Stop_DMA+0x46>
 80023fe:	683b      	ldr	r3, [r7, #0]
 8002400:	2b04      	cmp	r3, #4
 8002402:	d00e      	beq.n	8002422 <HAL_TIM_IC_Stop_DMA+0x62>
 8002404:	e037      	b.n	8002476 <HAL_TIM_IC_Stop_DMA+0xb6>
  {
    case TIM_CHANNEL_1:
    {
      /* Disable the TIM Capture/Compare 1 DMA request */
      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
 8002406:	687b      	ldr	r3, [r7, #4]
 8002408:	681b      	ldr	r3, [r3, #0]
 800240a:	68da      	ldr	r2, [r3, #12]
 800240c:	687b      	ldr	r3, [r7, #4]
 800240e:	681b      	ldr	r3, [r3, #0]
 8002410:	494f      	ldr	r1, [pc, #316]	@ (8002550 <HAL_TIM_IC_Stop_DMA+0x190>)
 8002412:	400a      	ands	r2, r1
 8002414:	60da      	str	r2, [r3, #12]
      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
 8002416:	687b      	ldr	r3, [r7, #4]
 8002418:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800241a:	0018      	movs	r0, r3
 800241c:	f7fe fe28 	bl	8001070 <HAL_DMA_Abort_IT>
      break;
 8002420:	e02e      	b.n	8002480 <HAL_TIM_IC_Stop_DMA+0xc0>
    }

    case TIM_CHANNEL_2:
    {
      /* Disable the TIM Capture/Compare 2 DMA request */
      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
 8002422:	687b      	ldr	r3, [r7, #4]
 8002424:	681b      	ldr	r3, [r3, #0]
 8002426:	68da      	ldr	r2, [r3, #12]
 8002428:	687b      	ldr	r3, [r7, #4]
 800242a:	681b      	ldr	r3, [r3, #0]
 800242c:	4949      	ldr	r1, [pc, #292]	@ (8002554 <HAL_TIM_IC_Stop_DMA+0x194>)
 800242e:	400a      	ands	r2, r1
 8002430:	60da      	str	r2, [r3, #12]
      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
 8002432:	687b      	ldr	r3, [r7, #4]
 8002434:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002436:	0018      	movs	r0, r3
 8002438:	f7fe fe1a 	bl	8001070 <HAL_DMA_Abort_IT>
      break;
 800243c:	e020      	b.n	8002480 <HAL_TIM_IC_Stop_DMA+0xc0>
    }

    case TIM_CHANNEL_3:
    {
      /* Disable the TIM Capture/Compare 3  DMA request */
      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
 800243e:	687b      	ldr	r3, [r7, #4]
 8002440:	681b      	ldr	r3, [r3, #0]
 8002442:	68da      	ldr	r2, [r3, #12]
 8002444:	687b      	ldr	r3, [r7, #4]
 8002446:	681b      	ldr	r3, [r3, #0]
 8002448:	4943      	ldr	r1, [pc, #268]	@ (8002558 <HAL_TIM_IC_Stop_DMA+0x198>)
 800244a:	400a      	ands	r2, r1
 800244c:	60da      	str	r2, [r3, #12]
      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
 800244e:	687b      	ldr	r3, [r7, #4]
 8002450:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8002452:	0018      	movs	r0, r3
 8002454:	f7fe fe0c 	bl	8001070 <HAL_DMA_Abort_IT>
      break;
 8002458:	e012      	b.n	8002480 <HAL_TIM_IC_Stop_DMA+0xc0>
    }

    case TIM_CHANNEL_4:
    {
      /* Disable the TIM Capture/Compare 4  DMA request */
      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
 800245a:	687b      	ldr	r3, [r7, #4]
 800245c:	681b      	ldr	r3, [r3, #0]
 800245e:	68da      	ldr	r2, [r3, #12]
 8002460:	687b      	ldr	r3, [r7, #4]
 8002462:	681b      	ldr	r3, [r3, #0]
 8002464:	493d      	ldr	r1, [pc, #244]	@ (800255c <HAL_TIM_IC_Stop_DMA+0x19c>)
 8002466:	400a      	ands	r2, r1
 8002468:	60da      	str	r2, [r3, #12]
      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
 800246a:	687b      	ldr	r3, [r7, #4]
 800246c:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800246e:	0018      	movs	r0, r3
 8002470:	f7fe fdfe 	bl	8001070 <HAL_DMA_Abort_IT>
      break;
 8002474:	e004      	b.n	8002480 <HAL_TIM_IC_Stop_DMA+0xc0>
    }

    default:
      status = HAL_ERROR;
 8002476:	230f      	movs	r3, #15
 8002478:	18fb      	adds	r3, r7, r3
 800247a:	2201      	movs	r2, #1
 800247c:	701a      	strb	r2, [r3, #0]
      break;
 800247e:	46c0      	nop			@ (mov r8, r8)
  }

  if (status == HAL_OK)
 8002480:	230f      	movs	r3, #15
 8002482:	18fb      	adds	r3, r7, r3
 8002484:	781b      	ldrb	r3, [r3, #0]
 8002486:	2b00      	cmp	r3, #0
 8002488:	d15b      	bne.n	8002542 <HAL_TIM_IC_Stop_DMA+0x182>
  {
    /* Disable the Peripheral */
    __HAL_TIM_DISABLE(htim);
 800248a:	687b      	ldr	r3, [r7, #4]
 800248c:	681b      	ldr	r3, [r3, #0]
 800248e:	6a1b      	ldr	r3, [r3, #32]
 8002490:	4a33      	ldr	r2, [pc, #204]	@ (8002560 <HAL_TIM_IC_Stop_DMA+0x1a0>)
 8002492:	4013      	ands	r3, r2
 8002494:	d10d      	bne.n	80024b2 <HAL_TIM_IC_Stop_DMA+0xf2>
 8002496:	687b      	ldr	r3, [r7, #4]
 8002498:	681b      	ldr	r3, [r3, #0]
 800249a:	6a1b      	ldr	r3, [r3, #32]
 800249c:	4a31      	ldr	r2, [pc, #196]	@ (8002564 <HAL_TIM_IC_Stop_DMA+0x1a4>)
 800249e:	4013      	ands	r3, r2
 80024a0:	d107      	bne.n	80024b2 <HAL_TIM_IC_Stop_DMA+0xf2>
 80024a2:	687b      	ldr	r3, [r7, #4]
 80024a4:	681b      	ldr	r3, [r3, #0]
 80024a6:	681a      	ldr	r2, [r3, #0]
 80024a8:	687b      	ldr	r3, [r7, #4]
 80024aa:	681b      	ldr	r3, [r3, #0]
 80024ac:	2101      	movs	r1, #1
 80024ae:	438a      	bics	r2, r1
 80024b0:	601a      	str	r2, [r3, #0]

    /* Set the TIM channel state */
    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
 80024b2:	683b      	ldr	r3, [r7, #0]
 80024b4:	2b00      	cmp	r3, #0
 80024b6:	d104      	bne.n	80024c2 <HAL_TIM_IC_Stop_DMA+0x102>
 80024b8:	687b      	ldr	r3, [r7, #4]
 80024ba:	223e      	movs	r2, #62	@ 0x3e
 80024bc:	2101      	movs	r1, #1
 80024be:	5499      	strb	r1, [r3, r2]
 80024c0:	e023      	b.n	800250a <HAL_TIM_IC_Stop_DMA+0x14a>
 80024c2:	683b      	ldr	r3, [r7, #0]
 80024c4:	2b04      	cmp	r3, #4
 80024c6:	d104      	bne.n	80024d2 <HAL_TIM_IC_Stop_DMA+0x112>
 80024c8:	687b      	ldr	r3, [r7, #4]
 80024ca:	223f      	movs	r2, #63	@ 0x3f
 80024cc:	2101      	movs	r1, #1
 80024ce:	5499      	strb	r1, [r3, r2]
 80024d0:	e01b      	b.n	800250a <HAL_TIM_IC_Stop_DMA+0x14a>
 80024d2:	683b      	ldr	r3, [r7, #0]
 80024d4:	2b08      	cmp	r3, #8
 80024d6:	d104      	bne.n	80024e2 <HAL_TIM_IC_Stop_DMA+0x122>
 80024d8:	687b      	ldr	r3, [r7, #4]
 80024da:	2240      	movs	r2, #64	@ 0x40
 80024dc:	2101      	movs	r1, #1
 80024de:	5499      	strb	r1, [r3, r2]
 80024e0:	e013      	b.n	800250a <HAL_TIM_IC_Stop_DMA+0x14a>
 80024e2:	683b      	ldr	r3, [r7, #0]
 80024e4:	2b0c      	cmp	r3, #12
 80024e6:	d104      	bne.n	80024f2 <HAL_TIM_IC_Stop_DMA+0x132>
 80024e8:	687b      	ldr	r3, [r7, #4]
 80024ea:	2241      	movs	r2, #65	@ 0x41
 80024ec:	2101      	movs	r1, #1
 80024ee:	5499      	strb	r1, [r3, r2]
 80024f0:	e00b      	b.n	800250a <HAL_TIM_IC_Stop_DMA+0x14a>
 80024f2:	683b      	ldr	r3, [r7, #0]
 80024f4:	2b10      	cmp	r3, #16
 80024f6:	d104      	bne.n	8002502 <HAL_TIM_IC_Stop_DMA+0x142>
 80024f8:	687b      	ldr	r3, [r7, #4]
 80024fa:	2242      	movs	r2, #66	@ 0x42
 80024fc:	2101      	movs	r1, #1
 80024fe:	5499      	strb	r1, [r3, r2]
 8002500:	e003      	b.n	800250a <HAL_TIM_IC_Stop_DMA+0x14a>
 8002502:	687b      	ldr	r3, [r7, #4]
 8002504:	2243      	movs	r2, #67	@ 0x43
 8002506:	2101      	movs	r1, #1
 8002508:	5499      	strb	r1, [r3, r2]
    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
 800250a:	683b      	ldr	r3, [r7, #0]
 800250c:	2b00      	cmp	r3, #0
 800250e:	d104      	bne.n	800251a <HAL_TIM_IC_Stop_DMA+0x15a>
 8002510:	687b      	ldr	r3, [r7, #4]
 8002512:	2244      	movs	r2, #68	@ 0x44
 8002514:	2101      	movs	r1, #1
 8002516:	5499      	strb	r1, [r3, r2]
 8002518:	e013      	b.n	8002542 <HAL_TIM_IC_Stop_DMA+0x182>
 800251a:	683b      	ldr	r3, [r7, #0]
 800251c:	2b04      	cmp	r3, #4
 800251e:	d104      	bne.n	800252a <HAL_TIM_IC_Stop_DMA+0x16a>
 8002520:	687b      	ldr	r3, [r7, #4]
 8002522:	2245      	movs	r2, #69	@ 0x45
 8002524:	2101      	movs	r1, #1
 8002526:	5499      	strb	r1, [r3, r2]
 8002528:	e00b      	b.n	8002542 <HAL_TIM_IC_Stop_DMA+0x182>
 800252a:	683b      	ldr	r3, [r7, #0]
 800252c:	2b08      	cmp	r3, #8
 800252e:	d104      	bne.n	800253a <HAL_TIM_IC_Stop_DMA+0x17a>
 8002530:	687b      	ldr	r3, [r7, #4]
 8002532:	2246      	movs	r2, #70	@ 0x46
 8002534:	2101      	movs	r1, #1
 8002536:	5499      	strb	r1, [r3, r2]
 8002538:	e003      	b.n	8002542 <HAL_TIM_IC_Stop_DMA+0x182>
 800253a:	687b      	ldr	r3, [r7, #4]
 800253c:	2247      	movs	r2, #71	@ 0x47
 800253e:	2101      	movs	r1, #1
 8002540:	5499      	strb	r1, [r3, r2]
  }

  /* Return function status */
  return status;
 8002542:	230f      	movs	r3, #15
 8002544:	18fb      	adds	r3, r7, r3
 8002546:	781b      	ldrb	r3, [r3, #0]
}
 8002548:	0018      	movs	r0, r3
 800254a:	46bd      	mov	sp, r7
 800254c:	b004      	add	sp, #16
 800254e:	bd80      	pop	{r7, pc}
 8002550:	fffffdff 	.word	0xfffffdff
 8002554:	fffffbff 	.word	0xfffffbff
 8002558:	fffff7ff 	.word	0xfffff7ff
 800255c:	ffffefff 	.word	0xffffefff
 8002560:	00001111 	.word	0x00001111
 8002564:	00000444 	.word	0x00000444

08002568 <HAL_TIM_IC_ConfigChannel>:
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
{
 8002568:	b580      	push	{r7, lr}
 800256a:	b086      	sub	sp, #24
 800256c:	af00      	add	r7, sp, #0
 800256e:	60f8      	str	r0, [r7, #12]
 8002570:	60b9      	str	r1, [r7, #8]
 8002572:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 8002574:	2317      	movs	r3, #23
 8002576:	18fb      	adds	r3, r7, r3
 8002578:	2200      	movs	r2, #0
 800257a:	701a      	strb	r2, [r3, #0]
  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));

  /* Process Locked */
  __HAL_LOCK(htim);
 800257c:	68fb      	ldr	r3, [r7, #12]
 800257e:	223c      	movs	r2, #60	@ 0x3c
 8002580:	5c9b      	ldrb	r3, [r3, r2]
 8002582:	2b01      	cmp	r3, #1
 8002584:	d101      	bne.n	800258a <HAL_TIM_IC_ConfigChannel+0x22>
 8002586:	2302      	movs	r3, #2
 8002588:	e08c      	b.n	80026a4 <HAL_TIM_IC_ConfigChannel+0x13c>
 800258a:	68fb      	ldr	r3, [r7, #12]
 800258c:	223c      	movs	r2, #60	@ 0x3c
 800258e:	2101      	movs	r1, #1
 8002590:	5499      	strb	r1, [r3, r2]

  if (Channel == TIM_CHANNEL_1)
 8002592:	687b      	ldr	r3, [r7, #4]
 8002594:	2b00      	cmp	r3, #0
 8002596:	d11b      	bne.n	80025d0 <HAL_TIM_IC_ConfigChannel+0x68>
  {
    /* TI1 Configuration */
    TIM_TI1_SetConfig(htim->Instance,
 8002598:	68fb      	ldr	r3, [r7, #12]
 800259a:	6818      	ldr	r0, [r3, #0]
                      sConfig->ICPolarity,
 800259c:	68bb      	ldr	r3, [r7, #8]
 800259e:	6819      	ldr	r1, [r3, #0]
                      sConfig->ICSelection,
 80025a0:	68bb      	ldr	r3, [r7, #8]
 80025a2:	685a      	ldr	r2, [r3, #4]
                      sConfig->ICFilter);
 80025a4:	68bb      	ldr	r3, [r7, #8]
 80025a6:	68db      	ldr	r3, [r3, #12]
    TIM_TI1_SetConfig(htim->Instance,
 80025a8:	f000 fb02 	bl	8002bb0 <TIM_TI1_SetConfig>

    /* Reset the IC1PSC Bits */
    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
 80025ac:	68fb      	ldr	r3, [r7, #12]
 80025ae:	681b      	ldr	r3, [r3, #0]
 80025b0:	699a      	ldr	r2, [r3, #24]
 80025b2:	68fb      	ldr	r3, [r7, #12]
 80025b4:	681b      	ldr	r3, [r3, #0]
 80025b6:	210c      	movs	r1, #12
 80025b8:	438a      	bics	r2, r1
 80025ba:	619a      	str	r2, [r3, #24]

    /* Set the IC1PSC value */
    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
 80025bc:	68fb      	ldr	r3, [r7, #12]
 80025be:	681b      	ldr	r3, [r3, #0]
 80025c0:	6999      	ldr	r1, [r3, #24]
 80025c2:	68bb      	ldr	r3, [r7, #8]
 80025c4:	689a      	ldr	r2, [r3, #8]
 80025c6:	68fb      	ldr	r3, [r7, #12]
 80025c8:	681b      	ldr	r3, [r3, #0]
 80025ca:	430a      	orrs	r2, r1
 80025cc:	619a      	str	r2, [r3, #24]
 80025ce:	e062      	b.n	8002696 <HAL_TIM_IC_ConfigChannel+0x12e>
  }
  else if (Channel == TIM_CHANNEL_2)
 80025d0:	687b      	ldr	r3, [r7, #4]
 80025d2:	2b04      	cmp	r3, #4
 80025d4:	d11c      	bne.n	8002610 <HAL_TIM_IC_ConfigChannel+0xa8>
  {
    /* TI2 Configuration */
    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

    TIM_TI2_SetConfig(htim->Instance,
 80025d6:	68fb      	ldr	r3, [r7, #12]
 80025d8:	6818      	ldr	r0, [r3, #0]
                      sConfig->ICPolarity,
 80025da:	68bb      	ldr	r3, [r7, #8]
 80025dc:	6819      	ldr	r1, [r3, #0]
                      sConfig->ICSelection,
 80025de:	68bb      	ldr	r3, [r7, #8]
 80025e0:	685a      	ldr	r2, [r3, #4]
                      sConfig->ICFilter);
 80025e2:	68bb      	ldr	r3, [r7, #8]
 80025e4:	68db      	ldr	r3, [r3, #12]
    TIM_TI2_SetConfig(htim->Instance,
 80025e6:	f000 fb63 	bl	8002cb0 <TIM_TI2_SetConfig>

    /* Reset the IC2PSC Bits */
    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
 80025ea:	68fb      	ldr	r3, [r7, #12]
 80025ec:	681b      	ldr	r3, [r3, #0]
 80025ee:	699a      	ldr	r2, [r3, #24]
 80025f0:	68fb      	ldr	r3, [r7, #12]
 80025f2:	681b      	ldr	r3, [r3, #0]
 80025f4:	492d      	ldr	r1, [pc, #180]	@ (80026ac <HAL_TIM_IC_ConfigChannel+0x144>)
 80025f6:	400a      	ands	r2, r1
 80025f8:	619a      	str	r2, [r3, #24]

    /* Set the IC2PSC value */
    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
 80025fa:	68fb      	ldr	r3, [r7, #12]
 80025fc:	681b      	ldr	r3, [r3, #0]
 80025fe:	6999      	ldr	r1, [r3, #24]
 8002600:	68bb      	ldr	r3, [r7, #8]
 8002602:	689b      	ldr	r3, [r3, #8]
 8002604:	021a      	lsls	r2, r3, #8
 8002606:	68fb      	ldr	r3, [r7, #12]
 8002608:	681b      	ldr	r3, [r3, #0]
 800260a:	430a      	orrs	r2, r1
 800260c:	619a      	str	r2, [r3, #24]
 800260e:	e042      	b.n	8002696 <HAL_TIM_IC_ConfigChannel+0x12e>
  }
  else if (Channel == TIM_CHANNEL_3)
 8002610:	687b      	ldr	r3, [r7, #4]
 8002612:	2b08      	cmp	r3, #8
 8002614:	d11b      	bne.n	800264e <HAL_TIM_IC_ConfigChannel+0xe6>
  {
    /* TI3 Configuration */
    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));

    TIM_TI3_SetConfig(htim->Instance,
 8002616:	68fb      	ldr	r3, [r7, #12]
 8002618:	6818      	ldr	r0, [r3, #0]
                      sConfig->ICPolarity,
 800261a:	68bb      	ldr	r3, [r7, #8]
 800261c:	6819      	ldr	r1, [r3, #0]
                      sConfig->ICSelection,
 800261e:	68bb      	ldr	r3, [r7, #8]
 8002620:	685a      	ldr	r2, [r3, #4]
                      sConfig->ICFilter);
 8002622:	68bb      	ldr	r3, [r7, #8]
 8002624:	68db      	ldr	r3, [r3, #12]
    TIM_TI3_SetConfig(htim->Instance,
 8002626:	f000 fbb7 	bl	8002d98 <TIM_TI3_SetConfig>

    /* Reset the IC3PSC Bits */
    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
 800262a:	68fb      	ldr	r3, [r7, #12]
 800262c:	681b      	ldr	r3, [r3, #0]
 800262e:	69da      	ldr	r2, [r3, #28]
 8002630:	68fb      	ldr	r3, [r7, #12]
 8002632:	681b      	ldr	r3, [r3, #0]
 8002634:	210c      	movs	r1, #12
 8002636:	438a      	bics	r2, r1
 8002638:	61da      	str	r2, [r3, #28]

    /* Set the IC3PSC value */
    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
 800263a:	68fb      	ldr	r3, [r7, #12]
 800263c:	681b      	ldr	r3, [r3, #0]
 800263e:	69d9      	ldr	r1, [r3, #28]
 8002640:	68bb      	ldr	r3, [r7, #8]
 8002642:	689a      	ldr	r2, [r3, #8]
 8002644:	68fb      	ldr	r3, [r7, #12]
 8002646:	681b      	ldr	r3, [r3, #0]
 8002648:	430a      	orrs	r2, r1
 800264a:	61da      	str	r2, [r3, #28]
 800264c:	e023      	b.n	8002696 <HAL_TIM_IC_ConfigChannel+0x12e>
  }
  else if (Channel == TIM_CHANNEL_4)
 800264e:	687b      	ldr	r3, [r7, #4]
 8002650:	2b0c      	cmp	r3, #12
 8002652:	d11c      	bne.n	800268e <HAL_TIM_IC_ConfigChannel+0x126>
  {
    /* TI4 Configuration */
    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));

    TIM_TI4_SetConfig(htim->Instance,
 8002654:	68fb      	ldr	r3, [r7, #12]
 8002656:	6818      	ldr	r0, [r3, #0]
                      sConfig->ICPolarity,
 8002658:	68bb      	ldr	r3, [r7, #8]
 800265a:	6819      	ldr	r1, [r3, #0]
                      sConfig->ICSelection,
 800265c:	68bb      	ldr	r3, [r7, #8]
 800265e:	685a      	ldr	r2, [r3, #4]
                      sConfig->ICFilter);
 8002660:	68bb      	ldr	r3, [r7, #8]
 8002662:	68db      	ldr	r3, [r3, #12]
    TIM_TI4_SetConfig(htim->Instance,
 8002664:	f000 fbd8 	bl	8002e18 <TIM_TI4_SetConfig>

    /* Reset the IC4PSC Bits */
    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
 8002668:	68fb      	ldr	r3, [r7, #12]
 800266a:	681b      	ldr	r3, [r3, #0]
 800266c:	69da      	ldr	r2, [r3, #28]
 800266e:	68fb      	ldr	r3, [r7, #12]
 8002670:	681b      	ldr	r3, [r3, #0]
 8002672:	490e      	ldr	r1, [pc, #56]	@ (80026ac <HAL_TIM_IC_ConfigChannel+0x144>)
 8002674:	400a      	ands	r2, r1
 8002676:	61da      	str	r2, [r3, #28]

    /* Set the IC4PSC value */
    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
 8002678:	68fb      	ldr	r3, [r7, #12]
 800267a:	681b      	ldr	r3, [r3, #0]
 800267c:	69d9      	ldr	r1, [r3, #28]
 800267e:	68bb      	ldr	r3, [r7, #8]
 8002680:	689b      	ldr	r3, [r3, #8]
 8002682:	021a      	lsls	r2, r3, #8
 8002684:	68fb      	ldr	r3, [r7, #12]
 8002686:	681b      	ldr	r3, [r3, #0]
 8002688:	430a      	orrs	r2, r1
 800268a:	61da      	str	r2, [r3, #28]
 800268c:	e003      	b.n	8002696 <HAL_TIM_IC_ConfigChannel+0x12e>
  }
  else
  {
    status = HAL_ERROR;
 800268e:	2317      	movs	r3, #23
 8002690:	18fb      	adds	r3, r7, r3
 8002692:	2201      	movs	r2, #1
 8002694:	701a      	strb	r2, [r3, #0]
  }

  __HAL_UNLOCK(htim);
 8002696:	68fb      	ldr	r3, [r7, #12]
 8002698:	223c      	movs	r2, #60	@ 0x3c
 800269a:	2100      	movs	r1, #0
 800269c:	5499      	strb	r1, [r3, r2]

  return status;
 800269e:	2317      	movs	r3, #23
 80026a0:	18fb      	adds	r3, r7, r3
 80026a2:	781b      	ldrb	r3, [r3, #0]
}
 80026a4:	0018      	movs	r0, r3
 80026a6:	46bd      	mov	sp, r7
 80026a8:	b006      	add	sp, #24
 80026aa:	bd80      	pop	{r7, pc}
 80026ac:	fffff3ff 	.word	0xfffff3ff

080026b0 <HAL_TIM_ConfigClockSource>:
  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  *         contains the clock source information for the TIM peripheral.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
 80026b0:	b580      	push	{r7, lr}
 80026b2:	b084      	sub	sp, #16
 80026b4:	af00      	add	r7, sp, #0
 80026b6:	6078      	str	r0, [r7, #4]
 80026b8:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 80026ba:	230f      	movs	r3, #15
 80026bc:	18fb      	adds	r3, r7, r3
 80026be:	2200      	movs	r2, #0
 80026c0:	701a      	strb	r2, [r3, #0]
  uint32_t tmpsmcr;

  /* Process Locked */
  __HAL_LOCK(htim);
 80026c2:	687b      	ldr	r3, [r7, #4]
 80026c4:	223c      	movs	r2, #60	@ 0x3c
 80026c6:	5c9b      	ldrb	r3, [r3, r2]
 80026c8:	2b01      	cmp	r3, #1
 80026ca:	d101      	bne.n	80026d0 <HAL_TIM_ConfigClockSource+0x20>
 80026cc:	2302      	movs	r3, #2
 80026ce:	e0bc      	b.n	800284a <HAL_TIM_ConfigClockSource+0x19a>
 80026d0:	687b      	ldr	r3, [r7, #4]
 80026d2:	223c      	movs	r2, #60	@ 0x3c
 80026d4:	2101      	movs	r1, #1
 80026d6:	5499      	strb	r1, [r3, r2]

  htim->State = HAL_TIM_STATE_BUSY;
 80026d8:	687b      	ldr	r3, [r7, #4]
 80026da:	223d      	movs	r2, #61	@ 0x3d
 80026dc:	2102      	movs	r1, #2
 80026de:	5499      	strb	r1, [r3, r2]

  /* Check the parameters */
  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));

  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  tmpsmcr = htim->Instance->SMCR;
 80026e0:	687b      	ldr	r3, [r7, #4]
 80026e2:	681b      	ldr	r3, [r3, #0]
 80026e4:	689b      	ldr	r3, [r3, #8]
 80026e6:	60bb      	str	r3, [r7, #8]
  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
 80026e8:	68bb      	ldr	r3, [r7, #8]
 80026ea:	4a5a      	ldr	r2, [pc, #360]	@ (8002854 <HAL_TIM_ConfigClockSource+0x1a4>)
 80026ec:	4013      	ands	r3, r2
 80026ee:	60bb      	str	r3, [r7, #8]
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 80026f0:	68bb      	ldr	r3, [r7, #8]
 80026f2:	4a59      	ldr	r2, [pc, #356]	@ (8002858 <HAL_TIM_ConfigClockSource+0x1a8>)
 80026f4:	4013      	ands	r3, r2
 80026f6:	60bb      	str	r3, [r7, #8]
  htim->Instance->SMCR = tmpsmcr;
 80026f8:	687b      	ldr	r3, [r7, #4]
 80026fa:	681b      	ldr	r3, [r3, #0]
 80026fc:	68ba      	ldr	r2, [r7, #8]
 80026fe:	609a      	str	r2, [r3, #8]

  switch (sClockSourceConfig->ClockSource)
 8002700:	683b      	ldr	r3, [r7, #0]
 8002702:	681b      	ldr	r3, [r3, #0]
 8002704:	2280      	movs	r2, #128	@ 0x80
 8002706:	0192      	lsls	r2, r2, #6
 8002708:	4293      	cmp	r3, r2
 800270a:	d040      	beq.n	800278e <HAL_TIM_ConfigClockSource+0xde>
 800270c:	2280      	movs	r2, #128	@ 0x80
 800270e:	0192      	lsls	r2, r2, #6
 8002710:	4293      	cmp	r3, r2
 8002712:	d900      	bls.n	8002716 <HAL_TIM_ConfigClockSource+0x66>
 8002714:	e088      	b.n	8002828 <HAL_TIM_ConfigClockSource+0x178>
 8002716:	2280      	movs	r2, #128	@ 0x80
 8002718:	0152      	lsls	r2, r2, #5
 800271a:	4293      	cmp	r3, r2
 800271c:	d100      	bne.n	8002720 <HAL_TIM_ConfigClockSource+0x70>
 800271e:	e088      	b.n	8002832 <HAL_TIM_ConfigClockSource+0x182>
 8002720:	2280      	movs	r2, #128	@ 0x80
 8002722:	0152      	lsls	r2, r2, #5
 8002724:	4293      	cmp	r3, r2
 8002726:	d900      	bls.n	800272a <HAL_TIM_ConfigClockSource+0x7a>
 8002728:	e07e      	b.n	8002828 <HAL_TIM_ConfigClockSource+0x178>
 800272a:	2b70      	cmp	r3, #112	@ 0x70
 800272c:	d018      	beq.n	8002760 <HAL_TIM_ConfigClockSource+0xb0>
 800272e:	d900      	bls.n	8002732 <HAL_TIM_ConfigClockSource+0x82>
 8002730:	e07a      	b.n	8002828 <HAL_TIM_ConfigClockSource+0x178>
 8002732:	2b60      	cmp	r3, #96	@ 0x60
 8002734:	d04f      	beq.n	80027d6 <HAL_TIM_ConfigClockSource+0x126>
 8002736:	d900      	bls.n	800273a <HAL_TIM_ConfigClockSource+0x8a>
 8002738:	e076      	b.n	8002828 <HAL_TIM_ConfigClockSource+0x178>
 800273a:	2b50      	cmp	r3, #80	@ 0x50
 800273c:	d03b      	beq.n	80027b6 <HAL_TIM_ConfigClockSource+0x106>
 800273e:	d900      	bls.n	8002742 <HAL_TIM_ConfigClockSource+0x92>
 8002740:	e072      	b.n	8002828 <HAL_TIM_ConfigClockSource+0x178>
 8002742:	2b40      	cmp	r3, #64	@ 0x40
 8002744:	d057      	beq.n	80027f6 <HAL_TIM_ConfigClockSource+0x146>
 8002746:	d900      	bls.n	800274a <HAL_TIM_ConfigClockSource+0x9a>
 8002748:	e06e      	b.n	8002828 <HAL_TIM_ConfigClockSource+0x178>
 800274a:	2b30      	cmp	r3, #48	@ 0x30
 800274c:	d063      	beq.n	8002816 <HAL_TIM_ConfigClockSource+0x166>
 800274e:	d86b      	bhi.n	8002828 <HAL_TIM_ConfigClockSource+0x178>
 8002750:	2b20      	cmp	r3, #32
 8002752:	d060      	beq.n	8002816 <HAL_TIM_ConfigClockSource+0x166>
 8002754:	d868      	bhi.n	8002828 <HAL_TIM_ConfigClockSource+0x178>
 8002756:	2b00      	cmp	r3, #0
 8002758:	d05d      	beq.n	8002816 <HAL_TIM_ConfigClockSource+0x166>
 800275a:	2b10      	cmp	r3, #16
 800275c:	d05b      	beq.n	8002816 <HAL_TIM_ConfigClockSource+0x166>
 800275e:	e063      	b.n	8002828 <HAL_TIM_ConfigClockSource+0x178>
      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      /* Configure the ETR Clock source */
      TIM_ETR_SetConfig(htim->Instance,
 8002760:	687b      	ldr	r3, [r7, #4]
 8002762:	6818      	ldr	r0, [r3, #0]
                        sClockSourceConfig->ClockPrescaler,
 8002764:	683b      	ldr	r3, [r7, #0]
 8002766:	6899      	ldr	r1, [r3, #8]
                        sClockSourceConfig->ClockPolarity,
 8002768:	683b      	ldr	r3, [r7, #0]
 800276a:	685a      	ldr	r2, [r3, #4]
                        sClockSourceConfig->ClockFilter);
 800276c:	683b      	ldr	r3, [r7, #0]
 800276e:	68db      	ldr	r3, [r3, #12]
      TIM_ETR_SetConfig(htim->Instance,
 8002770:	f000 fbb4 	bl	8002edc <TIM_ETR_SetConfig>

      /* Select the External clock mode1 and the ETRF trigger */
      tmpsmcr = htim->Instance->SMCR;
 8002774:	687b      	ldr	r3, [r7, #4]
 8002776:	681b      	ldr	r3, [r3, #0]
 8002778:	689b      	ldr	r3, [r3, #8]
 800277a:	60bb      	str	r3, [r7, #8]
      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
 800277c:	68bb      	ldr	r3, [r7, #8]
 800277e:	2277      	movs	r2, #119	@ 0x77
 8002780:	4313      	orrs	r3, r2
 8002782:	60bb      	str	r3, [r7, #8]
      /* Write to TIMx SMCR */
      htim->Instance->SMCR = tmpsmcr;
 8002784:	687b      	ldr	r3, [r7, #4]
 8002786:	681b      	ldr	r3, [r3, #0]
 8002788:	68ba      	ldr	r2, [r7, #8]
 800278a:	609a      	str	r2, [r3, #8]
      break;
 800278c:	e052      	b.n	8002834 <HAL_TIM_ConfigClockSource+0x184>
      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      /* Configure the ETR Clock source */
      TIM_ETR_SetConfig(htim->Instance,
 800278e:	687b      	ldr	r3, [r7, #4]
 8002790:	6818      	ldr	r0, [r3, #0]
                        sClockSourceConfig->ClockPrescaler,
 8002792:	683b      	ldr	r3, [r7, #0]
 8002794:	6899      	ldr	r1, [r3, #8]
                        sClockSourceConfig->ClockPolarity,
 8002796:	683b      	ldr	r3, [r7, #0]
 8002798:	685a      	ldr	r2, [r3, #4]
                        sClockSourceConfig->ClockFilter);
 800279a:	683b      	ldr	r3, [r7, #0]
 800279c:	68db      	ldr	r3, [r3, #12]
      TIM_ETR_SetConfig(htim->Instance,
 800279e:	f000 fb9d 	bl	8002edc <TIM_ETR_SetConfig>
      /* Enable the External clock mode2 */
      htim->Instance->SMCR |= TIM_SMCR_ECE;
 80027a2:	687b      	ldr	r3, [r7, #4]
 80027a4:	681b      	ldr	r3, [r3, #0]
 80027a6:	689a      	ldr	r2, [r3, #8]
 80027a8:	687b      	ldr	r3, [r7, #4]
 80027aa:	681b      	ldr	r3, [r3, #0]
 80027ac:	2180      	movs	r1, #128	@ 0x80
 80027ae:	01c9      	lsls	r1, r1, #7
 80027b0:	430a      	orrs	r2, r1
 80027b2:	609a      	str	r2, [r3, #8]
      break;
 80027b4:	e03e      	b.n	8002834 <HAL_TIM_ConfigClockSource+0x184>

      /* Check TI1 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI1_ConfigInputStage(htim->Instance,
 80027b6:	687b      	ldr	r3, [r7, #4]
 80027b8:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 80027ba:	683b      	ldr	r3, [r7, #0]
 80027bc:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 80027be:	683b      	ldr	r3, [r7, #0]
 80027c0:	68db      	ldr	r3, [r3, #12]
      TIM_TI1_ConfigInputStage(htim->Instance,
 80027c2:	001a      	movs	r2, r3
 80027c4:	f000 fa46 	bl	8002c54 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
 80027c8:	687b      	ldr	r3, [r7, #4]
 80027ca:	681b      	ldr	r3, [r3, #0]
 80027cc:	2150      	movs	r1, #80	@ 0x50
 80027ce:	0018      	movs	r0, r3
 80027d0:	f000 fb68 	bl	8002ea4 <TIM_ITRx_SetConfig>
      break;
 80027d4:	e02e      	b.n	8002834 <HAL_TIM_ConfigClockSource+0x184>

      /* Check TI2 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI2_ConfigInputStage(htim->Instance,
 80027d6:	687b      	ldr	r3, [r7, #4]
 80027d8:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 80027da:	683b      	ldr	r3, [r7, #0]
 80027dc:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 80027de:	683b      	ldr	r3, [r7, #0]
 80027e0:	68db      	ldr	r3, [r3, #12]
      TIM_TI2_ConfigInputStage(htim->Instance,
 80027e2:	001a      	movs	r2, r3
 80027e4:	f000 faa6 	bl	8002d34 <TIM_TI2_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
 80027e8:	687b      	ldr	r3, [r7, #4]
 80027ea:	681b      	ldr	r3, [r3, #0]
 80027ec:	2160      	movs	r1, #96	@ 0x60
 80027ee:	0018      	movs	r0, r3
 80027f0:	f000 fb58 	bl	8002ea4 <TIM_ITRx_SetConfig>
      break;
 80027f4:	e01e      	b.n	8002834 <HAL_TIM_ConfigClockSource+0x184>

      /* Check TI1 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI1_ConfigInputStage(htim->Instance,
 80027f6:	687b      	ldr	r3, [r7, #4]
 80027f8:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 80027fa:	683b      	ldr	r3, [r7, #0]
 80027fc:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 80027fe:	683b      	ldr	r3, [r7, #0]
 8002800:	68db      	ldr	r3, [r3, #12]
      TIM_TI1_ConfigInputStage(htim->Instance,
 8002802:	001a      	movs	r2, r3
 8002804:	f000 fa26 	bl	8002c54 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
 8002808:	687b      	ldr	r3, [r7, #4]
 800280a:	681b      	ldr	r3, [r3, #0]
 800280c:	2140      	movs	r1, #64	@ 0x40
 800280e:	0018      	movs	r0, r3
 8002810:	f000 fb48 	bl	8002ea4 <TIM_ITRx_SetConfig>
      break;
 8002814:	e00e      	b.n	8002834 <HAL_TIM_ConfigClockSource+0x184>
    case TIM_CLOCKSOURCE_ITR3:
    {
      /* Check whether or not the timer instance supports internal trigger input */
      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));

      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
 8002816:	687b      	ldr	r3, [r7, #4]
 8002818:	681a      	ldr	r2, [r3, #0]
 800281a:	683b      	ldr	r3, [r7, #0]
 800281c:	681b      	ldr	r3, [r3, #0]
 800281e:	0019      	movs	r1, r3
 8002820:	0010      	movs	r0, r2
 8002822:	f000 fb3f 	bl	8002ea4 <TIM_ITRx_SetConfig>
      break;
 8002826:	e005      	b.n	8002834 <HAL_TIM_ConfigClockSource+0x184>
    }

    default:
      status = HAL_ERROR;
 8002828:	230f      	movs	r3, #15
 800282a:	18fb      	adds	r3, r7, r3
 800282c:	2201      	movs	r2, #1
 800282e:	701a      	strb	r2, [r3, #0]
      break;
 8002830:	e000      	b.n	8002834 <HAL_TIM_ConfigClockSource+0x184>
      break;
 8002832:	46c0      	nop			@ (mov r8, r8)
  }
  htim->State = HAL_TIM_STATE_READY;
 8002834:	687b      	ldr	r3, [r7, #4]
 8002836:	223d      	movs	r2, #61	@ 0x3d
 8002838:	2101      	movs	r1, #1
 800283a:	5499      	strb	r1, [r3, r2]

  __HAL_UNLOCK(htim);
 800283c:	687b      	ldr	r3, [r7, #4]
 800283e:	223c      	movs	r2, #60	@ 0x3c
 8002840:	2100      	movs	r1, #0
 8002842:	5499      	strb	r1, [r3, r2]

  return status;
 8002844:	230f      	movs	r3, #15
 8002846:	18fb      	adds	r3, r7, r3
 8002848:	781b      	ldrb	r3, [r3, #0]
}
 800284a:	0018      	movs	r0, r3
 800284c:	46bd      	mov	sp, r7
 800284e:	b004      	add	sp, #16
 8002850:	bd80      	pop	{r7, pc}
 8002852:	46c0      	nop			@ (mov r8, r8)
 8002854:	ffceff88 	.word	0xffceff88
 8002858:	ffff00ff 	.word	0xffff00ff

0800285c <HAL_TIM_ReadCapturedValue>:
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  * @retval Captured value
  */
uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
{
 800285c:	b580      	push	{r7, lr}
 800285e:	b084      	sub	sp, #16
 8002860:	af00      	add	r7, sp, #0
 8002862:	6078      	str	r0, [r7, #4]
 8002864:	6039      	str	r1, [r7, #0]
  uint32_t tmpreg = 0U;
 8002866:	2300      	movs	r3, #0
 8002868:	60fb      	str	r3, [r7, #12]

  switch (Channel)
 800286a:	683b      	ldr	r3, [r7, #0]
 800286c:	2b0c      	cmp	r3, #12
 800286e:	d01e      	beq.n	80028ae <HAL_TIM_ReadCapturedValue+0x52>
 8002870:	683b      	ldr	r3, [r7, #0]
 8002872:	2b0c      	cmp	r3, #12
 8002874:	d820      	bhi.n	80028b8 <HAL_TIM_ReadCapturedValue+0x5c>
 8002876:	683b      	ldr	r3, [r7, #0]
 8002878:	2b08      	cmp	r3, #8
 800287a:	d013      	beq.n	80028a4 <HAL_TIM_ReadCapturedValue+0x48>
 800287c:	683b      	ldr	r3, [r7, #0]
 800287e:	2b08      	cmp	r3, #8
 8002880:	d81a      	bhi.n	80028b8 <HAL_TIM_ReadCapturedValue+0x5c>
 8002882:	683b      	ldr	r3, [r7, #0]
 8002884:	2b00      	cmp	r3, #0
 8002886:	d003      	beq.n	8002890 <HAL_TIM_ReadCapturedValue+0x34>
 8002888:	683b      	ldr	r3, [r7, #0]
 800288a:	2b04      	cmp	r3, #4
 800288c:	d005      	beq.n	800289a <HAL_TIM_ReadCapturedValue+0x3e>

      break;
    }

    default:
      break;
 800288e:	e013      	b.n	80028b8 <HAL_TIM_ReadCapturedValue+0x5c>
      tmpreg =  htim->Instance->CCR1;
 8002890:	687b      	ldr	r3, [r7, #4]
 8002892:	681b      	ldr	r3, [r3, #0]
 8002894:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8002896:	60fb      	str	r3, [r7, #12]
      break;
 8002898:	e00f      	b.n	80028ba <HAL_TIM_ReadCapturedValue+0x5e>
      tmpreg =   htim->Instance->CCR2;
 800289a:	687b      	ldr	r3, [r7, #4]
 800289c:	681b      	ldr	r3, [r3, #0]
 800289e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 80028a0:	60fb      	str	r3, [r7, #12]
      break;
 80028a2:	e00a      	b.n	80028ba <HAL_TIM_ReadCapturedValue+0x5e>
      tmpreg =   htim->Instance->CCR3;
 80028a4:	687b      	ldr	r3, [r7, #4]
 80028a6:	681b      	ldr	r3, [r3, #0]
 80028a8:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80028aa:	60fb      	str	r3, [r7, #12]
      break;
 80028ac:	e005      	b.n	80028ba <HAL_TIM_ReadCapturedValue+0x5e>
      tmpreg =   htim->Instance->CCR4;
 80028ae:	687b      	ldr	r3, [r7, #4]
 80028b0:	681b      	ldr	r3, [r3, #0]
 80028b2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80028b4:	60fb      	str	r3, [r7, #12]
      break;
 80028b6:	e000      	b.n	80028ba <HAL_TIM_ReadCapturedValue+0x5e>
      break;
 80028b8:	46c0      	nop			@ (mov r8, r8)
  }

  return tmpreg;
 80028ba:	68fb      	ldr	r3, [r7, #12]
}
 80028bc:	0018      	movs	r0, r3
 80028be:	46bd      	mov	sp, r7
 80028c0:	b004      	add	sp, #16
 80028c2:	bd80      	pop	{r7, pc}

080028c4 <HAL_TIM_IC_CaptureCallback>:
  * @brief  Input Capture callback in non-blocking mode
  * @param  htim TIM IC handle
  * @retval None
  */
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
 80028c4:	b580      	push	{r7, lr}
 80028c6:	b082      	sub	sp, #8
 80028c8:	af00      	add	r7, sp, #0
 80028ca:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
   */
}
 80028cc:	46c0      	nop			@ (mov r8, r8)
 80028ce:	46bd      	mov	sp, r7
 80028d0:	b002      	add	sp, #8
 80028d2:	bd80      	pop	{r7, pc}

080028d4 <HAL_TIM_IC_CaptureHalfCpltCallback>:
  * @brief  Input Capture half complete callback in non-blocking mode
  * @param  htim TIM IC handle
  * @retval None
  */
__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
{
 80028d4:	b580      	push	{r7, lr}
 80028d6:	b082      	sub	sp, #8
 80028d8:	af00      	add	r7, sp, #0
 80028da:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
   */
}
 80028dc:	46c0      	nop			@ (mov r8, r8)
 80028de:	46bd      	mov	sp, r7
 80028e0:	b002      	add	sp, #8
 80028e2:	bd80      	pop	{r7, pc}

080028e4 <HAL_TIM_ErrorCallback>:
  * @brief  Timer error callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
{
 80028e4:	b580      	push	{r7, lr}
 80028e6:	b082      	sub	sp, #8
 80028e8:	af00      	add	r7, sp, #0
 80028ea:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_ErrorCallback could be implemented in the user file
   */
}
 80028ec:	46c0      	nop			@ (mov r8, r8)
 80028ee:	46bd      	mov	sp, r7
 80028f0:	b002      	add	sp, #8
 80028f2:	bd80      	pop	{r7, pc}

080028f4 <TIM_DMAError>:
  * @brief  TIM DMA error callback
  * @param  hdma pointer to DMA handle.
  * @retval None
  */
void TIM_DMAError(DMA_HandleTypeDef *hdma)
{
 80028f4:	b580      	push	{r7, lr}
 80028f6:	b084      	sub	sp, #16
 80028f8:	af00      	add	r7, sp, #0
 80028fa:	6078      	str	r0, [r7, #4]
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 80028fc:	687b      	ldr	r3, [r7, #4]
 80028fe:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002900:	60fb      	str	r3, [r7, #12]

  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
 8002902:	68fb      	ldr	r3, [r7, #12]
 8002904:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8002906:	687a      	ldr	r2, [r7, #4]
 8002908:	429a      	cmp	r2, r3
 800290a:	d107      	bne.n	800291c <TIM_DMAError+0x28>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 800290c:	68fb      	ldr	r3, [r7, #12]
 800290e:	2201      	movs	r2, #1
 8002910:	771a      	strb	r2, [r3, #28]
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
 8002912:	68fb      	ldr	r3, [r7, #12]
 8002914:	223e      	movs	r2, #62	@ 0x3e
 8002916:	2101      	movs	r1, #1
 8002918:	5499      	strb	r1, [r3, r2]
 800291a:	e02a      	b.n	8002972 <TIM_DMAError+0x7e>
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
 800291c:	68fb      	ldr	r3, [r7, #12]
 800291e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002920:	687a      	ldr	r2, [r7, #4]
 8002922:	429a      	cmp	r2, r3
 8002924:	d107      	bne.n	8002936 <TIM_DMAError+0x42>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8002926:	68fb      	ldr	r3, [r7, #12]
 8002928:	2202      	movs	r2, #2
 800292a:	771a      	strb	r2, [r3, #28]
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
 800292c:	68fb      	ldr	r3, [r7, #12]
 800292e:	223f      	movs	r2, #63	@ 0x3f
 8002930:	2101      	movs	r1, #1
 8002932:	5499      	strb	r1, [r3, r2]
 8002934:	e01d      	b.n	8002972 <TIM_DMAError+0x7e>
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
 8002936:	68fb      	ldr	r3, [r7, #12]
 8002938:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800293a:	687a      	ldr	r2, [r7, #4]
 800293c:	429a      	cmp	r2, r3
 800293e:	d107      	bne.n	8002950 <TIM_DMAError+0x5c>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8002940:	68fb      	ldr	r3, [r7, #12]
 8002942:	2204      	movs	r2, #4
 8002944:	771a      	strb	r2, [r3, #28]
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
 8002946:	68fb      	ldr	r3, [r7, #12]
 8002948:	2240      	movs	r2, #64	@ 0x40
 800294a:	2101      	movs	r1, #1
 800294c:	5499      	strb	r1, [r3, r2]
 800294e:	e010      	b.n	8002972 <TIM_DMAError+0x7e>
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
 8002950:	68fb      	ldr	r3, [r7, #12]
 8002952:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8002954:	687a      	ldr	r2, [r7, #4]
 8002956:	429a      	cmp	r2, r3
 8002958:	d107      	bne.n	800296a <TIM_DMAError+0x76>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 800295a:	68fb      	ldr	r3, [r7, #12]
 800295c:	2208      	movs	r2, #8
 800295e:	771a      	strb	r2, [r3, #28]
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
 8002960:	68fb      	ldr	r3, [r7, #12]
 8002962:	2241      	movs	r2, #65	@ 0x41
 8002964:	2101      	movs	r1, #1
 8002966:	5499      	strb	r1, [r3, r2]
 8002968:	e003      	b.n	8002972 <TIM_DMAError+0x7e>
  }
  else
  {
    htim->State = HAL_TIM_STATE_READY;
 800296a:	68fb      	ldr	r3, [r7, #12]
 800296c:	223d      	movs	r2, #61	@ 0x3d
 800296e:	2101      	movs	r1, #1
 8002970:	5499      	strb	r1, [r3, r2]
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->ErrorCallback(htim);
#else
  HAL_TIM_ErrorCallback(htim);
 8002972:	68fb      	ldr	r3, [r7, #12]
 8002974:	0018      	movs	r0, r3
 8002976:	f7ff ffb5 	bl	80028e4 <HAL_TIM_ErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800297a:	68fb      	ldr	r3, [r7, #12]
 800297c:	2200      	movs	r2, #0
 800297e:	771a      	strb	r2, [r3, #28]
}
 8002980:	46c0      	nop			@ (mov r8, r8)
 8002982:	46bd      	mov	sp, r7
 8002984:	b004      	add	sp, #16
 8002986:	bd80      	pop	{r7, pc}

08002988 <TIM_DMACaptureCplt>:
  * @brief  TIM DMA Capture complete callback.
  * @param  hdma pointer to DMA handle.
  * @retval None
  */
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
{
 8002988:	b580      	push	{r7, lr}
 800298a:	b084      	sub	sp, #16
 800298c:	af00      	add	r7, sp, #0
 800298e:	6078      	str	r0, [r7, #4]
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8002990:	687b      	ldr	r3, [r7, #4]
 8002992:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002994:	60fb      	str	r3, [r7, #12]

  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
 8002996:	68fb      	ldr	r3, [r7, #12]
 8002998:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800299a:	687a      	ldr	r2, [r7, #4]
 800299c:	429a      	cmp	r2, r3
 800299e:	d10f      	bne.n	80029c0 <TIM_DMACaptureCplt+0x38>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80029a0:	68fb      	ldr	r3, [r7, #12]
 80029a2:	2201      	movs	r2, #1
 80029a4:	771a      	strb	r2, [r3, #28]

    if (hdma->Init.Mode == DMA_NORMAL)
 80029a6:	687b      	ldr	r3, [r7, #4]
 80029a8:	69db      	ldr	r3, [r3, #28]
 80029aa:	2b00      	cmp	r3, #0
 80029ac:	d146      	bne.n	8002a3c <TIM_DMACaptureCplt+0xb4>
    {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
 80029ae:	68fb      	ldr	r3, [r7, #12]
 80029b0:	223e      	movs	r2, #62	@ 0x3e
 80029b2:	2101      	movs	r1, #1
 80029b4:	5499      	strb	r1, [r3, r2]
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
 80029b6:	68fb      	ldr	r3, [r7, #12]
 80029b8:	2244      	movs	r2, #68	@ 0x44
 80029ba:	2101      	movs	r1, #1
 80029bc:	5499      	strb	r1, [r3, r2]
 80029be:	e03d      	b.n	8002a3c <TIM_DMACaptureCplt+0xb4>
    }
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
 80029c0:	68fb      	ldr	r3, [r7, #12]
 80029c2:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 80029c4:	687a      	ldr	r2, [r7, #4]
 80029c6:	429a      	cmp	r2, r3
 80029c8:	d10f      	bne.n	80029ea <TIM_DMACaptureCplt+0x62>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 80029ca:	68fb      	ldr	r3, [r7, #12]
 80029cc:	2202      	movs	r2, #2
 80029ce:	771a      	strb	r2, [r3, #28]

    if (hdma->Init.Mode == DMA_NORMAL)
 80029d0:	687b      	ldr	r3, [r7, #4]
 80029d2:	69db      	ldr	r3, [r3, #28]
 80029d4:	2b00      	cmp	r3, #0
 80029d6:	d131      	bne.n	8002a3c <TIM_DMACaptureCplt+0xb4>
    {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
 80029d8:	68fb      	ldr	r3, [r7, #12]
 80029da:	223f      	movs	r2, #63	@ 0x3f
 80029dc:	2101      	movs	r1, #1
 80029de:	5499      	strb	r1, [r3, r2]
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
 80029e0:	68fb      	ldr	r3, [r7, #12]
 80029e2:	2245      	movs	r2, #69	@ 0x45
 80029e4:	2101      	movs	r1, #1
 80029e6:	5499      	strb	r1, [r3, r2]
 80029e8:	e028      	b.n	8002a3c <TIM_DMACaptureCplt+0xb4>
    }
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
 80029ea:	68fb      	ldr	r3, [r7, #12]
 80029ec:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80029ee:	687a      	ldr	r2, [r7, #4]
 80029f0:	429a      	cmp	r2, r3
 80029f2:	d10f      	bne.n	8002a14 <TIM_DMACaptureCplt+0x8c>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 80029f4:	68fb      	ldr	r3, [r7, #12]
 80029f6:	2204      	movs	r2, #4
 80029f8:	771a      	strb	r2, [r3, #28]

    if (hdma->Init.Mode == DMA_NORMAL)
 80029fa:	687b      	ldr	r3, [r7, #4]
 80029fc:	69db      	ldr	r3, [r3, #28]
 80029fe:	2b00      	cmp	r3, #0
 8002a00:	d11c      	bne.n	8002a3c <TIM_DMACaptureCplt+0xb4>
    {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
 8002a02:	68fb      	ldr	r3, [r7, #12]
 8002a04:	2240      	movs	r2, #64	@ 0x40
 8002a06:	2101      	movs	r1, #1
 8002a08:	5499      	strb	r1, [r3, r2]
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
 8002a0a:	68fb      	ldr	r3, [r7, #12]
 8002a0c:	2246      	movs	r2, #70	@ 0x46
 8002a0e:	2101      	movs	r1, #1
 8002a10:	5499      	strb	r1, [r3, r2]
 8002a12:	e013      	b.n	8002a3c <TIM_DMACaptureCplt+0xb4>
    }
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
 8002a14:	68fb      	ldr	r3, [r7, #12]
 8002a16:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8002a18:	687a      	ldr	r2, [r7, #4]
 8002a1a:	429a      	cmp	r2, r3
 8002a1c:	d10e      	bne.n	8002a3c <TIM_DMACaptureCplt+0xb4>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 8002a1e:	68fb      	ldr	r3, [r7, #12]
 8002a20:	2208      	movs	r2, #8
 8002a22:	771a      	strb	r2, [r3, #28]

    if (hdma->Init.Mode == DMA_NORMAL)
 8002a24:	687b      	ldr	r3, [r7, #4]
 8002a26:	69db      	ldr	r3, [r3, #28]
 8002a28:	2b00      	cmp	r3, #0
 8002a2a:	d107      	bne.n	8002a3c <TIM_DMACaptureCplt+0xb4>
    {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
 8002a2c:	68fb      	ldr	r3, [r7, #12]
 8002a2e:	2241      	movs	r2, #65	@ 0x41
 8002a30:	2101      	movs	r1, #1
 8002a32:	5499      	strb	r1, [r3, r2]
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
 8002a34:	68fb      	ldr	r3, [r7, #12]
 8002a36:	2247      	movs	r2, #71	@ 0x47
 8002a38:	2101      	movs	r1, #1
 8002a3a:	5499      	strb	r1, [r3, r2]
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->IC_CaptureCallback(htim);
#else
  HAL_TIM_IC_CaptureCallback(htim);
 8002a3c:	68fb      	ldr	r3, [r7, #12]
 8002a3e:	0018      	movs	r0, r3
 8002a40:	f7ff ff40 	bl	80028c4 <HAL_TIM_IC_CaptureCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8002a44:	68fb      	ldr	r3, [r7, #12]
 8002a46:	2200      	movs	r2, #0
 8002a48:	771a      	strb	r2, [r3, #28]
}
 8002a4a:	46c0      	nop			@ (mov r8, r8)
 8002a4c:	46bd      	mov	sp, r7
 8002a4e:	b004      	add	sp, #16
 8002a50:	bd80      	pop	{r7, pc}

08002a52 <TIM_DMACaptureHalfCplt>:
  * @brief  TIM DMA Capture half complete callback.
  * @param  hdma pointer to DMA handle.
  * @retval None
  */
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
{
 8002a52:	b580      	push	{r7, lr}
 8002a54:	b084      	sub	sp, #16
 8002a56:	af00      	add	r7, sp, #0
 8002a58:	6078      	str	r0, [r7, #4]
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8002a5a:	687b      	ldr	r3, [r7, #4]
 8002a5c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002a5e:	60fb      	str	r3, [r7, #12]

  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
 8002a60:	68fb      	ldr	r3, [r7, #12]
 8002a62:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8002a64:	687a      	ldr	r2, [r7, #4]
 8002a66:	429a      	cmp	r2, r3
 8002a68:	d103      	bne.n	8002a72 <TIM_DMACaptureHalfCplt+0x20>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 8002a6a:	68fb      	ldr	r3, [r7, #12]
 8002a6c:	2201      	movs	r2, #1
 8002a6e:	771a      	strb	r2, [r3, #28]
 8002a70:	e019      	b.n	8002aa6 <TIM_DMACaptureHalfCplt+0x54>
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
 8002a72:	68fb      	ldr	r3, [r7, #12]
 8002a74:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002a76:	687a      	ldr	r2, [r7, #4]
 8002a78:	429a      	cmp	r2, r3
 8002a7a:	d103      	bne.n	8002a84 <TIM_DMACaptureHalfCplt+0x32>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8002a7c:	68fb      	ldr	r3, [r7, #12]
 8002a7e:	2202      	movs	r2, #2
 8002a80:	771a      	strb	r2, [r3, #28]
 8002a82:	e010      	b.n	8002aa6 <TIM_DMACaptureHalfCplt+0x54>
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
 8002a84:	68fb      	ldr	r3, [r7, #12]
 8002a86:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8002a88:	687a      	ldr	r2, [r7, #4]
 8002a8a:	429a      	cmp	r2, r3
 8002a8c:	d103      	bne.n	8002a96 <TIM_DMACaptureHalfCplt+0x44>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8002a8e:	68fb      	ldr	r3, [r7, #12]
 8002a90:	2204      	movs	r2, #4
 8002a92:	771a      	strb	r2, [r3, #28]
 8002a94:	e007      	b.n	8002aa6 <TIM_DMACaptureHalfCplt+0x54>
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
 8002a96:	68fb      	ldr	r3, [r7, #12]
 8002a98:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8002a9a:	687a      	ldr	r2, [r7, #4]
 8002a9c:	429a      	cmp	r2, r3
 8002a9e:	d102      	bne.n	8002aa6 <TIM_DMACaptureHalfCplt+0x54>
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 8002aa0:	68fb      	ldr	r3, [r7, #12]
 8002aa2:	2208      	movs	r2, #8
 8002aa4:	771a      	strb	r2, [r3, #28]
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->IC_CaptureHalfCpltCallback(htim);
#else
  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
 8002aa6:	68fb      	ldr	r3, [r7, #12]
 8002aa8:	0018      	movs	r0, r3
 8002aaa:	f7ff ff13 	bl	80028d4 <HAL_TIM_IC_CaptureHalfCpltCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8002aae:	68fb      	ldr	r3, [r7, #12]
 8002ab0:	2200      	movs	r2, #0
 8002ab2:	771a      	strb	r2, [r3, #28]
}
 8002ab4:	46c0      	nop			@ (mov r8, r8)
 8002ab6:	46bd      	mov	sp, r7
 8002ab8:	b004      	add	sp, #16
 8002aba:	bd80      	pop	{r7, pc}

08002abc <TIM_Base_SetConfig>:
  * @param  TIMx TIM peripheral
  * @param  Structure TIM Base configuration structure
  * @retval None
  */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
 8002abc:	b580      	push	{r7, lr}
 8002abe:	b084      	sub	sp, #16
 8002ac0:	af00      	add	r7, sp, #0
 8002ac2:	6078      	str	r0, [r7, #4]
 8002ac4:	6039      	str	r1, [r7, #0]
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;
 8002ac6:	687b      	ldr	r3, [r7, #4]
 8002ac8:	681b      	ldr	r3, [r3, #0]
 8002aca:	60fb      	str	r3, [r7, #12]

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8002acc:	687b      	ldr	r3, [r7, #4]
 8002ace:	4a32      	ldr	r2, [pc, #200]	@ (8002b98 <TIM_Base_SetConfig+0xdc>)
 8002ad0:	4293      	cmp	r3, r2
 8002ad2:	d003      	beq.n	8002adc <TIM_Base_SetConfig+0x20>
 8002ad4:	687b      	ldr	r3, [r7, #4]
 8002ad6:	4a31      	ldr	r2, [pc, #196]	@ (8002b9c <TIM_Base_SetConfig+0xe0>)
 8002ad8:	4293      	cmp	r3, r2
 8002ada:	d108      	bne.n	8002aee <TIM_Base_SetConfig+0x32>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8002adc:	68fb      	ldr	r3, [r7, #12]
 8002ade:	2270      	movs	r2, #112	@ 0x70
 8002ae0:	4393      	bics	r3, r2
 8002ae2:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= Structure->CounterMode;
 8002ae4:	683b      	ldr	r3, [r7, #0]
 8002ae6:	685b      	ldr	r3, [r3, #4]
 8002ae8:	68fa      	ldr	r2, [r7, #12]
 8002aea:	4313      	orrs	r3, r2
 8002aec:	60fb      	str	r3, [r7, #12]
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 8002aee:	687b      	ldr	r3, [r7, #4]
 8002af0:	4a29      	ldr	r2, [pc, #164]	@ (8002b98 <TIM_Base_SetConfig+0xdc>)
 8002af2:	4293      	cmp	r3, r2
 8002af4:	d00f      	beq.n	8002b16 <TIM_Base_SetConfig+0x5a>
 8002af6:	687b      	ldr	r3, [r7, #4]
 8002af8:	4a28      	ldr	r2, [pc, #160]	@ (8002b9c <TIM_Base_SetConfig+0xe0>)
 8002afa:	4293      	cmp	r3, r2
 8002afc:	d00b      	beq.n	8002b16 <TIM_Base_SetConfig+0x5a>
 8002afe:	687b      	ldr	r3, [r7, #4]
 8002b00:	4a27      	ldr	r2, [pc, #156]	@ (8002ba0 <TIM_Base_SetConfig+0xe4>)
 8002b02:	4293      	cmp	r3, r2
 8002b04:	d007      	beq.n	8002b16 <TIM_Base_SetConfig+0x5a>
 8002b06:	687b      	ldr	r3, [r7, #4]
 8002b08:	4a26      	ldr	r2, [pc, #152]	@ (8002ba4 <TIM_Base_SetConfig+0xe8>)
 8002b0a:	4293      	cmp	r3, r2
 8002b0c:	d003      	beq.n	8002b16 <TIM_Base_SetConfig+0x5a>
 8002b0e:	687b      	ldr	r3, [r7, #4]
 8002b10:	4a25      	ldr	r2, [pc, #148]	@ (8002ba8 <TIM_Base_SetConfig+0xec>)
 8002b12:	4293      	cmp	r3, r2
 8002b14:	d108      	bne.n	8002b28 <TIM_Base_SetConfig+0x6c>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
 8002b16:	68fb      	ldr	r3, [r7, #12]
 8002b18:	4a24      	ldr	r2, [pc, #144]	@ (8002bac <TIM_Base_SetConfig+0xf0>)
 8002b1a:	4013      	ands	r3, r2
 8002b1c:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8002b1e:	683b      	ldr	r3, [r7, #0]
 8002b20:	68db      	ldr	r3, [r3, #12]
 8002b22:	68fa      	ldr	r2, [r7, #12]
 8002b24:	4313      	orrs	r3, r2
 8002b26:	60fb      	str	r3, [r7, #12]
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8002b28:	68fb      	ldr	r3, [r7, #12]
 8002b2a:	2280      	movs	r2, #128	@ 0x80
 8002b2c:	4393      	bics	r3, r2
 8002b2e:	001a      	movs	r2, r3
 8002b30:	683b      	ldr	r3, [r7, #0]
 8002b32:	695b      	ldr	r3, [r3, #20]
 8002b34:	4313      	orrs	r3, r2
 8002b36:	60fb      	str	r3, [r7, #12]

  TIMx->CR1 = tmpcr1;
 8002b38:	687b      	ldr	r3, [r7, #4]
 8002b3a:	68fa      	ldr	r2, [r7, #12]
 8002b3c:	601a      	str	r2, [r3, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8002b3e:	683b      	ldr	r3, [r7, #0]
 8002b40:	689a      	ldr	r2, [r3, #8]
 8002b42:	687b      	ldr	r3, [r7, #4]
 8002b44:	62da      	str	r2, [r3, #44]	@ 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 8002b46:	683b      	ldr	r3, [r7, #0]
 8002b48:	681a      	ldr	r2, [r3, #0]
 8002b4a:	687b      	ldr	r3, [r7, #4]
 8002b4c:	629a      	str	r2, [r3, #40]	@ 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 8002b4e:	687b      	ldr	r3, [r7, #4]
 8002b50:	4a11      	ldr	r2, [pc, #68]	@ (8002b98 <TIM_Base_SetConfig+0xdc>)
 8002b52:	4293      	cmp	r3, r2
 8002b54:	d007      	beq.n	8002b66 <TIM_Base_SetConfig+0xaa>
 8002b56:	687b      	ldr	r3, [r7, #4]
 8002b58:	4a12      	ldr	r2, [pc, #72]	@ (8002ba4 <TIM_Base_SetConfig+0xe8>)
 8002b5a:	4293      	cmp	r3, r2
 8002b5c:	d003      	beq.n	8002b66 <TIM_Base_SetConfig+0xaa>
 8002b5e:	687b      	ldr	r3, [r7, #4]
 8002b60:	4a11      	ldr	r2, [pc, #68]	@ (8002ba8 <TIM_Base_SetConfig+0xec>)
 8002b62:	4293      	cmp	r3, r2
 8002b64:	d103      	bne.n	8002b6e <TIM_Base_SetConfig+0xb2>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 8002b66:	683b      	ldr	r3, [r7, #0]
 8002b68:	691a      	ldr	r2, [r3, #16]
 8002b6a:	687b      	ldr	r3, [r7, #4]
 8002b6c:	631a      	str	r2, [r3, #48]	@ 0x30
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 8002b6e:	687b      	ldr	r3, [r7, #4]
 8002b70:	2201      	movs	r2, #1
 8002b72:	615a      	str	r2, [r3, #20]

  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
 8002b74:	687b      	ldr	r3, [r7, #4]
 8002b76:	691b      	ldr	r3, [r3, #16]
 8002b78:	2201      	movs	r2, #1
 8002b7a:	4013      	ands	r3, r2
 8002b7c:	2b01      	cmp	r3, #1
 8002b7e:	d106      	bne.n	8002b8e <TIM_Base_SetConfig+0xd2>
  {
    /* Clear the update flag */
    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
 8002b80:	687b      	ldr	r3, [r7, #4]
 8002b82:	691b      	ldr	r3, [r3, #16]
 8002b84:	2201      	movs	r2, #1
 8002b86:	4393      	bics	r3, r2
 8002b88:	001a      	movs	r2, r3
 8002b8a:	687b      	ldr	r3, [r7, #4]
 8002b8c:	611a      	str	r2, [r3, #16]
  }
}
 8002b8e:	46c0      	nop			@ (mov r8, r8)
 8002b90:	46bd      	mov	sp, r7
 8002b92:	b004      	add	sp, #16
 8002b94:	bd80      	pop	{r7, pc}
 8002b96:	46c0      	nop			@ (mov r8, r8)
 8002b98:	40012c00 	.word	0x40012c00
 8002b9c:	40000400 	.word	0x40000400
 8002ba0:	40002000 	.word	0x40002000
 8002ba4:	40014400 	.word	0x40014400
 8002ba8:	40014800 	.word	0x40014800
 8002bac:	fffffcff 	.word	0xfffffcff

08002bb0 <TIM_TI1_SetConfig>:
  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
  *        protected against un-initialized filter and polarity values.
  */
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
                       uint32_t TIM_ICFilter)
{
 8002bb0:	b580      	push	{r7, lr}
 8002bb2:	b086      	sub	sp, #24
 8002bb4:	af00      	add	r7, sp, #0
 8002bb6:	60f8      	str	r0, [r7, #12]
 8002bb8:	60b9      	str	r1, [r7, #8]
 8002bba:	607a      	str	r2, [r7, #4]
 8002bbc:	603b      	str	r3, [r7, #0]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  tmpccer = TIMx->CCER;
 8002bbe:	68fb      	ldr	r3, [r7, #12]
 8002bc0:	6a1b      	ldr	r3, [r3, #32]
 8002bc2:	613b      	str	r3, [r7, #16]
  TIMx->CCER &= ~TIM_CCER_CC1E;
 8002bc4:	68fb      	ldr	r3, [r7, #12]
 8002bc6:	6a1b      	ldr	r3, [r3, #32]
 8002bc8:	2201      	movs	r2, #1
 8002bca:	4393      	bics	r3, r2
 8002bcc:	001a      	movs	r2, r3
 8002bce:	68fb      	ldr	r3, [r7, #12]
 8002bd0:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 8002bd2:	68fb      	ldr	r3, [r7, #12]
 8002bd4:	699b      	ldr	r3, [r3, #24]
 8002bd6:	617b      	str	r3, [r7, #20]

  /* Select the Input */
  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
 8002bd8:	68fb      	ldr	r3, [r7, #12]
 8002bda:	4a1c      	ldr	r2, [pc, #112]	@ (8002c4c <TIM_TI1_SetConfig+0x9c>)
 8002bdc:	4293      	cmp	r3, r2
 8002bde:	d003      	beq.n	8002be8 <TIM_TI1_SetConfig+0x38>
 8002be0:	68fb      	ldr	r3, [r7, #12]
 8002be2:	4a1b      	ldr	r2, [pc, #108]	@ (8002c50 <TIM_TI1_SetConfig+0xa0>)
 8002be4:	4293      	cmp	r3, r2
 8002be6:	d101      	bne.n	8002bec <TIM_TI1_SetConfig+0x3c>
 8002be8:	2301      	movs	r3, #1
 8002bea:	e000      	b.n	8002bee <TIM_TI1_SetConfig+0x3e>
 8002bec:	2300      	movs	r3, #0
 8002bee:	2b00      	cmp	r3, #0
 8002bf0:	d008      	beq.n	8002c04 <TIM_TI1_SetConfig+0x54>
  {
    tmpccmr1 &= ~TIM_CCMR1_CC1S;
 8002bf2:	697b      	ldr	r3, [r7, #20]
 8002bf4:	2203      	movs	r2, #3
 8002bf6:	4393      	bics	r3, r2
 8002bf8:	617b      	str	r3, [r7, #20]
    tmpccmr1 |= TIM_ICSelection;
 8002bfa:	697a      	ldr	r2, [r7, #20]
 8002bfc:	687b      	ldr	r3, [r7, #4]
 8002bfe:	4313      	orrs	r3, r2
 8002c00:	617b      	str	r3, [r7, #20]
 8002c02:	e003      	b.n	8002c0c <TIM_TI1_SetConfig+0x5c>
  }
  else
  {
    tmpccmr1 |= TIM_CCMR1_CC1S_0;
 8002c04:	697b      	ldr	r3, [r7, #20]
 8002c06:	2201      	movs	r2, #1
 8002c08:	4313      	orrs	r3, r2
 8002c0a:	617b      	str	r3, [r7, #20]
  }

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
 8002c0c:	697b      	ldr	r3, [r7, #20]
 8002c0e:	22f0      	movs	r2, #240	@ 0xf0
 8002c10:	4393      	bics	r3, r2
 8002c12:	617b      	str	r3, [r7, #20]
  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
 8002c14:	683b      	ldr	r3, [r7, #0]
 8002c16:	011b      	lsls	r3, r3, #4
 8002c18:	22ff      	movs	r2, #255	@ 0xff
 8002c1a:	4013      	ands	r3, r2
 8002c1c:	697a      	ldr	r2, [r7, #20]
 8002c1e:	4313      	orrs	r3, r2
 8002c20:	617b      	str	r3, [r7, #20]

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
 8002c22:	693b      	ldr	r3, [r7, #16]
 8002c24:	220a      	movs	r2, #10
 8002c26:	4393      	bics	r3, r2
 8002c28:	613b      	str	r3, [r7, #16]
  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
 8002c2a:	68bb      	ldr	r3, [r7, #8]
 8002c2c:	220a      	movs	r2, #10
 8002c2e:	4013      	ands	r3, r2
 8002c30:	693a      	ldr	r2, [r7, #16]
 8002c32:	4313      	orrs	r3, r2
 8002c34:	613b      	str	r3, [r7, #16]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
 8002c36:	68fb      	ldr	r3, [r7, #12]
 8002c38:	697a      	ldr	r2, [r7, #20]
 8002c3a:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 8002c3c:	68fb      	ldr	r3, [r7, #12]
 8002c3e:	693a      	ldr	r2, [r7, #16]
 8002c40:	621a      	str	r2, [r3, #32]
}
 8002c42:	46c0      	nop			@ (mov r8, r8)
 8002c44:	46bd      	mov	sp, r7
 8002c46:	b006      	add	sp, #24
 8002c48:	bd80      	pop	{r7, pc}
 8002c4a:	46c0      	nop			@ (mov r8, r8)
 8002c4c:	40012c00 	.word	0x40012c00
 8002c50:	40000400 	.word	0x40000400

08002c54 <TIM_TI1_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 8002c54:	b580      	push	{r7, lr}
 8002c56:	b086      	sub	sp, #24
 8002c58:	af00      	add	r7, sp, #0
 8002c5a:	60f8      	str	r0, [r7, #12]
 8002c5c:	60b9      	str	r1, [r7, #8]
 8002c5e:	607a      	str	r2, [r7, #4]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  tmpccer = TIMx->CCER;
 8002c60:	68fb      	ldr	r3, [r7, #12]
 8002c62:	6a1b      	ldr	r3, [r3, #32]
 8002c64:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC1E;
 8002c66:	68fb      	ldr	r3, [r7, #12]
 8002c68:	6a1b      	ldr	r3, [r3, #32]
 8002c6a:	2201      	movs	r2, #1
 8002c6c:	4393      	bics	r3, r2
 8002c6e:	001a      	movs	r2, r3
 8002c70:	68fb      	ldr	r3, [r7, #12]
 8002c72:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 8002c74:	68fb      	ldr	r3, [r7, #12]
 8002c76:	699b      	ldr	r3, [r3, #24]
 8002c78:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
 8002c7a:	693b      	ldr	r3, [r7, #16]
 8002c7c:	22f0      	movs	r2, #240	@ 0xf0
 8002c7e:	4393      	bics	r3, r2
 8002c80:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICFilter << 4U);
 8002c82:	687b      	ldr	r3, [r7, #4]
 8002c84:	011b      	lsls	r3, r3, #4
 8002c86:	693a      	ldr	r2, [r7, #16]
 8002c88:	4313      	orrs	r3, r2
 8002c8a:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
 8002c8c:	697b      	ldr	r3, [r7, #20]
 8002c8e:	220a      	movs	r2, #10
 8002c90:	4393      	bics	r3, r2
 8002c92:	617b      	str	r3, [r7, #20]
  tmpccer |= TIM_ICPolarity;
 8002c94:	697a      	ldr	r2, [r7, #20]
 8002c96:	68bb      	ldr	r3, [r7, #8]
 8002c98:	4313      	orrs	r3, r2
 8002c9a:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
 8002c9c:	68fb      	ldr	r3, [r7, #12]
 8002c9e:	693a      	ldr	r2, [r7, #16]
 8002ca0:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 8002ca2:	68fb      	ldr	r3, [r7, #12]
 8002ca4:	697a      	ldr	r2, [r7, #20]
 8002ca6:	621a      	str	r2, [r3, #32]
}
 8002ca8:	46c0      	nop			@ (mov r8, r8)
 8002caa:	46bd      	mov	sp, r7
 8002cac:	b006      	add	sp, #24
 8002cae:	bd80      	pop	{r7, pc}

08002cb0 <TIM_TI2_SetConfig>:
  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
  *        protected against un-initialized filter and polarity values.
  */
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
                              uint32_t TIM_ICFilter)
{
 8002cb0:	b580      	push	{r7, lr}
 8002cb2:	b086      	sub	sp, #24
 8002cb4:	af00      	add	r7, sp, #0
 8002cb6:	60f8      	str	r0, [r7, #12]
 8002cb8:	60b9      	str	r1, [r7, #8]
 8002cba:	607a      	str	r2, [r7, #4]
 8002cbc:	603b      	str	r3, [r7, #0]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  tmpccer = TIMx->CCER;
 8002cbe:	68fb      	ldr	r3, [r7, #12]
 8002cc0:	6a1b      	ldr	r3, [r3, #32]
 8002cc2:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC2E;
 8002cc4:	68fb      	ldr	r3, [r7, #12]
 8002cc6:	6a1b      	ldr	r3, [r3, #32]
 8002cc8:	2210      	movs	r2, #16
 8002cca:	4393      	bics	r3, r2
 8002ccc:	001a      	movs	r2, r3
 8002cce:	68fb      	ldr	r3, [r7, #12]
 8002cd0:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 8002cd2:	68fb      	ldr	r3, [r7, #12]
 8002cd4:	699b      	ldr	r3, [r3, #24]
 8002cd6:	613b      	str	r3, [r7, #16]

  /* Select the Input */
  tmpccmr1 &= ~TIM_CCMR1_CC2S;
 8002cd8:	693b      	ldr	r3, [r7, #16]
 8002cda:	4a14      	ldr	r2, [pc, #80]	@ (8002d2c <TIM_TI2_SetConfig+0x7c>)
 8002cdc:	4013      	ands	r3, r2
 8002cde:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICSelection << 8U);
 8002ce0:	687b      	ldr	r3, [r7, #4]
 8002ce2:	021b      	lsls	r3, r3, #8
 8002ce4:	693a      	ldr	r2, [r7, #16]
 8002ce6:	4313      	orrs	r3, r2
 8002ce8:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
 8002cea:	693b      	ldr	r3, [r7, #16]
 8002cec:	4a10      	ldr	r2, [pc, #64]	@ (8002d30 <TIM_TI2_SetConfig+0x80>)
 8002cee:	4013      	ands	r3, r2
 8002cf0:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
 8002cf2:	683b      	ldr	r3, [r7, #0]
 8002cf4:	031b      	lsls	r3, r3, #12
 8002cf6:	041b      	lsls	r3, r3, #16
 8002cf8:	0c1b      	lsrs	r3, r3, #16
 8002cfa:	693a      	ldr	r2, [r7, #16]
 8002cfc:	4313      	orrs	r3, r2
 8002cfe:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
 8002d00:	697b      	ldr	r3, [r7, #20]
 8002d02:	22a0      	movs	r2, #160	@ 0xa0
 8002d04:	4393      	bics	r3, r2
 8002d06:	617b      	str	r3, [r7, #20]
  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
 8002d08:	68bb      	ldr	r3, [r7, #8]
 8002d0a:	011b      	lsls	r3, r3, #4
 8002d0c:	22a0      	movs	r2, #160	@ 0xa0
 8002d0e:	4013      	ands	r3, r2
 8002d10:	697a      	ldr	r2, [r7, #20]
 8002d12:	4313      	orrs	r3, r2
 8002d14:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1 ;
 8002d16:	68fb      	ldr	r3, [r7, #12]
 8002d18:	693a      	ldr	r2, [r7, #16]
 8002d1a:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 8002d1c:	68fb      	ldr	r3, [r7, #12]
 8002d1e:	697a      	ldr	r2, [r7, #20]
 8002d20:	621a      	str	r2, [r3, #32]
}
 8002d22:	46c0      	nop			@ (mov r8, r8)
 8002d24:	46bd      	mov	sp, r7
 8002d26:	b006      	add	sp, #24
 8002d28:	bd80      	pop	{r7, pc}
 8002d2a:	46c0      	nop			@ (mov r8, r8)
 8002d2c:	fffffcff 	.word	0xfffffcff
 8002d30:	ffff0fff 	.word	0xffff0fff

08002d34 <TIM_TI2_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 8002d34:	b580      	push	{r7, lr}
 8002d36:	b086      	sub	sp, #24
 8002d38:	af00      	add	r7, sp, #0
 8002d3a:	60f8      	str	r0, [r7, #12]
 8002d3c:	60b9      	str	r1, [r7, #8]
 8002d3e:	607a      	str	r2, [r7, #4]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  tmpccer = TIMx->CCER;
 8002d40:	68fb      	ldr	r3, [r7, #12]
 8002d42:	6a1b      	ldr	r3, [r3, #32]
 8002d44:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC2E;
 8002d46:	68fb      	ldr	r3, [r7, #12]
 8002d48:	6a1b      	ldr	r3, [r3, #32]
 8002d4a:	2210      	movs	r2, #16
 8002d4c:	4393      	bics	r3, r2
 8002d4e:	001a      	movs	r2, r3
 8002d50:	68fb      	ldr	r3, [r7, #12]
 8002d52:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 8002d54:	68fb      	ldr	r3, [r7, #12]
 8002d56:	699b      	ldr	r3, [r3, #24]
 8002d58:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
 8002d5a:	693b      	ldr	r3, [r7, #16]
 8002d5c:	4a0d      	ldr	r2, [pc, #52]	@ (8002d94 <TIM_TI2_ConfigInputStage+0x60>)
 8002d5e:	4013      	ands	r3, r2
 8002d60:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICFilter << 12U);
 8002d62:	687b      	ldr	r3, [r7, #4]
 8002d64:	031b      	lsls	r3, r3, #12
 8002d66:	693a      	ldr	r2, [r7, #16]
 8002d68:	4313      	orrs	r3, r2
 8002d6a:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
 8002d6c:	697b      	ldr	r3, [r7, #20]
 8002d6e:	22a0      	movs	r2, #160	@ 0xa0
 8002d70:	4393      	bics	r3, r2
 8002d72:	617b      	str	r3, [r7, #20]
  tmpccer |= (TIM_ICPolarity << 4U);
 8002d74:	68bb      	ldr	r3, [r7, #8]
 8002d76:	011b      	lsls	r3, r3, #4
 8002d78:	697a      	ldr	r2, [r7, #20]
 8002d7a:	4313      	orrs	r3, r2
 8002d7c:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1 ;
 8002d7e:	68fb      	ldr	r3, [r7, #12]
 8002d80:	693a      	ldr	r2, [r7, #16]
 8002d82:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 8002d84:	68fb      	ldr	r3, [r7, #12]
 8002d86:	697a      	ldr	r2, [r7, #20]
 8002d88:	621a      	str	r2, [r3, #32]
}
 8002d8a:	46c0      	nop			@ (mov r8, r8)
 8002d8c:	46bd      	mov	sp, r7
 8002d8e:	b006      	add	sp, #24
 8002d90:	bd80      	pop	{r7, pc}
 8002d92:	46c0      	nop			@ (mov r8, r8)
 8002d94:	ffff0fff 	.word	0xffff0fff

08002d98 <TIM_TI3_SetConfig>:
  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  *        protected against un-initialized filter and polarity values.
  */
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
                              uint32_t TIM_ICFilter)
{
 8002d98:	b580      	push	{r7, lr}
 8002d9a:	b086      	sub	sp, #24
 8002d9c:	af00      	add	r7, sp, #0
 8002d9e:	60f8      	str	r0, [r7, #12]
 8002da0:	60b9      	str	r1, [r7, #8]
 8002da2:	607a      	str	r2, [r7, #4]
 8002da4:	603b      	str	r3, [r7, #0]
  uint32_t tmpccmr2;
  uint32_t tmpccer;

  /* Disable the Channel 3: Reset the CC3E Bit */
  tmpccer = TIMx->CCER;
 8002da6:	68fb      	ldr	r3, [r7, #12]
 8002da8:	6a1b      	ldr	r3, [r3, #32]
 8002daa:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC3E;
 8002dac:	68fb      	ldr	r3, [r7, #12]
 8002dae:	6a1b      	ldr	r3, [r3, #32]
 8002db0:	4a17      	ldr	r2, [pc, #92]	@ (8002e10 <TIM_TI3_SetConfig+0x78>)
 8002db2:	401a      	ands	r2, r3
 8002db4:	68fb      	ldr	r3, [r7, #12]
 8002db6:	621a      	str	r2, [r3, #32]
  tmpccmr2 = TIMx->CCMR2;
 8002db8:	68fb      	ldr	r3, [r7, #12]
 8002dba:	69db      	ldr	r3, [r3, #28]
 8002dbc:	613b      	str	r3, [r7, #16]

  /* Select the Input */
  tmpccmr2 &= ~TIM_CCMR2_CC3S;
 8002dbe:	693b      	ldr	r3, [r7, #16]
 8002dc0:	2203      	movs	r2, #3
 8002dc2:	4393      	bics	r3, r2
 8002dc4:	613b      	str	r3, [r7, #16]
  tmpccmr2 |= TIM_ICSelection;
 8002dc6:	693a      	ldr	r2, [r7, #16]
 8002dc8:	687b      	ldr	r3, [r7, #4]
 8002dca:	4313      	orrs	r3, r2
 8002dcc:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr2 &= ~TIM_CCMR2_IC3F;
 8002dce:	693b      	ldr	r3, [r7, #16]
 8002dd0:	22f0      	movs	r2, #240	@ 0xf0
 8002dd2:	4393      	bics	r3, r2
 8002dd4:	613b      	str	r3, [r7, #16]
  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
 8002dd6:	683b      	ldr	r3, [r7, #0]
 8002dd8:	011b      	lsls	r3, r3, #4
 8002dda:	22ff      	movs	r2, #255	@ 0xff
 8002ddc:	4013      	ands	r3, r2
 8002dde:	693a      	ldr	r2, [r7, #16]
 8002de0:	4313      	orrs	r3, r2
 8002de2:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC3E Bit */
  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
 8002de4:	697b      	ldr	r3, [r7, #20]
 8002de6:	4a0b      	ldr	r2, [pc, #44]	@ (8002e14 <TIM_TI3_SetConfig+0x7c>)
 8002de8:	4013      	ands	r3, r2
 8002dea:	617b      	str	r3, [r7, #20]
  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
 8002dec:	68bb      	ldr	r3, [r7, #8]
 8002dee:	021a      	lsls	r2, r3, #8
 8002df0:	23a0      	movs	r3, #160	@ 0xa0
 8002df2:	011b      	lsls	r3, r3, #4
 8002df4:	4013      	ands	r3, r2
 8002df6:	697a      	ldr	r2, [r7, #20]
 8002df8:	4313      	orrs	r3, r2
 8002dfa:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR2 and CCER registers */
  TIMx->CCMR2 = tmpccmr2;
 8002dfc:	68fb      	ldr	r3, [r7, #12]
 8002dfe:	693a      	ldr	r2, [r7, #16]
 8002e00:	61da      	str	r2, [r3, #28]
  TIMx->CCER = tmpccer;
 8002e02:	68fb      	ldr	r3, [r7, #12]
 8002e04:	697a      	ldr	r2, [r7, #20]
 8002e06:	621a      	str	r2, [r3, #32]
}
 8002e08:	46c0      	nop			@ (mov r8, r8)
 8002e0a:	46bd      	mov	sp, r7
 8002e0c:	b006      	add	sp, #24
 8002e0e:	bd80      	pop	{r7, pc}
 8002e10:	fffffeff 	.word	0xfffffeff
 8002e14:	fffff5ff 	.word	0xfffff5ff

08002e18 <TIM_TI4_SetConfig>:
  *        protected against un-initialized filter and polarity values.
  * @retval None
  */
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
                              uint32_t TIM_ICFilter)
{
 8002e18:	b580      	push	{r7, lr}
 8002e1a:	b086      	sub	sp, #24
 8002e1c:	af00      	add	r7, sp, #0
 8002e1e:	60f8      	str	r0, [r7, #12]
 8002e20:	60b9      	str	r1, [r7, #8]
 8002e22:	607a      	str	r2, [r7, #4]
 8002e24:	603b      	str	r3, [r7, #0]
  uint32_t tmpccmr2;
  uint32_t tmpccer;

  /* Disable the Channel 4: Reset the CC4E Bit */
  tmpccer = TIMx->CCER;
 8002e26:	68fb      	ldr	r3, [r7, #12]
 8002e28:	6a1b      	ldr	r3, [r3, #32]
 8002e2a:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC4E;
 8002e2c:	68fb      	ldr	r3, [r7, #12]
 8002e2e:	6a1b      	ldr	r3, [r3, #32]
 8002e30:	4a18      	ldr	r2, [pc, #96]	@ (8002e94 <TIM_TI4_SetConfig+0x7c>)
 8002e32:	401a      	ands	r2, r3
 8002e34:	68fb      	ldr	r3, [r7, #12]
 8002e36:	621a      	str	r2, [r3, #32]
  tmpccmr2 = TIMx->CCMR2;
 8002e38:	68fb      	ldr	r3, [r7, #12]
 8002e3a:	69db      	ldr	r3, [r3, #28]
 8002e3c:	613b      	str	r3, [r7, #16]

  /* Select the Input */
  tmpccmr2 &= ~TIM_CCMR2_CC4S;
 8002e3e:	693b      	ldr	r3, [r7, #16]
 8002e40:	4a15      	ldr	r2, [pc, #84]	@ (8002e98 <TIM_TI4_SetConfig+0x80>)
 8002e42:	4013      	ands	r3, r2
 8002e44:	613b      	str	r3, [r7, #16]
  tmpccmr2 |= (TIM_ICSelection << 8U);
 8002e46:	687b      	ldr	r3, [r7, #4]
 8002e48:	021b      	lsls	r3, r3, #8
 8002e4a:	693a      	ldr	r2, [r7, #16]
 8002e4c:	4313      	orrs	r3, r2
 8002e4e:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr2 &= ~TIM_CCMR2_IC4F;
 8002e50:	693b      	ldr	r3, [r7, #16]
 8002e52:	4a12      	ldr	r2, [pc, #72]	@ (8002e9c <TIM_TI4_SetConfig+0x84>)
 8002e54:	4013      	ands	r3, r2
 8002e56:	613b      	str	r3, [r7, #16]
  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
 8002e58:	683b      	ldr	r3, [r7, #0]
 8002e5a:	031b      	lsls	r3, r3, #12
 8002e5c:	041b      	lsls	r3, r3, #16
 8002e5e:	0c1b      	lsrs	r3, r3, #16
 8002e60:	693a      	ldr	r2, [r7, #16]
 8002e62:	4313      	orrs	r3, r2
 8002e64:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC4E Bit */
  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
 8002e66:	697b      	ldr	r3, [r7, #20]
 8002e68:	4a0d      	ldr	r2, [pc, #52]	@ (8002ea0 <TIM_TI4_SetConfig+0x88>)
 8002e6a:	4013      	ands	r3, r2
 8002e6c:	617b      	str	r3, [r7, #20]
  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
 8002e6e:	68bb      	ldr	r3, [r7, #8]
 8002e70:	031a      	lsls	r2, r3, #12
 8002e72:	23a0      	movs	r3, #160	@ 0xa0
 8002e74:	021b      	lsls	r3, r3, #8
 8002e76:	4013      	ands	r3, r2
 8002e78:	697a      	ldr	r2, [r7, #20]
 8002e7a:	4313      	orrs	r3, r2
 8002e7c:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR2 and CCER registers */
  TIMx->CCMR2 = tmpccmr2;
 8002e7e:	68fb      	ldr	r3, [r7, #12]
 8002e80:	693a      	ldr	r2, [r7, #16]
 8002e82:	61da      	str	r2, [r3, #28]
  TIMx->CCER = tmpccer ;
 8002e84:	68fb      	ldr	r3, [r7, #12]
 8002e86:	697a      	ldr	r2, [r7, #20]
 8002e88:	621a      	str	r2, [r3, #32]
}
 8002e8a:	46c0      	nop			@ (mov r8, r8)
 8002e8c:	46bd      	mov	sp, r7
 8002e8e:	b006      	add	sp, #24
 8002e90:	bd80      	pop	{r7, pc}
 8002e92:	46c0      	nop			@ (mov r8, r8)
 8002e94:	ffffefff 	.word	0xffffefff
 8002e98:	fffffcff 	.word	0xfffffcff
 8002e9c:	ffff0fff 	.word	0xffff0fff
 8002ea0:	ffff5fff 	.word	0xffff5fff

08002ea4 <TIM_ITRx_SetConfig>:
  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
  *            @arg TIM_TS_ETRF: External Trigger input
  * @retval None
  */
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
 8002ea4:	b580      	push	{r7, lr}
 8002ea6:	b084      	sub	sp, #16
 8002ea8:	af00      	add	r7, sp, #0
 8002eaa:	6078      	str	r0, [r7, #4]
 8002eac:	6039      	str	r1, [r7, #0]
  uint32_t tmpsmcr;

  /* Get the TIMx SMCR register value */
  tmpsmcr = TIMx->SMCR;
 8002eae:	687b      	ldr	r3, [r7, #4]
 8002eb0:	689b      	ldr	r3, [r3, #8]
 8002eb2:	60fb      	str	r3, [r7, #12]
  /* Reset the TS Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
 8002eb4:	68fb      	ldr	r3, [r7, #12]
 8002eb6:	4a08      	ldr	r2, [pc, #32]	@ (8002ed8 <TIM_ITRx_SetConfig+0x34>)
 8002eb8:	4013      	ands	r3, r2
 8002eba:	60fb      	str	r3, [r7, #12]
  /* Set the Input Trigger source and the slave mode*/
  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
 8002ebc:	683a      	ldr	r2, [r7, #0]
 8002ebe:	68fb      	ldr	r3, [r7, #12]
 8002ec0:	4313      	orrs	r3, r2
 8002ec2:	2207      	movs	r2, #7
 8002ec4:	4313      	orrs	r3, r2
 8002ec6:	60fb      	str	r3, [r7, #12]
  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 8002ec8:	687b      	ldr	r3, [r7, #4]
 8002eca:	68fa      	ldr	r2, [r7, #12]
 8002ecc:	609a      	str	r2, [r3, #8]
}
 8002ece:	46c0      	nop			@ (mov r8, r8)
 8002ed0:	46bd      	mov	sp, r7
 8002ed2:	b004      	add	sp, #16
 8002ed4:	bd80      	pop	{r7, pc}
 8002ed6:	46c0      	nop			@ (mov r8, r8)
 8002ed8:	ffcfff8f 	.word	0xffcfff8f

08002edc <TIM_ETR_SetConfig>:
  *          This parameter must be a value between 0x00 and 0x0F
  * @retval None
  */
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
 8002edc:	b580      	push	{r7, lr}
 8002ede:	b086      	sub	sp, #24
 8002ee0:	af00      	add	r7, sp, #0
 8002ee2:	60f8      	str	r0, [r7, #12]
 8002ee4:	60b9      	str	r1, [r7, #8]
 8002ee6:	607a      	str	r2, [r7, #4]
 8002ee8:	603b      	str	r3, [r7, #0]
  uint32_t tmpsmcr;

  tmpsmcr = TIMx->SMCR;
 8002eea:	68fb      	ldr	r3, [r7, #12]
 8002eec:	689b      	ldr	r3, [r3, #8]
 8002eee:	617b      	str	r3, [r7, #20]

  /* Reset the ETR Bits */
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 8002ef0:	697b      	ldr	r3, [r7, #20]
 8002ef2:	4a09      	ldr	r2, [pc, #36]	@ (8002f18 <TIM_ETR_SetConfig+0x3c>)
 8002ef4:	4013      	ands	r3, r2
 8002ef6:	617b      	str	r3, [r7, #20]

  /* Set the Prescaler, the Filter value and the Polarity */
  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
 8002ef8:	683b      	ldr	r3, [r7, #0]
 8002efa:	021a      	lsls	r2, r3, #8
 8002efc:	687b      	ldr	r3, [r7, #4]
 8002efe:	431a      	orrs	r2, r3
 8002f00:	68bb      	ldr	r3, [r7, #8]
 8002f02:	4313      	orrs	r3, r2
 8002f04:	697a      	ldr	r2, [r7, #20]
 8002f06:	4313      	orrs	r3, r2
 8002f08:	617b      	str	r3, [r7, #20]

  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 8002f0a:	68fb      	ldr	r3, [r7, #12]
 8002f0c:	697a      	ldr	r2, [r7, #20]
 8002f0e:	609a      	str	r2, [r3, #8]
}
 8002f10:	46c0      	nop			@ (mov r8, r8)
 8002f12:	46bd      	mov	sp, r7
 8002f14:	b006      	add	sp, #24
 8002f16:	bd80      	pop	{r7, pc}
 8002f18:	ffff00ff 	.word	0xffff00ff

08002f1c <TIM_CCxChannelCmd>:
  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
  * @retval None
  */
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
 8002f1c:	b580      	push	{r7, lr}
 8002f1e:	b086      	sub	sp, #24
 8002f20:	af00      	add	r7, sp, #0
 8002f22:	60f8      	str	r0, [r7, #12]
 8002f24:	60b9      	str	r1, [r7, #8]
 8002f26:	607a      	str	r2, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  assert_param(IS_TIM_CHANNELS(Channel));

  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
 8002f28:	68bb      	ldr	r3, [r7, #8]
 8002f2a:	221f      	movs	r2, #31
 8002f2c:	4013      	ands	r3, r2
 8002f2e:	2201      	movs	r2, #1
 8002f30:	409a      	lsls	r2, r3
 8002f32:	0013      	movs	r3, r2
 8002f34:	617b      	str	r3, [r7, #20]

  /* Reset the CCxE Bit */
  TIMx->CCER &= ~tmp;
 8002f36:	68fb      	ldr	r3, [r7, #12]
 8002f38:	6a1b      	ldr	r3, [r3, #32]
 8002f3a:	697a      	ldr	r2, [r7, #20]
 8002f3c:	43d2      	mvns	r2, r2
 8002f3e:	401a      	ands	r2, r3
 8002f40:	68fb      	ldr	r3, [r7, #12]
 8002f42:	621a      	str	r2, [r3, #32]

  /* Set or reset the CCxE Bit */
  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
 8002f44:	68fb      	ldr	r3, [r7, #12]
 8002f46:	6a1a      	ldr	r2, [r3, #32]
 8002f48:	68bb      	ldr	r3, [r7, #8]
 8002f4a:	211f      	movs	r1, #31
 8002f4c:	400b      	ands	r3, r1
 8002f4e:	6879      	ldr	r1, [r7, #4]
 8002f50:	4099      	lsls	r1, r3
 8002f52:	000b      	movs	r3, r1
 8002f54:	431a      	orrs	r2, r3
 8002f56:	68fb      	ldr	r3, [r7, #12]
 8002f58:	621a      	str	r2, [r3, #32]
}
 8002f5a:	46c0      	nop			@ (mov r8, r8)
 8002f5c:	46bd      	mov	sp, r7
 8002f5e:	b006      	add	sp, #24
 8002f60:	bd80      	pop	{r7, pc}
	...

08002f64 <HAL_TIMEx_MasterConfigSynchronization>:
  *         mode.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
{
 8002f64:	b580      	push	{r7, lr}
 8002f66:	b084      	sub	sp, #16
 8002f68:	af00      	add	r7, sp, #0
 8002f6a:	6078      	str	r0, [r7, #4]
 8002f6c:	6039      	str	r1, [r7, #0]
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);
 8002f6e:	687b      	ldr	r3, [r7, #4]
 8002f70:	223c      	movs	r2, #60	@ 0x3c
 8002f72:	5c9b      	ldrb	r3, [r3, r2]
 8002f74:	2b01      	cmp	r3, #1
 8002f76:	d101      	bne.n	8002f7c <HAL_TIMEx_MasterConfigSynchronization+0x18>
 8002f78:	2302      	movs	r3, #2
 8002f7a:	e04a      	b.n	8003012 <HAL_TIMEx_MasterConfigSynchronization+0xae>
 8002f7c:	687b      	ldr	r3, [r7, #4]
 8002f7e:	223c      	movs	r2, #60	@ 0x3c
 8002f80:	2101      	movs	r1, #1
 8002f82:	5499      	strb	r1, [r3, r2]

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;
 8002f84:	687b      	ldr	r3, [r7, #4]
 8002f86:	223d      	movs	r2, #61	@ 0x3d
 8002f88:	2102      	movs	r1, #2
 8002f8a:	5499      	strb	r1, [r3, r2]

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;
 8002f8c:	687b      	ldr	r3, [r7, #4]
 8002f8e:	681b      	ldr	r3, [r3, #0]
 8002f90:	685b      	ldr	r3, [r3, #4]
 8002f92:	60fb      	str	r3, [r7, #12]

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;
 8002f94:	687b      	ldr	r3, [r7, #4]
 8002f96:	681b      	ldr	r3, [r3, #0]
 8002f98:	689b      	ldr	r3, [r3, #8]
 8002f9a:	60bb      	str	r3, [r7, #8]

  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
 8002f9c:	687b      	ldr	r3, [r7, #4]
 8002f9e:	681b      	ldr	r3, [r3, #0]
 8002fa0:	4a1e      	ldr	r2, [pc, #120]	@ (800301c <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
 8002fa2:	4293      	cmp	r3, r2
 8002fa4:	d108      	bne.n	8002fb8 <HAL_TIMEx_MasterConfigSynchronization+0x54>
  {
    /* Check the parameters */
    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));

    /* Clear the MMS2 bits */
    tmpcr2 &= ~TIM_CR2_MMS2;
 8002fa6:	68fb      	ldr	r3, [r7, #12]
 8002fa8:	4a1d      	ldr	r2, [pc, #116]	@ (8003020 <HAL_TIMEx_MasterConfigSynchronization+0xbc>)
 8002faa:	4013      	ands	r3, r2
 8002fac:	60fb      	str	r3, [r7, #12]
    /* Select the TRGO2 source*/
    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
 8002fae:	683b      	ldr	r3, [r7, #0]
 8002fb0:	685b      	ldr	r3, [r3, #4]
 8002fb2:	68fa      	ldr	r2, [r7, #12]
 8002fb4:	4313      	orrs	r3, r2
 8002fb6:	60fb      	str	r3, [r7, #12]
  }

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
 8002fb8:	68fb      	ldr	r3, [r7, #12]
 8002fba:	2270      	movs	r2, #112	@ 0x70
 8002fbc:	4393      	bics	r3, r2
 8002fbe:	60fb      	str	r3, [r7, #12]
  /* Select the TRGO source */
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 8002fc0:	683b      	ldr	r3, [r7, #0]
 8002fc2:	681b      	ldr	r3, [r3, #0]
 8002fc4:	68fa      	ldr	r2, [r7, #12]
 8002fc6:	4313      	orrs	r3, r2
 8002fc8:	60fb      	str	r3, [r7, #12]

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;
 8002fca:	687b      	ldr	r3, [r7, #4]
 8002fcc:	681b      	ldr	r3, [r3, #0]
 8002fce:	68fa      	ldr	r2, [r7, #12]
 8002fd0:	605a      	str	r2, [r3, #4]

  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8002fd2:	687b      	ldr	r3, [r7, #4]
 8002fd4:	681b      	ldr	r3, [r3, #0]
 8002fd6:	4a11      	ldr	r2, [pc, #68]	@ (800301c <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
 8002fd8:	4293      	cmp	r3, r2
 8002fda:	d004      	beq.n	8002fe6 <HAL_TIMEx_MasterConfigSynchronization+0x82>
 8002fdc:	687b      	ldr	r3, [r7, #4]
 8002fde:	681b      	ldr	r3, [r3, #0]
 8002fe0:	4a10      	ldr	r2, [pc, #64]	@ (8003024 <HAL_TIMEx_MasterConfigSynchronization+0xc0>)
 8002fe2:	4293      	cmp	r3, r2
 8002fe4:	d10c      	bne.n	8003000 <HAL_TIMEx_MasterConfigSynchronization+0x9c>
  {
    /* Reset the MSM Bit */
    tmpsmcr &= ~TIM_SMCR_MSM;
 8002fe6:	68bb      	ldr	r3, [r7, #8]
 8002fe8:	2280      	movs	r2, #128	@ 0x80
 8002fea:	4393      	bics	r3, r2
 8002fec:	60bb      	str	r3, [r7, #8]
    /* Set master mode */
    tmpsmcr |= sMasterConfig->MasterSlaveMode;
 8002fee:	683b      	ldr	r3, [r7, #0]
 8002ff0:	689b      	ldr	r3, [r3, #8]
 8002ff2:	68ba      	ldr	r2, [r7, #8]
 8002ff4:	4313      	orrs	r3, r2
 8002ff6:	60bb      	str	r3, [r7, #8]

    /* Update TIMx SMCR */
    htim->Instance->SMCR = tmpsmcr;
 8002ff8:	687b      	ldr	r3, [r7, #4]
 8002ffa:	681b      	ldr	r3, [r3, #0]
 8002ffc:	68ba      	ldr	r2, [r7, #8]
 8002ffe:	609a      	str	r2, [r3, #8]
  }

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;
 8003000:	687b      	ldr	r3, [r7, #4]
 8003002:	223d      	movs	r2, #61	@ 0x3d
 8003004:	2101      	movs	r1, #1
 8003006:	5499      	strb	r1, [r3, r2]

  __HAL_UNLOCK(htim);
 8003008:	687b      	ldr	r3, [r7, #4]
 800300a:	223c      	movs	r2, #60	@ 0x3c
 800300c:	2100      	movs	r1, #0
 800300e:	5499      	strb	r1, [r3, r2]

  return HAL_OK;
 8003010:	2300      	movs	r3, #0
}
 8003012:	0018      	movs	r0, r3
 8003014:	46bd      	mov	sp, r7
 8003016:	b004      	add	sp, #16
 8003018:	bd80      	pop	{r7, pc}
 800301a:	46c0      	nop			@ (mov r8, r8)
 800301c:	40012c00 	.word	0x40012c00
 8003020:	ff0fffff 	.word	0xff0fffff
 8003024:	40000400 	.word	0x40000400

08003028 <memset>:
 8003028:	0003      	movs	r3, r0
 800302a:	1882      	adds	r2, r0, r2
 800302c:	4293      	cmp	r3, r2
 800302e:	d100      	bne.n	8003032 <memset+0xa>
 8003030:	4770      	bx	lr
 8003032:	7019      	strb	r1, [r3, #0]
 8003034:	3301      	adds	r3, #1
 8003036:	e7f9      	b.n	800302c <memset+0x4>

08003038 <__libc_init_array>:
 8003038:	b570      	push	{r4, r5, r6, lr}
 800303a:	2600      	movs	r6, #0
 800303c:	4c0c      	ldr	r4, [pc, #48]	@ (8003070 <__libc_init_array+0x38>)
 800303e:	4d0d      	ldr	r5, [pc, #52]	@ (8003074 <__libc_init_array+0x3c>)
 8003040:	1b64      	subs	r4, r4, r5
 8003042:	10a4      	asrs	r4, r4, #2
 8003044:	42a6      	cmp	r6, r4
 8003046:	d109      	bne.n	800305c <__libc_init_array+0x24>
 8003048:	2600      	movs	r6, #0
 800304a:	f000 f819 	bl	8003080 <_init>
 800304e:	4c0a      	ldr	r4, [pc, #40]	@ (8003078 <__libc_init_array+0x40>)
 8003050:	4d0a      	ldr	r5, [pc, #40]	@ (800307c <__libc_init_array+0x44>)
 8003052:	1b64      	subs	r4, r4, r5
 8003054:	10a4      	asrs	r4, r4, #2
 8003056:	42a6      	cmp	r6, r4
 8003058:	d105      	bne.n	8003066 <__libc_init_array+0x2e>
 800305a:	bd70      	pop	{r4, r5, r6, pc}
 800305c:	00b3      	lsls	r3, r6, #2
 800305e:	58eb      	ldr	r3, [r5, r3]
 8003060:	4798      	blx	r3
 8003062:	3601      	adds	r6, #1
 8003064:	e7ee      	b.n	8003044 <__libc_init_array+0xc>
 8003066:	00b3      	lsls	r3, r6, #2
 8003068:	58eb      	ldr	r3, [r5, r3]
 800306a:	4798      	blx	r3
 800306c:	3601      	adds	r6, #1
 800306e:	e7f2      	b.n	8003056 <__libc_init_array+0x1e>
 8003070:	080030d8 	.word	0x080030d8
 8003074:	080030d8 	.word	0x080030d8
 8003078:	080030dc 	.word	0x080030dc
 800307c:	080030d8 	.word	0x080030d8

08003080 <_init>:
 8003080:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8003082:	46c0      	nop			@ (mov r8, r8)
 8003084:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8003086:	bc08      	pop	{r3}
 8003088:	469e      	mov	lr, r3
 800308a:	4770      	bx	lr

0800308c <_fini>:
 800308c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800308e:	46c0      	nop			@ (mov r8, r8)
 8003090:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8003092:	bc08      	pop	{r3}
 8003094:	469e      	mov	lr, r3
 8003096:	4770      	bx	lr