andre
/
U-FOC


			
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STM32G431RB_Bootloader.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000001d8  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00002e80  080001d8  080001d8  000101d8  2**3
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000064  08003058  08003058  00013058  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  080030bc  080030bc  0002002c  2**0
                  CONTENTS
  4 .ARM          00000008  080030bc  080030bc  000130bc  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  080030c4  080030c4  0002002c  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  080030c4  080030c4  000130c4  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  080030c8  080030c8  000130c8  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         0000002c  20000000  080030cc  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00000100  2000002c  080030f8  0002002c  2**2
                  ALLOC
 10 ._user_heap_stack 00000604  2000012c  080030f8  0002012c  2**0
                  ALLOC
 11 .noinit       00000004  20007fc0  20007fc0  00027fc0  2**2
                  ALLOC
 12 .ARM.attributes 00000030  00000000  00000000  0002002c  2**0
                  CONTENTS, READONLY
 13 .debug_info   0001c9bb  00000000  00000000  0002005c  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_abbrev 0000348c  00000000  00000000  0003ca17  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_loc    0001707f  00000000  00000000  0003fea3  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_aranges 00000dc8  00000000  00000000  00056f28  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_ranges 00002468  00000000  00000000  00057cf0  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_macro  0001e337  00000000  00000000  0005a158  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .debug_line   0001c4d3  00000000  00000000  0007848f  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 20 .debug_str    000c573a  00000000  00000000  00094962  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 21 .comment      00000050  00000000  00000000  0015a09c  2**0
                  CONTENTS, READONLY
 22 .debug_frame  00002ab0  00000000  00000000  0015a0ec  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

080001d8 <__do_global_dtors_aux>:
 80001d8:	b510      	push	{r4, lr}
 80001da:	4c05      	ldr	r4, [pc, #20]	; (80001f0 <__do_global_dtors_aux+0x18>)
 80001dc:	7823      	ldrb	r3, [r4, #0]
 80001de:	b933      	cbnz	r3, 80001ee <__do_global_dtors_aux+0x16>
 80001e0:	4b04      	ldr	r3, [pc, #16]	; (80001f4 <__do_global_dtors_aux+0x1c>)
 80001e2:	b113      	cbz	r3, 80001ea <__do_global_dtors_aux+0x12>
 80001e4:	4804      	ldr	r0, [pc, #16]	; (80001f8 <__do_global_dtors_aux+0x20>)
 80001e6:	f3af 8000 	nop.w
 80001ea:	2301      	movs	r3, #1
 80001ec:	7023      	strb	r3, [r4, #0]
 80001ee:	bd10      	pop	{r4, pc}
 80001f0:	2000002c 	.word	0x2000002c
 80001f4:	00000000 	.word	0x00000000
 80001f8:	08003040 	.word	0x08003040

080001fc <frame_dummy>:
 80001fc:	b508      	push	{r3, lr}
 80001fe:	4b03      	ldr	r3, [pc, #12]	; (800020c <frame_dummy+0x10>)
 8000200:	b11b      	cbz	r3, 800020a <frame_dummy+0xe>
 8000202:	4903      	ldr	r1, [pc, #12]	; (8000210 <frame_dummy+0x14>)
 8000204:	4803      	ldr	r0, [pc, #12]	; (8000214 <frame_dummy+0x18>)
 8000206:	f3af 8000 	nop.w
 800020a:	bd08      	pop	{r3, pc}
 800020c:	00000000 	.word	0x00000000
 8000210:	20000030 	.word	0x20000030
 8000214:	08003040 	.word	0x08003040

08000218 <__aeabi_uldivmod>:
 8000218:	b953      	cbnz	r3, 8000230 <__aeabi_uldivmod+0x18>
 800021a:	b94a      	cbnz	r2, 8000230 <__aeabi_uldivmod+0x18>
 800021c:	2900      	cmp	r1, #0
 800021e:	bf08      	it	eq
 8000220:	2800      	cmpeq	r0, #0
 8000222:	bf1c      	itt	ne
 8000224:	f04f 31ff 	movne.w	r1, #4294967295	; 0xffffffff
 8000228:	f04f 30ff 	movne.w	r0, #4294967295	; 0xffffffff
 800022c:	f000 b974 	b.w	8000518 <__aeabi_idiv0>
 8000230:	f1ad 0c08 	sub.w	ip, sp, #8
 8000234:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 8000238:	f000 f806 	bl	8000248 <__udivmoddi4>
 800023c:	f8dd e004 	ldr.w	lr, [sp, #4]
 8000240:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8000244:	b004      	add	sp, #16
 8000246:	4770      	bx	lr

08000248 <__udivmoddi4>:
 8000248:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 800024c:	9d08      	ldr	r5, [sp, #32]
 800024e:	4604      	mov	r4, r0
 8000250:	468e      	mov	lr, r1
 8000252:	2b00      	cmp	r3, #0
 8000254:	d14d      	bne.n	80002f2 <__udivmoddi4+0xaa>
 8000256:	428a      	cmp	r2, r1
 8000258:	4694      	mov	ip, r2
 800025a:	d969      	bls.n	8000330 <__udivmoddi4+0xe8>
 800025c:	fab2 f282 	clz	r2, r2
 8000260:	b152      	cbz	r2, 8000278 <__udivmoddi4+0x30>
 8000262:	fa01 f302 	lsl.w	r3, r1, r2
 8000266:	f1c2 0120 	rsb	r1, r2, #32
 800026a:	fa20 f101 	lsr.w	r1, r0, r1
 800026e:	fa0c fc02 	lsl.w	ip, ip, r2
 8000272:	ea41 0e03 	orr.w	lr, r1, r3
 8000276:	4094      	lsls	r4, r2
 8000278:	ea4f 481c 	mov.w	r8, ip, lsr #16
 800027c:	0c21      	lsrs	r1, r4, #16
 800027e:	fbbe f6f8 	udiv	r6, lr, r8
 8000282:	fa1f f78c 	uxth.w	r7, ip
 8000286:	fb08 e316 	mls	r3, r8, r6, lr
 800028a:	ea41 4303 	orr.w	r3, r1, r3, lsl #16
 800028e:	fb06 f107 	mul.w	r1, r6, r7
 8000292:	4299      	cmp	r1, r3
 8000294:	d90a      	bls.n	80002ac <__udivmoddi4+0x64>
 8000296:	eb1c 0303 	adds.w	r3, ip, r3
 800029a:	f106 30ff 	add.w	r0, r6, #4294967295	; 0xffffffff
 800029e:	f080 811f 	bcs.w	80004e0 <__udivmoddi4+0x298>
 80002a2:	4299      	cmp	r1, r3
 80002a4:	f240 811c 	bls.w	80004e0 <__udivmoddi4+0x298>
 80002a8:	3e02      	subs	r6, #2
 80002aa:	4463      	add	r3, ip
 80002ac:	1a5b      	subs	r3, r3, r1
 80002ae:	b2a4      	uxth	r4, r4
 80002b0:	fbb3 f0f8 	udiv	r0, r3, r8
 80002b4:	fb08 3310 	mls	r3, r8, r0, r3
 80002b8:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
 80002bc:	fb00 f707 	mul.w	r7, r0, r7
 80002c0:	42a7      	cmp	r7, r4
 80002c2:	d90a      	bls.n	80002da <__udivmoddi4+0x92>
 80002c4:	eb1c 0404 	adds.w	r4, ip, r4
 80002c8:	f100 33ff 	add.w	r3, r0, #4294967295	; 0xffffffff
 80002cc:	f080 810a 	bcs.w	80004e4 <__udivmoddi4+0x29c>
 80002d0:	42a7      	cmp	r7, r4
 80002d2:	f240 8107 	bls.w	80004e4 <__udivmoddi4+0x29c>
 80002d6:	4464      	add	r4, ip
 80002d8:	3802      	subs	r0, #2
 80002da:	ea40 4006 	orr.w	r0, r0, r6, lsl #16
 80002de:	1be4      	subs	r4, r4, r7
 80002e0:	2600      	movs	r6, #0
 80002e2:	b11d      	cbz	r5, 80002ec <__udivmoddi4+0xa4>
 80002e4:	40d4      	lsrs	r4, r2
 80002e6:	2300      	movs	r3, #0
 80002e8:	e9c5 4300 	strd	r4, r3, [r5]
 80002ec:	4631      	mov	r1, r6
 80002ee:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002f2:	428b      	cmp	r3, r1
 80002f4:	d909      	bls.n	800030a <__udivmoddi4+0xc2>
 80002f6:	2d00      	cmp	r5, #0
 80002f8:	f000 80ef 	beq.w	80004da <__udivmoddi4+0x292>
 80002fc:	2600      	movs	r6, #0
 80002fe:	e9c5 0100 	strd	r0, r1, [r5]
 8000302:	4630      	mov	r0, r6
 8000304:	4631      	mov	r1, r6
 8000306:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800030a:	fab3 f683 	clz	r6, r3
 800030e:	2e00      	cmp	r6, #0
 8000310:	d14a      	bne.n	80003a8 <__udivmoddi4+0x160>
 8000312:	428b      	cmp	r3, r1
 8000314:	d302      	bcc.n	800031c <__udivmoddi4+0xd4>
 8000316:	4282      	cmp	r2, r0
 8000318:	f200 80f9 	bhi.w	800050e <__udivmoddi4+0x2c6>
 800031c:	1a84      	subs	r4, r0, r2
 800031e:	eb61 0303 	sbc.w	r3, r1, r3
 8000322:	2001      	movs	r0, #1
 8000324:	469e      	mov	lr, r3
 8000326:	2d00      	cmp	r5, #0
 8000328:	d0e0      	beq.n	80002ec <__udivmoddi4+0xa4>
 800032a:	e9c5 4e00 	strd	r4, lr, [r5]
 800032e:	e7dd      	b.n	80002ec <__udivmoddi4+0xa4>
 8000330:	b902      	cbnz	r2, 8000334 <__udivmoddi4+0xec>
 8000332:	deff      	udf	#255	; 0xff
 8000334:	fab2 f282 	clz	r2, r2
 8000338:	2a00      	cmp	r2, #0
 800033a:	f040 8092 	bne.w	8000462 <__udivmoddi4+0x21a>
 800033e:	eba1 010c 	sub.w	r1, r1, ip
 8000342:	ea4f 471c 	mov.w	r7, ip, lsr #16
 8000346:	fa1f fe8c 	uxth.w	lr, ip
 800034a:	2601      	movs	r6, #1
 800034c:	0c20      	lsrs	r0, r4, #16
 800034e:	fbb1 f3f7 	udiv	r3, r1, r7
 8000352:	fb07 1113 	mls	r1, r7, r3, r1
 8000356:	ea40 4101 	orr.w	r1, r0, r1, lsl #16
 800035a:	fb0e f003 	mul.w	r0, lr, r3
 800035e:	4288      	cmp	r0, r1
 8000360:	d908      	bls.n	8000374 <__udivmoddi4+0x12c>
 8000362:	eb1c 0101 	adds.w	r1, ip, r1
 8000366:	f103 38ff 	add.w	r8, r3, #4294967295	; 0xffffffff
 800036a:	d202      	bcs.n	8000372 <__udivmoddi4+0x12a>
 800036c:	4288      	cmp	r0, r1
 800036e:	f200 80cb 	bhi.w	8000508 <__udivmoddi4+0x2c0>
 8000372:	4643      	mov	r3, r8
 8000374:	1a09      	subs	r1, r1, r0
 8000376:	b2a4      	uxth	r4, r4
 8000378:	fbb1 f0f7 	udiv	r0, r1, r7
 800037c:	fb07 1110 	mls	r1, r7, r0, r1
 8000380:	ea44 4401 	orr.w	r4, r4, r1, lsl #16
 8000384:	fb0e fe00 	mul.w	lr, lr, r0
 8000388:	45a6      	cmp	lr, r4
 800038a:	d908      	bls.n	800039e <__udivmoddi4+0x156>
 800038c:	eb1c 0404 	adds.w	r4, ip, r4
 8000390:	f100 31ff 	add.w	r1, r0, #4294967295	; 0xffffffff
 8000394:	d202      	bcs.n	800039c <__udivmoddi4+0x154>
 8000396:	45a6      	cmp	lr, r4
 8000398:	f200 80bb 	bhi.w	8000512 <__udivmoddi4+0x2ca>
 800039c:	4608      	mov	r0, r1
 800039e:	eba4 040e 	sub.w	r4, r4, lr
 80003a2:	ea40 4003 	orr.w	r0, r0, r3, lsl #16
 80003a6:	e79c      	b.n	80002e2 <__udivmoddi4+0x9a>
 80003a8:	f1c6 0720 	rsb	r7, r6, #32
 80003ac:	40b3      	lsls	r3, r6
 80003ae:	fa22 fc07 	lsr.w	ip, r2, r7
 80003b2:	ea4c 0c03 	orr.w	ip, ip, r3
 80003b6:	fa20 f407 	lsr.w	r4, r0, r7
 80003ba:	fa01 f306 	lsl.w	r3, r1, r6
 80003be:	431c      	orrs	r4, r3
 80003c0:	40f9      	lsrs	r1, r7
 80003c2:	ea4f 491c 	mov.w	r9, ip, lsr #16
 80003c6:	fa00 f306 	lsl.w	r3, r0, r6
 80003ca:	fbb1 f8f9 	udiv	r8, r1, r9
 80003ce:	0c20      	lsrs	r0, r4, #16
 80003d0:	fa1f fe8c 	uxth.w	lr, ip
 80003d4:	fb09 1118 	mls	r1, r9, r8, r1
 80003d8:	ea40 4101 	orr.w	r1, r0, r1, lsl #16
 80003dc:	fb08 f00e 	mul.w	r0, r8, lr
 80003e0:	4288      	cmp	r0, r1
 80003e2:	fa02 f206 	lsl.w	r2, r2, r6
 80003e6:	d90b      	bls.n	8000400 <__udivmoddi4+0x1b8>
 80003e8:	eb1c 0101 	adds.w	r1, ip, r1
 80003ec:	f108 3aff 	add.w	sl, r8, #4294967295	; 0xffffffff
 80003f0:	f080 8088 	bcs.w	8000504 <__udivmoddi4+0x2bc>
 80003f4:	4288      	cmp	r0, r1
 80003f6:	f240 8085 	bls.w	8000504 <__udivmoddi4+0x2bc>
 80003fa:	f1a8 0802 	sub.w	r8, r8, #2
 80003fe:	4461      	add	r1, ip
 8000400:	1a09      	subs	r1, r1, r0
 8000402:	b2a4      	uxth	r4, r4
 8000404:	fbb1 f0f9 	udiv	r0, r1, r9
 8000408:	fb09 1110 	mls	r1, r9, r0, r1
 800040c:	ea44 4101 	orr.w	r1, r4, r1, lsl #16
 8000410:	fb00 fe0e 	mul.w	lr, r0, lr
 8000414:	458e      	cmp	lr, r1
 8000416:	d908      	bls.n	800042a <__udivmoddi4+0x1e2>
 8000418:	eb1c 0101 	adds.w	r1, ip, r1
 800041c:	f100 34ff 	add.w	r4, r0, #4294967295	; 0xffffffff
 8000420:	d26c      	bcs.n	80004fc <__udivmoddi4+0x2b4>
 8000422:	458e      	cmp	lr, r1
 8000424:	d96a      	bls.n	80004fc <__udivmoddi4+0x2b4>
 8000426:	3802      	subs	r0, #2
 8000428:	4461      	add	r1, ip
 800042a:	ea40 4008 	orr.w	r0, r0, r8, lsl #16
 800042e:	fba0 9402 	umull	r9, r4, r0, r2
 8000432:	eba1 010e 	sub.w	r1, r1, lr
 8000436:	42a1      	cmp	r1, r4
 8000438:	46c8      	mov	r8, r9
 800043a:	46a6      	mov	lr, r4
 800043c:	d356      	bcc.n	80004ec <__udivmoddi4+0x2a4>
 800043e:	d053      	beq.n	80004e8 <__udivmoddi4+0x2a0>
 8000440:	b15d      	cbz	r5, 800045a <__udivmoddi4+0x212>
 8000442:	ebb3 0208 	subs.w	r2, r3, r8
 8000446:	eb61 010e 	sbc.w	r1, r1, lr
 800044a:	fa01 f707 	lsl.w	r7, r1, r7
 800044e:	fa22 f306 	lsr.w	r3, r2, r6
 8000452:	40f1      	lsrs	r1, r6
 8000454:	431f      	orrs	r7, r3
 8000456:	e9c5 7100 	strd	r7, r1, [r5]
 800045a:	2600      	movs	r6, #0
 800045c:	4631      	mov	r1, r6
 800045e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000462:	f1c2 0320 	rsb	r3, r2, #32
 8000466:	40d8      	lsrs	r0, r3
 8000468:	fa0c fc02 	lsl.w	ip, ip, r2
 800046c:	fa21 f303 	lsr.w	r3, r1, r3
 8000470:	4091      	lsls	r1, r2
 8000472:	4301      	orrs	r1, r0
 8000474:	ea4f 471c 	mov.w	r7, ip, lsr #16
 8000478:	fa1f fe8c 	uxth.w	lr, ip
 800047c:	fbb3 f0f7 	udiv	r0, r3, r7
 8000480:	fb07 3610 	mls	r6, r7, r0, r3
 8000484:	0c0b      	lsrs	r3, r1, #16
 8000486:	ea43 4306 	orr.w	r3, r3, r6, lsl #16
 800048a:	fb00 f60e 	mul.w	r6, r0, lr
 800048e:	429e      	cmp	r6, r3
 8000490:	fa04 f402 	lsl.w	r4, r4, r2
 8000494:	d908      	bls.n	80004a8 <__udivmoddi4+0x260>
 8000496:	eb1c 0303 	adds.w	r3, ip, r3
 800049a:	f100 38ff 	add.w	r8, r0, #4294967295	; 0xffffffff
 800049e:	d22f      	bcs.n	8000500 <__udivmoddi4+0x2b8>
 80004a0:	429e      	cmp	r6, r3
 80004a2:	d92d      	bls.n	8000500 <__udivmoddi4+0x2b8>
 80004a4:	3802      	subs	r0, #2
 80004a6:	4463      	add	r3, ip
 80004a8:	1b9b      	subs	r3, r3, r6
 80004aa:	b289      	uxth	r1, r1
 80004ac:	fbb3 f6f7 	udiv	r6, r3, r7
 80004b0:	fb07 3316 	mls	r3, r7, r6, r3
 80004b4:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
 80004b8:	fb06 f30e 	mul.w	r3, r6, lr
 80004bc:	428b      	cmp	r3, r1
 80004be:	d908      	bls.n	80004d2 <__udivmoddi4+0x28a>
 80004c0:	eb1c 0101 	adds.w	r1, ip, r1
 80004c4:	f106 38ff 	add.w	r8, r6, #4294967295	; 0xffffffff
 80004c8:	d216      	bcs.n	80004f8 <__udivmoddi4+0x2b0>
 80004ca:	428b      	cmp	r3, r1
 80004cc:	d914      	bls.n	80004f8 <__udivmoddi4+0x2b0>
 80004ce:	3e02      	subs	r6, #2
 80004d0:	4461      	add	r1, ip
 80004d2:	1ac9      	subs	r1, r1, r3
 80004d4:	ea46 4600 	orr.w	r6, r6, r0, lsl #16
 80004d8:	e738      	b.n	800034c <__udivmoddi4+0x104>
 80004da:	462e      	mov	r6, r5
 80004dc:	4628      	mov	r0, r5
 80004de:	e705      	b.n	80002ec <__udivmoddi4+0xa4>
 80004e0:	4606      	mov	r6, r0
 80004e2:	e6e3      	b.n	80002ac <__udivmoddi4+0x64>
 80004e4:	4618      	mov	r0, r3
 80004e6:	e6f8      	b.n	80002da <__udivmoddi4+0x92>
 80004e8:	454b      	cmp	r3, r9
 80004ea:	d2a9      	bcs.n	8000440 <__udivmoddi4+0x1f8>
 80004ec:	ebb9 0802 	subs.w	r8, r9, r2
 80004f0:	eb64 0e0c 	sbc.w	lr, r4, ip
 80004f4:	3801      	subs	r0, #1
 80004f6:	e7a3      	b.n	8000440 <__udivmoddi4+0x1f8>
 80004f8:	4646      	mov	r6, r8
 80004fa:	e7ea      	b.n	80004d2 <__udivmoddi4+0x28a>
 80004fc:	4620      	mov	r0, r4
 80004fe:	e794      	b.n	800042a <__udivmoddi4+0x1e2>
 8000500:	4640      	mov	r0, r8
 8000502:	e7d1      	b.n	80004a8 <__udivmoddi4+0x260>
 8000504:	46d0      	mov	r8, sl
 8000506:	e77b      	b.n	8000400 <__udivmoddi4+0x1b8>
 8000508:	3b02      	subs	r3, #2
 800050a:	4461      	add	r1, ip
 800050c:	e732      	b.n	8000374 <__udivmoddi4+0x12c>
 800050e:	4630      	mov	r0, r6
 8000510:	e709      	b.n	8000326 <__udivmoddi4+0xde>
 8000512:	4464      	add	r4, ip
 8000514:	3802      	subs	r0, #2
 8000516:	e742      	b.n	800039e <__udivmoddi4+0x156>

08000518 <__aeabi_idiv0>:
 8000518:	4770      	bx	lr
 800051a:	bf00      	nop

0800051c <Bootloader_Deinit_All>:
static const uint32_t XTEA_KEY[4] = {
    0xA56BABCD, 0x0000FFFF, 0xABCDEF12, 0x13572468
};


void Bootloader_Deinit_All(void) {
 800051c:	b510      	push	{r4, lr}
	// Deinit ALL
	HAL_TIM_Base_Stop(&htim6);
 800051e:	4c10      	ldr	r4, [pc, #64]	; (8000560 <Bootloader_Deinit_All+0x44>)
void Bootloader_Deinit_All(void) {
 8000520:	b086      	sub	sp, #24
	HAL_TIM_Base_Stop(&htim6);
 8000522:	4620      	mov	r0, r4
 8000524:	f001 fe68 	bl	80021f8 <HAL_TIM_Base_Stop>
	HAL_TIM_Base_DeInit(&htim6);
 8000528:	4620      	mov	r0, r4
 800052a:	f001 fe31 	bl	8002190 <HAL_TIM_Base_DeInit>
	HAL_UART_DeInit(&huart1);
 800052e:	480d      	ldr	r0, [pc, #52]	; (8000564 <Bootloader_Deinit_All+0x48>)
 8000530:	f001 fff6 	bl	8002520 <HAL_UART_DeInit>

	GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000534:	2300      	movs	r3, #0
	GPIO_InitStruct.Pin = LED_Pin;
 8000536:	f44f 5200 	mov.w	r2, #8192	; 0x2000
	HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
 800053a:	a901      	add	r1, sp, #4
 800053c:	480a      	ldr	r0, [pc, #40]	; (8000568 <Bootloader_Deinit_All+0x4c>)
	GPIO_InitTypeDef GPIO_InitStruct = {0};
 800053e:	9305      	str	r3, [sp, #20]
 8000540:	e9cd 2301 	strd	r2, r3, [sp, #4]
 8000544:	e9cd 3303 	strd	r3, r3, [sp, #12]
	HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
 8000548:	f000 fe3a 	bl	80011c0 <HAL_GPIO_Init>
	GPIO_InitStruct.Pin = KEY_Pin;
 800054c:	2304      	movs	r3, #4
	HAL_GPIO_Init(KEY_GPIO_Port, &GPIO_InitStruct);
 800054e:	4807      	ldr	r0, [pc, #28]	; (800056c <Bootloader_Deinit_All+0x50>)
	GPIO_InitStruct.Pin = KEY_Pin;
 8000550:	9301      	str	r3, [sp, #4]
	HAL_GPIO_Init(KEY_GPIO_Port, &GPIO_InitStruct);
 8000552:	eb0d 0103 	add.w	r1, sp, r3
 8000556:	f000 fe33 	bl	80011c0 <HAL_GPIO_Init>
}
 800055a:	b006      	add	sp, #24
 800055c:	bd10      	pop	{r4, pc}
 800055e:	bf00      	nop
 8000560:	20000048 	.word	0x20000048
 8000564:	20000094 	.word	0x20000094
 8000568:	48000800 	.word	0x48000800
 800056c:	48000c00 	.word	0x48000c00

08000570 <Bootloader_flag>:
	}

    HAL_FLASH_Lock();
}

uint8_t Bootloader_flag(void) {
 8000570:	b508      	push	{r3, lr}
	if (HAL_GPIO_ReadPin(KEY_GPIO_Port, KEY_Pin) == GPIO_PIN_SET) {
 8000572:	4807      	ldr	r0, [pc, #28]	; (8000590 <Bootloader_flag+0x20>)
 8000574:	2104      	movs	r1, #4
 8000576:	f000 ffc7 	bl	8001508 <HAL_GPIO_ReadPin>
 800057a:	2801      	cmp	r0, #1
 800057c:	d006      	beq.n	800058c <Bootloader_flag+0x1c>
		return 1;
	} else {
		return (boot_magic == BOOT_MAGIC_VALUE);
 800057e:	4a05      	ldr	r2, [pc, #20]	; (8000594 <Bootloader_flag+0x24>)
 8000580:	4b05      	ldr	r3, [pc, #20]	; (8000598 <Bootloader_flag+0x28>)
 8000582:	6810      	ldr	r0, [r2, #0]
 8000584:	1ac0      	subs	r0, r0, r3
 8000586:	fab0 f080 	clz	r0, r0
 800058a:	0940      	lsrs	r0, r0, #5
	}
}
 800058c:	bd08      	pop	{r3, pc}
 800058e:	bf00      	nop
 8000590:	48000c00 	.word	0x48000c00
 8000594:	20007fc0 	.word	0x20007fc0
 8000598:	b001b001 	.word	0xb001b001

0800059c <Bootloader_flag_reset>:

void Bootloader_flag_reset(void) {
	boot_magic = 0;
 800059c:	4b01      	ldr	r3, [pc, #4]	; (80005a4 <Bootloader_flag_reset+0x8>)
 800059e:	2200      	movs	r2, #0
 80005a0:	601a      	str	r2, [r3, #0]
}
 80005a2:	4770      	bx	lr
 80005a4:	20007fc0 	.word	0x20007fc0

080005a8 <Bootloader_cmd>:

    HAL_FLASH_Lock();
}

void Bootloader_cmd(void)
{
 80005a8:	b580      	push	{r7, lr}
	EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
 80005aa:	ed9f 8b91 	vldr	d8, [pc, #580]	; 80007f0 <Bootloader_cmd+0x248>
{
 80005ae:	b08a      	sub	sp, #40	; 0x28
    uint8_t rx[1], tx;

    while (1) {
        tx = '$';
        HAL_UART_Transmit(&huart1, &tx, 1, 100);
 80005b0:	f8df 8264 	ldr.w	r8, [pc, #612]	; 8000818 <Bootloader_cmd+0x270>
 80005b4:	ac02      	add	r4, sp, #8
 80005b6:	ad04      	add	r5, sp, #16
 80005b8:	af06      	add	r7, sp, #24
        tx = '$';
 80005ba:	2024      	movs	r0, #36	; 0x24
        HAL_UART_Transmit(&huart1, &tx, 1, 100);
 80005bc:	2364      	movs	r3, #100	; 0x64
 80005be:	2201      	movs	r2, #1
 80005c0:	f10d 0107 	add.w	r1, sp, #7
        tx = '$';
 80005c4:	f88d 0007 	strb.w	r0, [sp, #7]
        HAL_UART_Transmit(&huart1, &tx, 1, 100);
 80005c8:	4640      	mov	r0, r8
 80005ca:	f001 ffc9 	bl	8002560 <HAL_UART_Transmit>
    	HAL_UART_Receive(&huart1, rx, 1, HAL_MAX_DELAY);
 80005ce:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
 80005d2:	2201      	movs	r2, #1
 80005d4:	a901      	add	r1, sp, #4
 80005d6:	4640      	mov	r0, r8
 80005d8:	f002 f840 	bl	800265c <HAL_UART_Receive>

    	// Erase Chip
    	if (rx[0] == 'e') {
 80005dc:	f89d 3004 	ldrb.w	r3, [sp, #4]
 80005e0:	2b65      	cmp	r3, #101	; 0x65
 80005e2:	f000 80c3 	beq.w	800076c <Bootloader_cmd+0x1c4>
    			// Erase
    			Flash_erase();
    		}
    	}

    	if (rx[0] == 'u') {
 80005e6:	2b75      	cmp	r3, #117	; 0x75
 80005e8:	f000 8081 	beq.w	80006ee <Bootloader_cmd+0x146>
			tx = '>';
			HAL_UART_Transmit(&huart1, &tx, 1, 100);
			Bootloader_run(0);
    	}

    	if (rx[0] == 'c') {
 80005ec:	2b63      	cmp	r3, #99	; 0x63
 80005ee:	d025      	beq.n	800063c <Bootloader_cmd+0x94>
			tx = '>';
			HAL_UART_Transmit(&huart1, &tx, 1, 100);
    		Bootloader_run(1);
    	}

    	if (rx[0] == 'r') {
 80005f0:	2b72      	cmp	r3, #114	; 0x72
 80005f2:	d1e2      	bne.n	80005ba <Bootloader_cmd+0x12>
	HAL_TIM_Base_Stop(&htim6);
 80005f4:	4880      	ldr	r0, [pc, #512]	; (80007f8 <Bootloader_cmd+0x250>)
 80005f6:	f001 fdff 	bl	80021f8 <HAL_TIM_Base_Stop>
	HAL_TIM_Base_DeInit(&htim6);
 80005fa:	487f      	ldr	r0, [pc, #508]	; (80007f8 <Bootloader_cmd+0x250>)
 80005fc:	f001 fdc8 	bl	8002190 <HAL_TIM_Base_DeInit>
	HAL_UART_DeInit(&huart1);
 8000600:	4640      	mov	r0, r8
 8000602:	f001 ff8d 	bl	8002520 <HAL_UART_DeInit>
	GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000606:	2300      	movs	r3, #0
	GPIO_InitStruct.Pin = LED_Pin;
 8000608:	f44f 5200 	mov.w	r2, #8192	; 0x2000
	HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
 800060c:	4629      	mov	r1, r5
 800060e:	487b      	ldr	r0, [pc, #492]	; (80007fc <Bootloader_cmd+0x254>)
	GPIO_InitStruct.Pin = LED_Pin;
 8000610:	9204      	str	r2, [sp, #16]
	GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000612:	e9cd 3305 	strd	r3, r3, [sp, #20]
 8000616:	e9cd 3307 	strd	r3, r3, [sp, #28]
	HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
 800061a:	f000 fdd1 	bl	80011c0 <HAL_GPIO_Init>
	GPIO_InitStruct.Pin = KEY_Pin;
 800061e:	2304      	movs	r3, #4
	HAL_GPIO_Init(KEY_GPIO_Port, &GPIO_InitStruct);
 8000620:	4629      	mov	r1, r5
 8000622:	4877      	ldr	r0, [pc, #476]	; (8000800 <Bootloader_cmd+0x258>)
	GPIO_InitStruct.Pin = KEY_Pin;
 8000624:	9304      	str	r3, [sp, #16]
	HAL_GPIO_Init(KEY_GPIO_Port, &GPIO_InitStruct);
 8000626:	f000 fdcb 	bl	80011c0 <HAL_GPIO_Init>
void Bootloader_jump_to_app(void)
{
  	uint32_t appJumpAddress;
  	void (*GoToApp)(void);

  	appJumpAddress = *((volatile uint32_t*)(APP_ADDRESS + 4));
 800062a:	4b76      	ldr	r3, [pc, #472]	; (8000804 <Bootloader_cmd+0x25c>)
  	GoToApp = (void (*)(void))appJumpAddress;
  	SCB->VTOR = APP_ADDRESS;
 800062c:	4976      	ldr	r1, [pc, #472]	; (8000808 <Bootloader_cmd+0x260>)
  	appJumpAddress = *((volatile uint32_t*)(APP_ADDRESS + 4));
 800062e:	685a      	ldr	r2, [r3, #4]
  	SCB->VTOR = APP_ADDRESS;
 8000630:	608b      	str	r3, [r1, #8]
  	__set_MSP(*((volatile uint32_t*) APP_ADDRESS)); //stack pointer (to RAM) for USER app in this address
 8000632:	681b      	ldr	r3, [r3, #0]
  \details Assigns the given value to the Main Stack Pointer (MSP).
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
 8000634:	f383 8808 	msr	MSP, r3
  	GoToApp();
 8000638:	4790      	blx	r2
}
 800063a:	e7be      	b.n	80005ba <Bootloader_cmd+0x12>
			tx = '>';
 800063c:	203e      	movs	r0, #62	; 0x3e
 800063e:	f88d 0007 	strb.w	r0, [sp, #7]
			HAL_UART_Transmit(&huart1, &tx, 1, 100);
 8000642:	2364      	movs	r3, #100	; 0x64
 8000644:	2201      	movs	r2, #1
 8000646:	f10d 0107 	add.w	r1, sp, #7
 800064a:	4640      	mov	r0, r8
 800064c:	f001 ff88 	bl	8002560 <HAL_UART_Transmit>
    uint32_t flash_addr = APP_ADDRESS;
 8000650:	f8df 91b0 	ldr.w	r9, [pc, #432]	; 8000804 <Bootloader_cmd+0x25c>
            		xtea_decrypt(block, XTEA_KEY);
 8000654:	f8df a1c4 	ldr.w	sl, [pc, #452]	; 800081c <Bootloader_cmd+0x274>
    	Status = HAL_UART_Receive(&huart1, rx, PACKET_SIZE, 1000);
 8000658:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 800065c:	2210      	movs	r2, #16
 800065e:	4629      	mov	r1, r5
 8000660:	4640      	mov	r0, r8
 8000662:	f001 fffb 	bl	800265c <HAL_UART_Receive>
    	if (Status == HAL_OK) {
 8000666:	4606      	mov	r6, r0
 8000668:	bbe0      	cbnz	r0, 80006e4 <Bootloader_cmd+0x13c>
            		memcpy(block, &rx[i], 8);
 800066a:	e895 0003 	ldmia.w	r5, {r0, r1}
 800066e:	e884 0003 	stmia.w	r4, {r0, r1}
            		xtea_decrypt(block, XTEA_KEY);
 8000672:	4651      	mov	r1, sl
 8000674:	4620      	mov	r0, r4
 8000676:	f000 fa99 	bl	8000bac <xtea_decrypt>
            		memcpy(&rx[i], block, 8);
 800067a:	e894 0003 	ldmia.w	r4, {r0, r1}
 800067e:	e885 0003 	stmia.w	r5, {r0, r1}
            		memcpy(block, &rx[i], 8);
 8000682:	e897 0003 	ldmia.w	r7, {r0, r1}
 8000686:	e884 0003 	stmia.w	r4, {r0, r1}
            		xtea_decrypt(block, XTEA_KEY);
 800068a:	4651      	mov	r1, sl
 800068c:	4620      	mov	r0, r4
 800068e:	f000 fa8d 	bl	8000bac <xtea_decrypt>
            		memcpy(&rx[i], block, 8);
 8000692:	e894 0003 	ldmia.w	r4, {r0, r1}
 8000696:	e887 0003 	stmia.w	r7, {r0, r1}
    HAL_FLASH_Unlock();
 800069a:	f000 fc69 	bl	8000f70 <HAL_FLASH_Unlock>
        memcpy(&d, data + i, 8);
 800069e:	e895 0003 	ldmia.w	r5, {r0, r1}
 80006a2:	e884 0003 	stmia.w	r4, {r0, r1}
        HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, addr + i, d);
 80006a6:	4649      	mov	r1, r9
 80006a8:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 80006ac:	4630      	mov	r0, r6
 80006ae:	f000 fba5 	bl	8000dfc <HAL_FLASH_Program>
        memcpy(&d, data + i, 8);
 80006b2:	e897 0003 	ldmia.w	r7, {r0, r1}
 80006b6:	e884 0003 	stmia.w	r4, {r0, r1}
        HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, addr + i, d);
 80006ba:	f109 0108 	add.w	r1, r9, #8
 80006be:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 80006c2:	4630      	mov	r0, r6
 80006c4:	f000 fb9a 	bl	8000dfc <HAL_FLASH_Program>
        	uint8_t ack = 0x7F;
 80006c8:	267f      	movs	r6, #127	; 0x7f
    HAL_FLASH_Lock();
 80006ca:	f000 fc65 	bl	8000f98 <HAL_FLASH_Lock>
        	HAL_UART_Transmit(&huart1, &ack, 1, 100);
 80006ce:	2364      	movs	r3, #100	; 0x64
 80006d0:	2201      	movs	r2, #1
 80006d2:	4621      	mov	r1, r4
 80006d4:	4640      	mov	r0, r8
        	flash_addr += PACKET_SIZE;
 80006d6:	f109 0910 	add.w	r9, r9, #16
        	uint8_t ack = 0x7F;
 80006da:	f88d 6008 	strb.w	r6, [sp, #8]
        	HAL_UART_Transmit(&huart1, &ack, 1, 100);
 80006de:	f001 ff3f 	bl	8002560 <HAL_UART_Transmit>
 80006e2:	e7b9      	b.n	8000658 <Bootloader_cmd+0xb0>
    		if (Status == HAL_TIMEOUT) {
 80006e4:	2803      	cmp	r0, #3
 80006e6:	d1b7      	bne.n	8000658 <Bootloader_cmd+0xb0>
    	if (rx[0] == 'r') {
 80006e8:	f89d 3004 	ldrb.w	r3, [sp, #4]
}
 80006ec:	e780      	b.n	80005f0 <Bootloader_cmd+0x48>
			tx = '>';
 80006ee:	203e      	movs	r0, #62	; 0x3e
 80006f0:	f88d 0007 	strb.w	r0, [sp, #7]
			HAL_UART_Transmit(&huart1, &tx, 1, 100);
 80006f4:	2364      	movs	r3, #100	; 0x64
 80006f6:	2201      	movs	r2, #1
 80006f8:	f10d 0107 	add.w	r1, sp, #7
 80006fc:	4640      	mov	r0, r8
 80006fe:	f001 ff2f 	bl	8002560 <HAL_UART_Transmit>
    uint32_t flash_addr = APP_ADDRESS;
 8000702:	f8df 9100 	ldr.w	r9, [pc, #256]	; 8000804 <Bootloader_cmd+0x25c>
    	Status = HAL_UART_Receive(&huart1, rx, PACKET_SIZE, 1000);
 8000706:	4629      	mov	r1, r5
 8000708:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 800070c:	2210      	movs	r2, #16
 800070e:	4640      	mov	r0, r8
 8000710:	f001 ffa4 	bl	800265c <HAL_UART_Receive>
    	if (Status == HAL_OK) {
 8000714:	4606      	mov	r6, r0
 8000716:	bb20      	cbnz	r0, 8000762 <Bootloader_cmd+0x1ba>
    HAL_FLASH_Unlock();
 8000718:	f000 fc2a 	bl	8000f70 <HAL_FLASH_Unlock>
        memcpy(&d, data + i, 8);
 800071c:	e895 0003 	ldmia.w	r5, {r0, r1}
 8000720:	e884 0003 	stmia.w	r4, {r0, r1}
        HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, addr + i, d);
 8000724:	4649      	mov	r1, r9
 8000726:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 800072a:	4630      	mov	r0, r6
 800072c:	f000 fb66 	bl	8000dfc <HAL_FLASH_Program>
        memcpy(&d, data + i, 8);
 8000730:	e897 0003 	ldmia.w	r7, {r0, r1}
 8000734:	e884 0003 	stmia.w	r4, {r0, r1}
        HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, addr + i, d);
 8000738:	f109 0108 	add.w	r1, r9, #8
 800073c:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8000740:	4630      	mov	r0, r6
 8000742:	f000 fb5b 	bl	8000dfc <HAL_FLASH_Program>
        	uint8_t ack = 0x7F;
 8000746:	267f      	movs	r6, #127	; 0x7f
    HAL_FLASH_Lock();
 8000748:	f000 fc26 	bl	8000f98 <HAL_FLASH_Lock>
        	HAL_UART_Transmit(&huart1, &ack, 1, 100);
 800074c:	2364      	movs	r3, #100	; 0x64
 800074e:	2201      	movs	r2, #1
 8000750:	4621      	mov	r1, r4
 8000752:	4640      	mov	r0, r8
        	flash_addr += PACKET_SIZE;
 8000754:	f109 0910 	add.w	r9, r9, #16
        	uint8_t ack = 0x7F;
 8000758:	f88d 6008 	strb.w	r6, [sp, #8]
        	HAL_UART_Transmit(&huart1, &ack, 1, 100);
 800075c:	f001 ff00 	bl	8002560 <HAL_UART_Transmit>
 8000760:	e7d1      	b.n	8000706 <Bootloader_cmd+0x15e>
    		if (Status == HAL_TIMEOUT) {
 8000762:	2803      	cmp	r0, #3
 8000764:	d1cf      	bne.n	8000706 <Bootloader_cmd+0x15e>
    	if (rx[0] == 'c') {
 8000766:	f89d 3004 	ldrb.w	r3, [sp, #4]
}
 800076a:	e73f      	b.n	80005ec <Bootloader_cmd+0x44>
    		tx = '?';
 800076c:	203f      	movs	r0, #63	; 0x3f
    		HAL_UART_Transmit(&huart1, &tx, 1, 100);
 800076e:	2364      	movs	r3, #100	; 0x64
 8000770:	2201      	movs	r2, #1
 8000772:	f10d 0107 	add.w	r1, sp, #7
    		tx = '?';
 8000776:	f88d 0007 	strb.w	r0, [sp, #7]
    		HAL_UART_Transmit(&huart1, &tx, 1, 100);
 800077a:	4640      	mov	r0, r8
 800077c:	f001 fef0 	bl	8002560 <HAL_UART_Transmit>
    		HAL_UART_Receive(&huart1, rx, 1, 1000);
 8000780:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8000784:	2201      	movs	r2, #1
 8000786:	a901      	add	r1, sp, #4
 8000788:	4640      	mov	r0, r8
 800078a:	f001 ff67 	bl	800265c <HAL_UART_Receive>
    		if (rx[0] == 'y') {
 800078e:	f89d 3004 	ldrb.w	r3, [sp, #4]
 8000792:	2b79      	cmp	r3, #121	; 0x79
 8000794:	f47f af27 	bne.w	80005e6 <Bootloader_cmd+0x3e>
	uint32_t PageError = 0;
 8000798:	2300      	movs	r3, #0
 800079a:	9302      	str	r3, [sp, #8]
	HAL_FLASH_Unlock();
 800079c:	f000 fbe8 	bl	8000f70 <HAL_FLASH_Unlock>
	EraseInitStruct.NbPages = FLASH_PAGE_NB - flash_start_page;
 80007a0:	4b1a      	ldr	r3, [pc, #104]	; (800080c <Bootloader_cmd+0x264>)
 80007a2:	f8b3 20e0 	ldrh.w	r2, [r3, #224]	; 0xe0
 80007a6:	f64f 73ff 	movw	r3, #65535	; 0xffff
	EraseInitStruct.Page = flash_start_page;
 80007aa:	2110      	movs	r1, #16
	EraseInitStruct.NbPages = FLASH_PAGE_NB - flash_start_page;
 80007ac:	429a      	cmp	r2, r3
	EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
 80007ae:	ed8d 8b04 	vstr	d8, [sp, #16]
	EraseInitStruct.Page = flash_start_page;
 80007b2:	9106      	str	r1, [sp, #24]
	EraseInitStruct.NbPages = FLASH_PAGE_NB - flash_start_page;
 80007b4:	d017      	beq.n	80007e6 <Bootloader_cmd+0x23e>
 80007b6:	4a16      	ldr	r2, [pc, #88]	; (8000810 <Bootloader_cmd+0x268>)
 80007b8:	4b16      	ldr	r3, [pc, #88]	; (8000814 <Bootloader_cmd+0x26c>)
 80007ba:	f8d2 25e0 	ldr.w	r2, [r2, #1504]	; 0x5e0
 80007be:	ea03 2382 	and.w	r3, r3, r2, lsl #10
 80007c2:	f5b3 2f00 	cmp.w	r3, #524288	; 0x80000
 80007c6:	d010      	beq.n	80007ea <Bootloader_cmd+0x242>
 80007c8:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
 80007cc:	bf14      	ite	ne
 80007ce:	2330      	movne	r3, #48	; 0x30
 80007d0:	2370      	moveq	r3, #112	; 0x70
	if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) == HAL_OK)
 80007d2:	4621      	mov	r1, r4
 80007d4:	4628      	mov	r0, r5
	EraseInitStruct.NbPages = FLASH_PAGE_NB - flash_start_page;
 80007d6:	9307      	str	r3, [sp, #28]
	if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) == HAL_OK)
 80007d8:	f000 fc14 	bl	8001004 <HAL_FLASHEx_Erase>
    HAL_FLASH_Lock();
 80007dc:	f000 fbdc 	bl	8000f98 <HAL_FLASH_Lock>
    	if (rx[0] == 'u') {
 80007e0:	f89d 3004 	ldrb.w	r3, [sp, #4]
}
 80007e4:	e6ff      	b.n	80005e6 <Bootloader_cmd+0x3e>
 80007e6:	2330      	movs	r3, #48	; 0x30
 80007e8:	e7f3      	b.n	80007d2 <Bootloader_cmd+0x22a>
 80007ea:	23f0      	movs	r3, #240	; 0xf0
 80007ec:	e7f1      	b.n	80007d2 <Bootloader_cmd+0x22a>
 80007ee:	bf00      	nop
	...
 80007f8:	20000048 	.word	0x20000048
 80007fc:	48000800 	.word	0x48000800
 8000800:	48000c00 	.word	0x48000c00
 8000804:	08008000 	.word	0x08008000
 8000808:	e000ed00 	.word	0xe000ed00
 800080c:	1fff7500 	.word	0x1fff7500
 8000810:	1fff7000 	.word	0x1fff7000
 8000814:	03fffc00 	.word	0x03fffc00
 8000818:	20000094 	.word	0x20000094
 800081c:	08003058 	.word	0x08003058

08000820 <Bootloader_jump_to_app>:
  	appJumpAddress = *((volatile uint32_t*)(APP_ADDRESS + 4));
 8000820:	4b03      	ldr	r3, [pc, #12]	; (8000830 <Bootloader_jump_to_app+0x10>)
  	SCB->VTOR = APP_ADDRESS;
 8000822:	4904      	ldr	r1, [pc, #16]	; (8000834 <Bootloader_jump_to_app+0x14>)
  	appJumpAddress = *((volatile uint32_t*)(APP_ADDRESS + 4));
 8000824:	685a      	ldr	r2, [r3, #4]
  	SCB->VTOR = APP_ADDRESS;
 8000826:	608b      	str	r3, [r1, #8]
  	__set_MSP(*((volatile uint32_t*) APP_ADDRESS)); //stack pointer (to RAM) for USER app in this address
 8000828:	681b      	ldr	r3, [r3, #0]
 800082a:	f383 8808 	msr	MSP, r3
  	GoToApp();
 800082e:	4710      	bx	r2
 8000830:	08008000 	.word	0x08008000
 8000834:	e000ed00 	.word	0xe000ed00

08000838 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8000838:	b510      	push	{r4, lr}
 800083a:	b094      	sub	sp, #80	; 0x50
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 800083c:	2238      	movs	r2, #56	; 0x38
 800083e:	2100      	movs	r1, #0
 8000840:	a806      	add	r0, sp, #24
 8000842:	f002 fbf5 	bl	8003030 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8000846:	2400      	movs	r4, #0

  /** Configure the main internal regulator output voltage
  */
  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
 8000848:	f44f 7000 	mov.w	r0, #512	; 0x200
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 800084c:	e9cd 4400 	strd	r4, r4, [sp]
 8000850:	e9cd 4402 	strd	r4, r4, [sp, #8]
 8000854:	9404      	str	r4, [sp, #16]
  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
 8000856:	f000 fe6d 	bl	8001534 <HAL_PWREx_ControlVoltageScaling>

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 800085a:	f44f 7380 	mov.w	r3, #256	; 0x100
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 800085e:	2202      	movs	r2, #2
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8000860:	9309      	str	r3, [sp, #36]	; 0x24
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8000862:	a806      	add	r0, sp, #24
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8000864:	2340      	movs	r3, #64	; 0x40
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8000866:	9206      	str	r2, [sp, #24]
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8000868:	930a      	str	r3, [sp, #40]	; 0x28
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
 800086a:	940d      	str	r4, [sp, #52]	; 0x34
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800086c:	f000 fee8 	bl	8001640 <HAL_RCC_OscConfig>
 8000870:	b108      	cbz	r0, 8000876 <SystemClock_Config+0x3e>
  __ASM volatile ("cpsid i" : : : "memory");
 8000872:	b672      	cpsid	i
void Error_Handler(void)
{
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 8000874:	e7fe      	b.n	8000874 <SystemClock_Config+0x3c>
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8000876:	220f      	movs	r2, #15
 8000878:	2301      	movs	r3, #1
 800087a:	e9cd 2300 	strd	r2, r3, [sp]
 800087e:	4601      	mov	r1, r0
 8000880:	2200      	movs	r2, #0
 8000882:	2300      	movs	r3, #0
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
 8000884:	4668      	mov	r0, sp
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8000886:	e9cd 2302 	strd	r2, r3, [sp, #8]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 800088a:	9104      	str	r1, [sp, #16]
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
 800088c:	f001 f95c 	bl	8001b48 <HAL_RCC_ClockConfig>
 8000890:	b108      	cbz	r0, 8000896 <SystemClock_Config+0x5e>
 8000892:	b672      	cpsid	i
  while (1)
 8000894:	e7fe      	b.n	8000894 <SystemClock_Config+0x5c>
}
 8000896:	b014      	add	sp, #80	; 0x50
 8000898:	bd10      	pop	{r4, pc}
 800089a:	bf00      	nop

0800089c <main>:
{
 800089c:	b500      	push	{lr}
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800089e:	2400      	movs	r4, #0
{
 80008a0:	b08b      	sub	sp, #44	; 0x2c
  HAL_Init();
 80008a2:	f000 f9fd 	bl	8000ca0 <HAL_Init>
  SystemClock_Config();
 80008a6:	f7ff ffc7 	bl	8000838 <SystemClock_Config>
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80008aa:	e9cd 4404 	strd	r4, r4, [sp, #16]
 80008ae:	e9cd 4406 	strd	r4, r4, [sp, #24]
  __HAL_RCC_GPIOC_CLK_ENABLE();
 80008b2:	4b49      	ldr	r3, [pc, #292]	; (80009d8 <main+0x13c>)
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80008b4:	9408      	str	r4, [sp, #32]
  __HAL_RCC_GPIOC_CLK_ENABLE();
 80008b6:	6cd9      	ldr	r1, [r3, #76]	; 0x4c
  HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET);
 80008b8:	4848      	ldr	r0, [pc, #288]	; (80009dc <main+0x140>)
  huart1.Instance = USART1;
 80008ba:	4d49      	ldr	r5, [pc, #292]	; (80009e0 <main+0x144>)
  __HAL_RCC_GPIOC_CLK_ENABLE();
 80008bc:	f041 0104 	orr.w	r1, r1, #4
 80008c0:	64d9      	str	r1, [r3, #76]	; 0x4c
 80008c2:	6cd9      	ldr	r1, [r3, #76]	; 0x4c
 80008c4:	f001 0104 	and.w	r1, r1, #4
 80008c8:	9101      	str	r1, [sp, #4]
 80008ca:	9901      	ldr	r1, [sp, #4]
  __HAL_RCC_GPIOD_CLK_ENABLE();
 80008cc:	6cd9      	ldr	r1, [r3, #76]	; 0x4c
 80008ce:	f041 0108 	orr.w	r1, r1, #8
 80008d2:	64d9      	str	r1, [r3, #76]	; 0x4c
 80008d4:	6cd9      	ldr	r1, [r3, #76]	; 0x4c
 80008d6:	f001 0108 	and.w	r1, r1, #8
 80008da:	9102      	str	r1, [sp, #8]
 80008dc:	9902      	ldr	r1, [sp, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 80008de:	6cd9      	ldr	r1, [r3, #76]	; 0x4c
 80008e0:	f041 0102 	orr.w	r1, r1, #2
 80008e4:	64d9      	str	r1, [r3, #76]	; 0x4c
 80008e6:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80008e8:	f003 0302 	and.w	r3, r3, #2
  HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET);
 80008ec:	4622      	mov	r2, r4
  __HAL_RCC_GPIOB_CLK_ENABLE();
 80008ee:	9303      	str	r3, [sp, #12]
  HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET);
 80008f0:	f44f 5100 	mov.w	r1, #8192	; 0x2000
  __HAL_RCC_GPIOB_CLK_ENABLE();
 80008f4:	9b03      	ldr	r3, [sp, #12]
  HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET);
 80008f6:	f000 fe0d 	bl	8001514 <HAL_GPIO_WritePin>
  GPIO_InitStruct.Pin = LED_Pin;
 80008fa:	f44f 5200 	mov.w	r2, #8192	; 0x2000
 80008fe:	2301      	movs	r3, #1
 8000900:	e9cd 2304 	strd	r2, r3, [sp, #16]
  HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
 8000904:	4835      	ldr	r0, [pc, #212]	; (80009dc <main+0x140>)
  GPIO_InitStruct.Pin = LED_Pin;
 8000906:	2200      	movs	r2, #0
 8000908:	2300      	movs	r3, #0
  HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
 800090a:	a904      	add	r1, sp, #16
  GPIO_InitStruct.Pin = LED_Pin;
 800090c:	e9cd 2306 	strd	r2, r3, [sp, #24]
  HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
 8000910:	f000 fc56 	bl	80011c0 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = KEY_Pin;
 8000914:	2204      	movs	r2, #4
 8000916:	2300      	movs	r3, #0
 8000918:	e9cd 2304 	strd	r2, r3, [sp, #16]
  HAL_GPIO_Init(KEY_GPIO_Port, &GPIO_InitStruct);
 800091c:	4831      	ldr	r0, [pc, #196]	; (80009e4 <main+0x148>)
  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
 800091e:	2302      	movs	r3, #2
  HAL_GPIO_Init(KEY_GPIO_Port, &GPIO_InitStruct);
 8000920:	a904      	add	r1, sp, #16
  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
 8000922:	9306      	str	r3, [sp, #24]
  HAL_GPIO_Init(KEY_GPIO_Port, &GPIO_InitStruct);
 8000924:	f000 fc4c 	bl	80011c0 <HAL_GPIO_Init>
  huart1.Init.BaudRate = 115200;
 8000928:	4a2f      	ldr	r2, [pc, #188]	; (80009e8 <main+0x14c>)
  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 800092a:	62ac      	str	r4, [r5, #40]	; 0x28
  huart1.Init.BaudRate = 115200;
 800092c:	f44f 33e1 	mov.w	r3, #115200	; 0x1c200
 8000930:	e9c5 2300 	strd	r2, r3, [r5]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8000934:	4628      	mov	r0, r5
  huart1.Init.Mode = UART_MODE_TX_RX;
 8000936:	230c      	movs	r3, #12
  huart1.Init.StopBits = UART_STOPBITS_1;
 8000938:	e9c5 4402 	strd	r4, r4, [r5, #8]
  huart1.Init.Mode = UART_MODE_TX_RX;
 800093c:	e9c5 4304 	strd	r4, r3, [r5, #16]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8000940:	e9c5 4406 	strd	r4, r4, [r5, #24]
  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
 8000944:	e9c5 4408 	strd	r4, r4, [r5, #32]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8000948:	f002 fa78 	bl	8002e3c <HAL_UART_Init>
 800094c:	b108      	cbz	r0, 8000952 <main+0xb6>
 800094e:	b672      	cpsid	i
  while (1)
 8000950:	e7fe      	b.n	8000950 <main+0xb4>
  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
 8000952:	4601      	mov	r1, r0
 8000954:	4628      	mov	r0, r5
 8000956:	f002 fac3 	bl	8002ee0 <HAL_UARTEx_SetTxFifoThreshold>
 800095a:	b108      	cbz	r0, 8000960 <main+0xc4>
 800095c:	b672      	cpsid	i
  while (1)
 800095e:	e7fe      	b.n	800095e <main+0xc2>
  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
 8000960:	4601      	mov	r1, r0
 8000962:	4628      	mov	r0, r5
 8000964:	f002 fafe 	bl	8002f64 <HAL_UARTEx_SetRxFifoThreshold>
 8000968:	b108      	cbz	r0, 800096e <main+0xd2>
 800096a:	b672      	cpsid	i
  while (1)
 800096c:	e7fe      	b.n	800096c <main+0xd0>
  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
 800096e:	4628      	mov	r0, r5
 8000970:	f002 fa98 	bl	8002ea4 <HAL_UARTEx_DisableFifoMode>
 8000974:	4603      	mov	r3, r0
 8000976:	b108      	cbz	r0, 800097c <main+0xe0>
 8000978:	b672      	cpsid	i
  while (1)
 800097a:	e7fe      	b.n	800097a <main+0xde>
  htim6.Instance = TIM6;
 800097c:	4c1b      	ldr	r4, [pc, #108]	; (80009ec <main+0x150>)
 800097e:	491c      	ldr	r1, [pc, #112]	; (80009f0 <main+0x154>)
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8000980:	9006      	str	r0, [sp, #24]
  htim6.Init.Prescaler = 160-1;
 8000982:	229f      	movs	r2, #159	; 0x9f
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8000984:	e9cd 0004 	strd	r0, r0, [sp, #16]
  htim6.Init.Prescaler = 160-1;
 8000988:	e9c4 1200 	strd	r1, r2, [r4]
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 800098c:	4620      	mov	r0, r4
  htim6.Init.Period = 10000;
 800098e:	f242 7210 	movw	r2, #10000	; 0x2710
 8000992:	e9c4 3202 	strd	r3, r2, [r4, #8]
  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8000996:	61a3      	str	r3, [r4, #24]
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8000998:	f001 fb58 	bl	800204c <HAL_TIM_Base_Init>
 800099c:	4603      	mov	r3, r0
 800099e:	b108      	cbz	r0, 80009a4 <main+0x108>
 80009a0:	b672      	cpsid	i
  while (1)
 80009a2:	e7fe      	b.n	80009a2 <main+0x106>
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 80009a4:	a904      	add	r1, sp, #16
 80009a6:	4620      	mov	r0, r4
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 80009a8:	9304      	str	r3, [sp, #16]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 80009aa:	9306      	str	r3, [sp, #24]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 80009ac:	f001 fd60 	bl	8002470 <HAL_TIMEx_MasterConfigSynchronization>
 80009b0:	b108      	cbz	r0, 80009b6 <main+0x11a>
 80009b2:	b672      	cpsid	i
  while (1)
 80009b4:	e7fe      	b.n	80009b4 <main+0x118>
  HAL_TIM_Base_Start_IT(&htim6);
 80009b6:	4620      	mov	r0, r4
 80009b8:	f001 fc34 	bl	8002224 <HAL_TIM_Base_Start_IT>
  if (Bootloader_flag() == 1) {
 80009bc:	f7ff fdd8 	bl	8000570 <Bootloader_flag>
 80009c0:	2801      	cmp	r0, #1
 80009c2:	d004      	beq.n	80009ce <main+0x132>
  Bootloader_Deinit_All();
 80009c4:	f7ff fdaa 	bl	800051c <Bootloader_Deinit_All>
  Bootloader_jump_to_app();
 80009c8:	f7ff ff2a 	bl	8000820 <Bootloader_jump_to_app>
  while (1)
 80009cc:	e7fe      	b.n	80009cc <main+0x130>
	Bootloader_flag_reset();
 80009ce:	f7ff fde5 	bl	800059c <Bootloader_flag_reset>
	Bootloader_cmd();
 80009d2:	f7ff fde9 	bl	80005a8 <Bootloader_cmd>
 80009d6:	e7f5      	b.n	80009c4 <main+0x128>
 80009d8:	40021000 	.word	0x40021000
 80009dc:	48000800 	.word	0x48000800
 80009e0:	20000094 	.word	0x20000094
 80009e4:	48000c00 	.word	0x48000c00
 80009e8:	40013800 	.word	0x40013800
 80009ec:	20000048 	.word	0x20000048
 80009f0:	40001000 	.word	0x40001000

080009f4 <Error_Handler>:
 80009f4:	b672      	cpsid	i
  while (1)
 80009f6:	e7fe      	b.n	80009f6 <Error_Handler+0x2>

080009f8 <HAL_MspInit>:

  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 80009f8:	4b0b      	ldr	r3, [pc, #44]	; (8000a28 <HAL_MspInit+0x30>)
 80009fa:	6e1a      	ldr	r2, [r3, #96]	; 0x60
 80009fc:	f042 0201 	orr.w	r2, r2, #1
 8000a00:	661a      	str	r2, [r3, #96]	; 0x60
 8000a02:	6e1a      	ldr	r2, [r3, #96]	; 0x60
{
 8000a04:	b082      	sub	sp, #8
  __HAL_RCC_SYSCFG_CLK_ENABLE();
 8000a06:	f002 0201 	and.w	r2, r2, #1
 8000a0a:	9200      	str	r2, [sp, #0]
 8000a0c:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_PWR_CLK_ENABLE();
 8000a0e:	6d9a      	ldr	r2, [r3, #88]	; 0x58
 8000a10:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
 8000a14:	659a      	str	r2, [r3, #88]	; 0x58
 8000a16:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8000a18:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000a1c:	9301      	str	r3, [sp, #4]
 8000a1e:	9b01      	ldr	r3, [sp, #4]
  HAL_PWREx_DisableUCPDDeadBattery();

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8000a20:	b002      	add	sp, #8
  HAL_PWREx_DisableUCPDDeadBattery();
 8000a22:	f000 be05 	b.w	8001630 <HAL_PWREx_DisableUCPDDeadBattery>
 8000a26:	bf00      	nop
 8000a28:	40021000 	.word	0x40021000

08000a2c <HAL_TIM_Base_MspInit>:
  * @param htim_base: TIM_Base handle pointer
  * @retval None
  */
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
  if(htim_base->Instance==TIM6)
 8000a2c:	4b0e      	ldr	r3, [pc, #56]	; (8000a68 <HAL_TIM_Base_MspInit+0x3c>)
 8000a2e:	6802      	ldr	r2, [r0, #0]
 8000a30:	429a      	cmp	r2, r3
 8000a32:	d000      	beq.n	8000a36 <HAL_TIM_Base_MspInit+0xa>
 8000a34:	4770      	bx	lr
  {
    /* USER CODE BEGIN TIM6_MspInit 0 */

    /* USER CODE END TIM6_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM6_CLK_ENABLE();
 8000a36:	f503 3300 	add.w	r3, r3, #131072	; 0x20000
{
 8000a3a:	b500      	push	{lr}
    __HAL_RCC_TIM6_CLK_ENABLE();
 8000a3c:	6d99      	ldr	r1, [r3, #88]	; 0x58
 8000a3e:	f041 0110 	orr.w	r1, r1, #16
 8000a42:	6599      	str	r1, [r3, #88]	; 0x58
 8000a44:	6d9b      	ldr	r3, [r3, #88]	; 0x58
{
 8000a46:	b083      	sub	sp, #12
    /* TIM6 interrupt Init */
    HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
 8000a48:	2200      	movs	r2, #0
    __HAL_RCC_TIM6_CLK_ENABLE();
 8000a4a:	f003 0310 	and.w	r3, r3, #16
 8000a4e:	9301      	str	r3, [sp, #4]
    HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
 8000a50:	2036      	movs	r0, #54	; 0x36
 8000a52:	4611      	mov	r1, r2
    __HAL_RCC_TIM6_CLK_ENABLE();
 8000a54:	9b01      	ldr	r3, [sp, #4]
    HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
 8000a56:	f000 f957 	bl	8000d08 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
 8000a5a:	2036      	movs	r0, #54	; 0x36

    /* USER CODE END TIM6_MspInit 1 */

  }

}
 8000a5c:	b003      	add	sp, #12
 8000a5e:	f85d eb04 	ldr.w	lr, [sp], #4
    HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
 8000a62:	f000 b98f 	b.w	8000d84 <HAL_NVIC_EnableIRQ>
 8000a66:	bf00      	nop
 8000a68:	40001000 	.word	0x40001000

08000a6c <HAL_TIM_Base_MspDeInit>:
  * @param htim_base: TIM_Base handle pointer
  * @retval None
  */
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
{
  if(htim_base->Instance==TIM6)
 8000a6c:	4b06      	ldr	r3, [pc, #24]	; (8000a88 <HAL_TIM_Base_MspDeInit+0x1c>)
 8000a6e:	6802      	ldr	r2, [r0, #0]
 8000a70:	429a      	cmp	r2, r3
 8000a72:	d000      	beq.n	8000a76 <HAL_TIM_Base_MspDeInit+0xa>
    /* USER CODE BEGIN TIM6_MspDeInit 1 */

    /* USER CODE END TIM6_MspDeInit 1 */
  }

}
 8000a74:	4770      	bx	lr
    __HAL_RCC_TIM6_CLK_DISABLE();
 8000a76:	4a05      	ldr	r2, [pc, #20]	; (8000a8c <HAL_TIM_Base_MspDeInit+0x20>)
 8000a78:	6d93      	ldr	r3, [r2, #88]	; 0x58
 8000a7a:	f023 0310 	bic.w	r3, r3, #16
    HAL_NVIC_DisableIRQ(TIM6_DAC_IRQn);
 8000a7e:	2036      	movs	r0, #54	; 0x36
    __HAL_RCC_TIM6_CLK_DISABLE();
 8000a80:	6593      	str	r3, [r2, #88]	; 0x58
    HAL_NVIC_DisableIRQ(TIM6_DAC_IRQn);
 8000a82:	f000 b98d 	b.w	8000da0 <HAL_NVIC_DisableIRQ>
 8000a86:	bf00      	nop
 8000a88:	40001000 	.word	0x40001000
 8000a8c:	40021000 	.word	0x40021000

08000a90 <HAL_UART_MspInit>:
  * This function configures the hardware resources used in this example
  * @param huart: UART handle pointer
  * @retval None
  */
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8000a90:	b510      	push	{r4, lr}
 8000a92:	4604      	mov	r4, r0
 8000a94:	b098      	sub	sp, #96	; 0x60
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000a96:	2100      	movs	r1, #0
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8000a98:	2244      	movs	r2, #68	; 0x44
 8000a9a:	a807      	add	r0, sp, #28
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000a9c:	e9cd 1102 	strd	r1, r1, [sp, #8]
 8000aa0:	e9cd 1104 	strd	r1, r1, [sp, #16]
 8000aa4:	9106      	str	r1, [sp, #24]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8000aa6:	f002 fac3 	bl	8003030 <memset>
  if(huart->Instance==USART1)
 8000aaa:	4b1d      	ldr	r3, [pc, #116]	; (8000b20 <HAL_UART_MspInit+0x90>)
 8000aac:	6822      	ldr	r2, [r4, #0]
 8000aae:	429a      	cmp	r2, r3
 8000ab0:	d001      	beq.n	8000ab6 <HAL_UART_MspInit+0x26>

    /* USER CODE END USART1_MspInit 1 */

  }

}
 8000ab2:	b018      	add	sp, #96	; 0x60
 8000ab4:	bd10      	pop	{r4, pc}
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
 8000ab6:	2301      	movs	r3, #1
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8000ab8:	a807      	add	r0, sp, #28
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
 8000aba:	9307      	str	r3, [sp, #28]
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8000abc:	f001 f97a 	bl	8001db4 <HAL_RCCEx_PeriphCLKConfig>
 8000ac0:	bb10      	cbnz	r0, 8000b08 <HAL_UART_MspInit+0x78>
    __HAL_RCC_USART1_CLK_ENABLE();
 8000ac2:	4b18      	ldr	r3, [pc, #96]	; (8000b24 <HAL_UART_MspInit+0x94>)
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8000ac4:	4818      	ldr	r0, [pc, #96]	; (8000b28 <HAL_UART_MspInit+0x98>)
    __HAL_RCC_USART1_CLK_ENABLE();
 8000ac6:	6e1a      	ldr	r2, [r3, #96]	; 0x60
 8000ac8:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
 8000acc:	661a      	str	r2, [r3, #96]	; 0x60
 8000ace:	6e1a      	ldr	r2, [r3, #96]	; 0x60
 8000ad0:	f402 4280 	and.w	r2, r2, #16384	; 0x4000
 8000ad4:	9200      	str	r2, [sp, #0]
 8000ad6:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8000ad8:	6cda      	ldr	r2, [r3, #76]	; 0x4c
    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
 8000ada:	ed9f 7b0d 	vldr	d7, [pc, #52]	; 8000b10 <HAL_UART_MspInit+0x80>
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8000ade:	f042 0202 	orr.w	r2, r2, #2
 8000ae2:	64da      	str	r2, [r3, #76]	; 0x4c
 8000ae4:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
 8000ae6:	ed8d 7b02 	vstr	d7, [sp, #8]
 8000aea:	ed9f 7b0b 	vldr	d7, [pc, #44]	; 8000b18 <HAL_UART_MspInit+0x88>
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8000aee:	f003 0302 	and.w	r3, r3, #2
 8000af2:	9301      	str	r3, [sp, #4]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8000af4:	a902      	add	r1, sp, #8
    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
 8000af6:	2307      	movs	r3, #7
    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
 8000af8:	ed8d 7b04 	vstr	d7, [sp, #16]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8000afc:	9a01      	ldr	r2, [sp, #4]
    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
 8000afe:	9306      	str	r3, [sp, #24]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8000b00:	f000 fb5e 	bl	80011c0 <HAL_GPIO_Init>
}
 8000b04:	b018      	add	sp, #96	; 0x60
 8000b06:	bd10      	pop	{r4, pc}
      Error_Handler();
 8000b08:	f7ff ff74 	bl	80009f4 <Error_Handler>
 8000b0c:	e7d9      	b.n	8000ac2 <HAL_UART_MspInit+0x32>
 8000b0e:	bf00      	nop
 8000b10:	000000c0 	.word	0x000000c0
 8000b14:	00000002 	.word	0x00000002
	...
 8000b20:	40013800 	.word	0x40013800
 8000b24:	40021000 	.word	0x40021000
 8000b28:	48000400 	.word	0x48000400

08000b2c <HAL_UART_MspDeInit>:
  * @param huart: UART handle pointer
  * @retval None
  */
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
  if(huart->Instance==USART1)
 8000b2c:	4b06      	ldr	r3, [pc, #24]	; (8000b48 <HAL_UART_MspDeInit+0x1c>)
 8000b2e:	6802      	ldr	r2, [r0, #0]
 8000b30:	429a      	cmp	r2, r3
 8000b32:	d000      	beq.n	8000b36 <HAL_UART_MspDeInit+0xa>
    /* USER CODE BEGIN USART1_MspDeInit 1 */

    /* USER CODE END USART1_MspDeInit 1 */
  }

}
 8000b34:	4770      	bx	lr
    __HAL_RCC_USART1_CLK_DISABLE();
 8000b36:	4a05      	ldr	r2, [pc, #20]	; (8000b4c <HAL_UART_MspDeInit+0x20>)
    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
 8000b38:	4805      	ldr	r0, [pc, #20]	; (8000b50 <HAL_UART_MspDeInit+0x24>)
    __HAL_RCC_USART1_CLK_DISABLE();
 8000b3a:	6e13      	ldr	r3, [r2, #96]	; 0x60
 8000b3c:	f423 4380 	bic.w	r3, r3, #16384	; 0x4000
    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
 8000b40:	21c0      	movs	r1, #192	; 0xc0
    __HAL_RCC_USART1_CLK_DISABLE();
 8000b42:	6613      	str	r3, [r2, #96]	; 0x60
    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
 8000b44:	f000 bc4e 	b.w	80013e4 <HAL_GPIO_DeInit>
 8000b48:	40013800 	.word	0x40013800
 8000b4c:	40021000 	.word	0x40021000
 8000b50:	48000400 	.word	0x48000400

08000b54 <NMI_Handler>:
{
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
   while (1)
 8000b54:	e7fe      	b.n	8000b54 <NMI_Handler>
 8000b56:	bf00      	nop

08000b58 <HardFault_Handler>:
void HardFault_Handler(void)
{
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8000b58:	e7fe      	b.n	8000b58 <HardFault_Handler>
 8000b5a:	bf00      	nop

08000b5c <MemManage_Handler>:
void MemManage_Handler(void)
{
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8000b5c:	e7fe      	b.n	8000b5c <MemManage_Handler>
 8000b5e:	bf00      	nop

08000b60 <BusFault_Handler>:
void BusFault_Handler(void)
{
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8000b60:	e7fe      	b.n	8000b60 <BusFault_Handler>
 8000b62:	bf00      	nop

08000b64 <UsageFault_Handler>:
void UsageFault_Handler(void)
{
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8000b64:	e7fe      	b.n	8000b64 <UsageFault_Handler>
 8000b66:	bf00      	nop

08000b68 <SVC_Handler>:

  /* USER CODE END SVCall_IRQn 0 */
  /* USER CODE BEGIN SVCall_IRQn 1 */

  /* USER CODE END SVCall_IRQn 1 */
}
 8000b68:	4770      	bx	lr
 8000b6a:	bf00      	nop

08000b6c <DebugMon_Handler>:
 8000b6c:	4770      	bx	lr
 8000b6e:	bf00      	nop

08000b70 <PendSV_Handler>:
 8000b70:	4770      	bx	lr
 8000b72:	bf00      	nop

08000b74 <SysTick_Handler>:
void SysTick_Handler(void)
{
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8000b74:	f000 b8a4 	b.w	8000cc0 <HAL_IncTick>

08000b78 <TIM6_DAC_IRQHandler>:

/**
  * @brief This function handles TIM6 global interrupt, DAC1 and DAC3 channel underrun error interrupts.
  */
void TIM6_DAC_IRQHandler(void)
{
 8000b78:	b508      	push	{r3, lr}
  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
	HAL_GPIO_TogglePin(LED_GPIO_Port, LED_Pin);
 8000b7a:	4805      	ldr	r0, [pc, #20]	; (8000b90 <TIM6_DAC_IRQHandler+0x18>)
 8000b7c:	f44f 5100 	mov.w	r1, #8192	; 0x2000
 8000b80:	f000 fcce 	bl	8001520 <HAL_GPIO_TogglePin>
  /* USER CODE END TIM6_DAC_IRQn 0 */
  HAL_TIM_IRQHandler(&htim6);
  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */

  /* USER CODE END TIM6_DAC_IRQn 1 */
}
 8000b84:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
  HAL_TIM_IRQHandler(&htim6);
 8000b88:	4802      	ldr	r0, [pc, #8]	; (8000b94 <TIM6_DAC_IRQHandler+0x1c>)
 8000b8a:	f001 bb8f 	b.w	80022ac <HAL_TIM_IRQHandler>
 8000b8e:	bf00      	nop
 8000b90:	48000800 	.word	0x48000800
 8000b94:	20000048 	.word	0x20000048

08000b98 <SystemInit>:

void SystemInit(void)
{
  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
 8000b98:	4a03      	ldr	r2, [pc, #12]	; (8000ba8 <SystemInit+0x10>)
 8000b9a:	f8d2 3088 	ldr.w	r3, [r2, #136]	; 0x88
 8000b9e:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
 8000ba2:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88

  /* Configure the Vector Table location add offset address ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
 8000ba6:	4770      	bx	lr
 8000ba8:	e000ed00 	.word	0xe000ed00

08000bac <xtea_decrypt>:
        v1 += (((v0<<4) ^ (v0>>5)) + v0) ^ (sum + k[(sum>>11) & 3]);
    }
    v[0]=v0; v[1]=v1;
}

void xtea_decrypt(uint32_t v[2], const uint32_t k[4]) {
 8000bac:	b470      	push	{r4, r5, r6}
    uint32_t v0=v[0], v1=v[1], delta=0x9E3779B9, sum=delta*32;
 8000bae:	e9d0 5400 	ldrd	r5, r4, [r0]
 8000bb2:	4b11      	ldr	r3, [pc, #68]	; (8000bf8 <xtea_decrypt+0x4c>)
    for (uint8_t i=0;i<32;i++) {
        v1 -= (((v0<<4) ^ (v0>>5)) + v0) ^ (sum + k[(sum>>11) & 3]);
        sum -= delta;
 8000bb4:	4e11      	ldr	r6, [pc, #68]	; (8000bfc <xtea_decrypt+0x50>)
        v1 -= (((v0<<4) ^ (v0>>5)) + v0) ^ (sum + k[(sum>>11) & 3]);
 8000bb6:	f3c3 22c1 	ubfx	r2, r3, #11, #2
 8000bba:	ea4f 1c55 	mov.w	ip, r5, lsr #5
 8000bbe:	f851 2022 	ldr.w	r2, [r1, r2, lsl #2]
 8000bc2:	ea8c 1c05 	eor.w	ip, ip, r5, lsl #4
 8000bc6:	44ac      	add	ip, r5
 8000bc8:	441a      	add	r2, r3
        sum -= delta;
 8000bca:	4433      	add	r3, r6
        v1 -= (((v0<<4) ^ (v0>>5)) + v0) ^ (sum + k[(sum>>11) & 3]);
 8000bcc:	ea82 020c 	eor.w	r2, r2, ip
        v0 -= (((v1<<4) ^ (v1>>5)) + v1) ^ (sum + k[sum & 3]);
 8000bd0:	f003 0c03 	and.w	ip, r3, #3
        v1 -= (((v0<<4) ^ (v0>>5)) + v0) ^ (sum + k[(sum>>11) & 3]);
 8000bd4:	1aa4      	subs	r4, r4, r2
        v0 -= (((v1<<4) ^ (v1>>5)) + v1) ^ (sum + k[sum & 3]);
 8000bd6:	f851 202c 	ldr.w	r2, [r1, ip, lsl #2]
 8000bda:	ea4f 1c54 	mov.w	ip, r4, lsr #5
 8000bde:	ea8c 1c04 	eor.w	ip, ip, r4, lsl #4
 8000be2:	441a      	add	r2, r3
 8000be4:	44a4      	add	ip, r4
 8000be6:	ea82 020c 	eor.w	r2, r2, ip
 8000bea:	1aad      	subs	r5, r5, r2
    for (uint8_t i=0;i<32;i++) {
 8000bec:	2b00      	cmp	r3, #0
 8000bee:	d1e2      	bne.n	8000bb6 <xtea_decrypt+0xa>
    }
    v[0]=v0; v[1]=v1;
 8000bf0:	e9c0 5400 	strd	r5, r4, [r0]
}
 8000bf4:	bc70      	pop	{r4, r5, r6}
 8000bf6:	4770      	bx	lr
 8000bf8:	c6ef3720 	.word	0xc6ef3720
 8000bfc:	61c88647 	.word	0x61c88647

08000c00 <Reset_Handler>:

    .section	.text.Reset_Handler
	.weak	Reset_Handler
	.type	Reset_Handler, %function
Reset_Handler:
  ldr   r0, =_estack
 8000c00:	480d      	ldr	r0, [pc, #52]	; (8000c38 <LoopForever+0x2>)
  mov   sp, r0          /* set stack pointer */
 8000c02:	4685      	mov	sp, r0
  
/* Call the clock system initialization function.*/
    bl  SystemInit
 8000c04:	f7ff ffc8 	bl	8000b98 <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 8000c08:	480c      	ldr	r0, [pc, #48]	; (8000c3c <LoopForever+0x6>)
  ldr r1, =_edata
 8000c0a:	490d      	ldr	r1, [pc, #52]	; (8000c40 <LoopForever+0xa>)
  ldr r2, =_sidata
 8000c0c:	4a0d      	ldr	r2, [pc, #52]	; (8000c44 <LoopForever+0xe>)
  movs r3, #0
 8000c0e:	2300      	movs	r3, #0
  b	LoopCopyDataInit
 8000c10:	e002      	b.n	8000c18 <LoopCopyDataInit>

08000c12 <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 8000c12:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 8000c14:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 8000c16:	3304      	adds	r3, #4

08000c18 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8000c18:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8000c1a:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8000c1c:	d3f9      	bcc.n	8000c12 <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 8000c1e:	4a0a      	ldr	r2, [pc, #40]	; (8000c48 <LoopForever+0x12>)
  ldr r4, =_ebss
 8000c20:	4c0a      	ldr	r4, [pc, #40]	; (8000c4c <LoopForever+0x16>)
  movs r3, #0
 8000c22:	2300      	movs	r3, #0
  b LoopFillZerobss
 8000c24:	e001      	b.n	8000c2a <LoopFillZerobss>

08000c26 <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 8000c26:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8000c28:	3204      	adds	r2, #4

08000c2a <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8000c2a:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8000c2c:	d3fb      	bcc.n	8000c26 <FillZerobss>
/* Call static constructors */
    bl __libc_init_array
 8000c2e:	f002 f9db 	bl	8002fe8 <__libc_init_array>
/* Call the application's entry point.*/
	bl	main
 8000c32:	f7ff fe33 	bl	800089c <main>

08000c36 <LoopForever>:

LoopForever:
    b LoopForever
 8000c36:	e7fe      	b.n	8000c36 <LoopForever>
  ldr   r0, =_estack
 8000c38:	20007f80 	.word	0x20007f80
  ldr r0, =_sdata
 8000c3c:	20000000 	.word	0x20000000
  ldr r1, =_edata
 8000c40:	2000002c 	.word	0x2000002c
  ldr r2, =_sidata
 8000c44:	080030cc 	.word	0x080030cc
  ldr r2, =_sbss
 8000c48:	2000002c 	.word	0x2000002c
  ldr r4, =_ebss
 8000c4c:	2000012c 	.word	0x2000012c

08000c50 <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section	.text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
	b	Infinite_Loop
 8000c50:	e7fe      	b.n	8000c50 <ADC1_2_IRQHandler>
	...

08000c54 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority: Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8000c54:	b538      	push	{r3, r4, r5, lr}
  HAL_StatusTypeDef  status = HAL_OK;

  if (uwTickFreq != 0U)
 8000c56:	4b0f      	ldr	r3, [pc, #60]	; (8000c94 <HAL_InitTick+0x40>)
 8000c58:	681b      	ldr	r3, [r3, #0]
 8000c5a:	b90b      	cbnz	r3, 8000c60 <HAL_InitTick+0xc>
      status = HAL_ERROR;
    }
  }
  else
  {
    status = HAL_ERROR;
 8000c5c:	2001      	movs	r0, #1
  }

  /* Return function status */
  return status;
}
 8000c5e:	bd38      	pop	{r3, r4, r5, pc}
    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
 8000c60:	490d      	ldr	r1, [pc, #52]	; (8000c98 <HAL_InitTick+0x44>)
 8000c62:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
 8000c66:	4605      	mov	r5, r0
 8000c68:	fbb2 f3f3 	udiv	r3, r2, r3
 8000c6c:	6808      	ldr	r0, [r1, #0]
 8000c6e:	fbb0 f0f3 	udiv	r0, r0, r3
 8000c72:	f000 f8a9 	bl	8000dc8 <HAL_SYSTICK_Config>
 8000c76:	4604      	mov	r4, r0
 8000c78:	2800      	cmp	r0, #0
 8000c7a:	d1ef      	bne.n	8000c5c <HAL_InitTick+0x8>
      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8000c7c:	2d0f      	cmp	r5, #15
 8000c7e:	d8ed      	bhi.n	8000c5c <HAL_InitTick+0x8>
        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8000c80:	4602      	mov	r2, r0
 8000c82:	4629      	mov	r1, r5
 8000c84:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8000c88:	f000 f83e 	bl	8000d08 <HAL_NVIC_SetPriority>
        uwTickPrio = TickPriority;
 8000c8c:	4b03      	ldr	r3, [pc, #12]	; (8000c9c <HAL_InitTick+0x48>)
 8000c8e:	4620      	mov	r0, r4
 8000c90:	601d      	str	r5, [r3, #0]
}
 8000c92:	bd38      	pop	{r3, r4, r5, pc}
 8000c94:	20000004 	.word	0x20000004
 8000c98:	20000000 	.word	0x20000000
 8000c9c:	20000008 	.word	0x20000008

08000ca0 <HAL_Init>:
{
 8000ca0:	b510      	push	{r4, lr}
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8000ca2:	2003      	movs	r0, #3
 8000ca4:	f000 f81e 	bl	8000ce4 <HAL_NVIC_SetPriorityGrouping>
  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 8000ca8:	200f      	movs	r0, #15
 8000caa:	f7ff ffd3 	bl	8000c54 <HAL_InitTick>
 8000cae:	b110      	cbz	r0, 8000cb6 <HAL_Init+0x16>
    status = HAL_ERROR;
 8000cb0:	2401      	movs	r4, #1
}
 8000cb2:	4620      	mov	r0, r4
 8000cb4:	bd10      	pop	{r4, pc}
 8000cb6:	4604      	mov	r4, r0
    HAL_MspInit();
 8000cb8:	f7ff fe9e 	bl	80009f8 <HAL_MspInit>
}
 8000cbc:	4620      	mov	r0, r4
 8000cbe:	bd10      	pop	{r4, pc}

08000cc0 <HAL_IncTick>:
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
  uwTick += uwTickFreq;
 8000cc0:	4a03      	ldr	r2, [pc, #12]	; (8000cd0 <HAL_IncTick+0x10>)
 8000cc2:	4904      	ldr	r1, [pc, #16]	; (8000cd4 <HAL_IncTick+0x14>)
 8000cc4:	6813      	ldr	r3, [r2, #0]
 8000cc6:	6809      	ldr	r1, [r1, #0]
 8000cc8:	440b      	add	r3, r1
 8000cca:	6013      	str	r3, [r2, #0]
}
 8000ccc:	4770      	bx	lr
 8000cce:	bf00      	nop
 8000cd0:	20000128 	.word	0x20000128
 8000cd4:	20000004 	.word	0x20000004

08000cd8 <HAL_GetTick>:
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
  return uwTick;
 8000cd8:	4b01      	ldr	r3, [pc, #4]	; (8000ce0 <HAL_GetTick+0x8>)
 8000cda:	6818      	ldr	r0, [r3, #0]
}
 8000cdc:	4770      	bx	lr
 8000cde:	bf00      	nop
 8000ce0:	20000128 	.word	0x20000128

08000ce4 <HAL_NVIC_SetPriorityGrouping>:
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8000ce4:	4907      	ldr	r1, [pc, #28]	; (8000d04 <HAL_NVIC_SetPriorityGrouping+0x20>)
 8000ce6:	68ca      	ldr	r2, [r1, #12]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 8000ce8:	0203      	lsls	r3, r0, #8
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8000cea:	f64f 00ff 	movw	r0, #63743	; 0xf8ff
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 8000cee:	f403 63e0 	and.w	r3, r3, #1792	; 0x700
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8000cf2:	4002      	ands	r2, r0
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 8000cf4:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 8000cf6:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 8000cfa:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
  SCB->AIRCR =  reg_value;
 8000cfe:	60cb      	str	r3, [r1, #12]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));

  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
}
 8000d00:	4770      	bx	lr
 8000d02:	bf00      	nop
 8000d04:	e000ed00 	.word	0xe000ed00

08000d08 <HAL_NVIC_SetPriority>:
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8000d08:	4b1c      	ldr	r3, [pc, #112]	; (8000d7c <HAL_NVIC_SetPriority+0x74>)
 8000d0a:	68db      	ldr	r3, [r3, #12]
 8000d0c:	f3c3 2302 	ubfx	r3, r3, #8, #3
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8000d10:	b500      	push	{lr}
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8000d12:	f1c3 0e07 	rsb	lr, r3, #7
 8000d16:	f1be 0f04 	cmp.w	lr, #4
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000d1a:	f103 0c04 	add.w	ip, r3, #4
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8000d1e:	bf28      	it	cs
 8000d20:	f04f 0e04 	movcs.w	lr, #4
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000d24:	f1bc 0f06 	cmp.w	ip, #6
 8000d28:	d91b      	bls.n	8000d62 <HAL_NVIC_SetPriority+0x5a>
 8000d2a:	3b03      	subs	r3, #3

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8000d2c:	f04f 3cff 	mov.w	ip, #4294967295	; 0xffffffff
 8000d30:	fa0c fc03 	lsl.w	ip, ip, r3
 8000d34:	ea22 020c 	bic.w	r2, r2, ip
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000d38:	f04f 3cff 	mov.w	ip, #4294967295	; 0xffffffff
 8000d3c:	fa0c fc0e 	lsl.w	ip, ip, lr
 8000d40:	ea21 010c 	bic.w	r1, r1, ip
 8000d44:	4099      	lsls	r1, r3
  if ((int32_t)(IRQn) >= 0)
 8000d46:	2800      	cmp	r0, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000d48:	ea41 0102 	orr.w	r1, r1, r2
  if ((int32_t)(IRQn) >= 0)
 8000d4c:	db0c      	blt.n	8000d68 <HAL_NVIC_SetPriority+0x60>
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000d4e:	f100 4060 	add.w	r0, r0, #3758096384	; 0xe0000000
 8000d52:	0109      	lsls	r1, r1, #4
 8000d54:	f500 4061 	add.w	r0, r0, #57600	; 0xe100
 8000d58:	b2c9      	uxtb	r1, r1
 8000d5a:	f880 1300 	strb.w	r1, [r0, #768]	; 0x300
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));

  prioritygroup = NVIC_GetPriorityGrouping();

  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
 8000d5e:	f85d fb04 	ldr.w	pc, [sp], #4
 8000d62:	2200      	movs	r2, #0
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000d64:	4613      	mov	r3, r2
 8000d66:	e7e7      	b.n	8000d38 <HAL_NVIC_SetPriority+0x30>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000d68:	4b05      	ldr	r3, [pc, #20]	; (8000d80 <HAL_NVIC_SetPriority+0x78>)
 8000d6a:	f000 000f 	and.w	r0, r0, #15
 8000d6e:	0109      	lsls	r1, r1, #4
 8000d70:	4403      	add	r3, r0
 8000d72:	b2c9      	uxtb	r1, r1
 8000d74:	7619      	strb	r1, [r3, #24]
 8000d76:	f85d fb04 	ldr.w	pc, [sp], #4
 8000d7a:	bf00      	nop
 8000d7c:	e000ed00 	.word	0xe000ed00
 8000d80:	e000ecfc 	.word	0xe000ecfc

08000d84 <HAL_NVIC_EnableIRQ>:
  if ((int32_t)(IRQn) >= 0)
 8000d84:	2800      	cmp	r0, #0
 8000d86:	db08      	blt.n	8000d9a <HAL_NVIC_EnableIRQ+0x16>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 8000d88:	4a04      	ldr	r2, [pc, #16]	; (8000d9c <HAL_NVIC_EnableIRQ+0x18>)
 8000d8a:	0941      	lsrs	r1, r0, #5
 8000d8c:	2301      	movs	r3, #1
 8000d8e:	f000 001f 	and.w	r0, r0, #31
 8000d92:	fa03 f000 	lsl.w	r0, r3, r0
 8000d96:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
}
 8000d9a:	4770      	bx	lr
 8000d9c:	e000e100 	.word	0xe000e100

08000da0 <HAL_NVIC_DisableIRQ>:
  if ((int32_t)(IRQn) >= 0)
 8000da0:	2800      	cmp	r0, #0
 8000da2:	db0d      	blt.n	8000dc0 <HAL_NVIC_DisableIRQ+0x20>
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 8000da4:	0943      	lsrs	r3, r0, #5
 8000da6:	4907      	ldr	r1, [pc, #28]	; (8000dc4 <HAL_NVIC_DisableIRQ+0x24>)
 8000da8:	2201      	movs	r2, #1
 8000daa:	3320      	adds	r3, #32
 8000dac:	f000 001f 	and.w	r0, r0, #31
 8000db0:	fa02 f000 	lsl.w	r0, r2, r0
 8000db4:	f841 0023 	str.w	r0, [r1, r3, lsl #2]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
 8000db8:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
 8000dbc:	f3bf 8f6f 	isb	sy
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Disable interrupt */
  NVIC_DisableIRQ(IRQn);
}
 8000dc0:	4770      	bx	lr
 8000dc2:	bf00      	nop
 8000dc4:	e000e100 	.word	0xe000e100

08000dc8 <HAL_SYSTICK_Config>:
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8000dc8:	3801      	subs	r0, #1
 8000dca:	f1b0 7f80 	cmp.w	r0, #16777216	; 0x1000000
 8000dce:	d210      	bcs.n	8000df2 <HAL_SYSTICK_Config+0x2a>
  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 8000dd0:	b410      	push	{r4}
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8000dd2:	f04f 23e0 	mov.w	r3, #3758153728	; 0xe000e000
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000dd6:	4c08      	ldr	r4, [pc, #32]	; (8000df8 <HAL_SYSTICK_Config+0x30>)
  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8000dd8:	6158      	str	r0, [r3, #20]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000dda:	f04f 0cf0 	mov.w	ip, #240	; 0xf0
 8000dde:	f884 c023 	strb.w	ip, [r4, #35]	; 0x23
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 8000de2:	2200      	movs	r2, #0
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 8000de4:	2107      	movs	r1, #7
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 8000de6:	4610      	mov	r0, r2
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 8000de8:	619a      	str	r2, [r3, #24]
   return SysTick_Config(TicksNumb);
}
 8000dea:	f85d 4b04 	ldr.w	r4, [sp], #4
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 8000dee:	6119      	str	r1, [r3, #16]
 8000df0:	4770      	bx	lr
    return (1UL);                                                   /* Reload value impossible */
 8000df2:	2001      	movs	r0, #1
 8000df4:	4770      	bx	lr
 8000df6:	bf00      	nop
 8000df8:	e000ed00 	.word	0xe000ed00

08000dfc <HAL_FLASH_Program>:
  *         are stored the data for the row fast program.
  *
  * @retval HAL_Status
  */
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
 8000dfc:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}

  /* Check the parameters */
  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));

  /* Process Locked */
  __HAL_LOCK(&pFlash);
 8000e00:	f8df 8168 	ldr.w	r8, [pc, #360]	; 8000f6c <HAL_FLASH_Program+0x170>
{
 8000e04:	469a      	mov	sl, r3
  __HAL_LOCK(&pFlash);
 8000e06:	f898 3000 	ldrb.w	r3, [r8]
 8000e0a:	2b01      	cmp	r3, #1
 8000e0c:	d05e      	beq.n	8000ecc <HAL_FLASH_Program+0xd0>
 8000e0e:	2301      	movs	r3, #1
 8000e10:	4681      	mov	r9, r0
 8000e12:	460e      	mov	r6, r1
 8000e14:	4617      	mov	r7, r2
 8000e16:	f888 3000 	strb.w	r3, [r8]
{
  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
     Even if the FLASH operation fails, the BUSY flag will be reset and an error
     flag will be set */

  uint32_t tickstart = HAL_GetTick();
 8000e1a:	f7ff ff5d 	bl	8000cd8 <HAL_GetTick>
  uint32_t error;

  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
 8000e1e:	4d52      	ldr	r5, [pc, #328]	; (8000f68 <HAL_FLASH_Program+0x16c>)
  uint32_t tickstart = HAL_GetTick();
 8000e20:	4604      	mov	r4, r0
  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
 8000e22:	e006      	b.n	8000e32 <HAL_FLASH_Program+0x36>
  {
    if ((HAL_GetTick() - tickstart) > Timeout)
 8000e24:	f7ff ff58 	bl	8000cd8 <HAL_GetTick>
 8000e28:	eba0 0c04 	sub.w	ip, r0, r4
 8000e2c:	f5bc 7f7a 	cmp.w	ip, #1000	; 0x3e8
 8000e30:	d845      	bhi.n	8000ebe <HAL_FLASH_Program+0xc2>
  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
 8000e32:	692b      	ldr	r3, [r5, #16]
 8000e34:	03d8      	lsls	r0, r3, #15
 8000e36:	d4f5      	bmi.n	8000e24 <HAL_FLASH_Program+0x28>
      return HAL_TIMEOUT;
    }
  }

  /* Check FLASH operation error flags */
  error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
 8000e38:	692c      	ldr	r4, [r5, #16]
 8000e3a:	f24c 33fa 	movw	r3, #50170	; 0xc3fa
  if (error != 0u)
 8000e3e:	401c      	ands	r4, r3
 8000e40:	d156      	bne.n	8000ef0 <HAL_FLASH_Program+0xf4>

    return HAL_ERROR;
  }

  /* Check FLASH End of Operation flag  */
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
 8000e42:	692b      	ldr	r3, [r5, #16]
    if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
 8000e44:	4a48      	ldr	r2, [pc, #288]	; (8000f68 <HAL_FLASH_Program+0x16c>)
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
 8000e46:	07d9      	lsls	r1, r3, #31
  {
    /* Clear FLASH End of Operation pending bit */
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
 8000e48:	bf44      	itt	mi
 8000e4a:	2301      	movmi	r3, #1
 8000e4c:	612b      	strmi	r3, [r5, #16]
    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 8000e4e:	2300      	movs	r3, #0
 8000e50:	f8c8 3004 	str.w	r3, [r8, #4]
    if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
 8000e54:	6813      	ldr	r3, [r2, #0]
 8000e56:	f413 6380 	ands.w	r3, r3, #1024	; 0x400
      __HAL_FLASH_DATA_CACHE_DISABLE();
 8000e5a:	bf1f      	itttt	ne
 8000e5c:	6813      	ldrne	r3, [r2, #0]
 8000e5e:	f423 6380 	bicne.w	r3, r3, #1024	; 0x400
 8000e62:	6013      	strne	r3, [r2, #0]
      pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
 8000e64:	2302      	movne	r3, #2
      pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
 8000e66:	f888 301c 	strb.w	r3, [r8, #28]
    if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
 8000e6a:	f1b9 0f00 	cmp.w	r9, #0
 8000e6e:	d031      	beq.n	8000ed4 <HAL_FLASH_Program+0xd8>
    else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
 8000e70:	f109 33ff 	add.w	r3, r9, #4294967295	; 0xffffffff
 8000e74:	2b01      	cmp	r3, #1
 8000e76:	d943      	bls.n	8000f00 <HAL_FLASH_Program+0x104>
  uint32_t tickstart = HAL_GetTick();
 8000e78:	f7ff ff2e 	bl	8000cd8 <HAL_GetTick>
  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
 8000e7c:	4e3a      	ldr	r6, [pc, #232]	; (8000f68 <HAL_FLASH_Program+0x16c>)
  uint32_t tickstart = HAL_GetTick();
 8000e7e:	4605      	mov	r5, r0
  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
 8000e80:	e005      	b.n	8000e8e <HAL_FLASH_Program+0x92>
    if ((HAL_GetTick() - tickstart) > Timeout)
 8000e82:	f7ff ff29 	bl	8000cd8 <HAL_GetTick>
 8000e86:	1b40      	subs	r0, r0, r5
 8000e88:	f5b0 7f7a 	cmp.w	r0, #1000	; 0x3e8
 8000e8c:	d82e      	bhi.n	8000eec <HAL_FLASH_Program+0xf0>
  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
 8000e8e:	6933      	ldr	r3, [r6, #16]
 8000e90:	03db      	lsls	r3, r3, #15
 8000e92:	d4f6      	bmi.n	8000e82 <HAL_FLASH_Program+0x86>
  error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
 8000e94:	6933      	ldr	r3, [r6, #16]
 8000e96:	f24c 32fa 	movw	r2, #50170	; 0xc3fa
  if (error != 0u)
 8000e9a:	4013      	ands	r3, r2
 8000e9c:	d153      	bne.n	8000f46 <HAL_FLASH_Program+0x14a>
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
 8000e9e:	6937      	ldr	r7, [r6, #16]
 8000ea0:	f017 0701 	ands.w	r7, r7, #1
 8000ea4:	d002      	beq.n	8000eac <HAL_FLASH_Program+0xb0>
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
 8000ea6:	2201      	movs	r2, #1
 8000ea8:	6132      	str	r2, [r6, #16]
 8000eaa:	461f      	mov	r7, r3
    if (prog_bit != 0U)
 8000eac:	b124      	cbz	r4, 8000eb8 <HAL_FLASH_Program+0xbc>
      CLEAR_BIT(FLASH->CR, prog_bit);
 8000eae:	4a2e      	ldr	r2, [pc, #184]	; (8000f68 <HAL_FLASH_Program+0x16c>)
 8000eb0:	6953      	ldr	r3, [r2, #20]
 8000eb2:	ea23 0404 	bic.w	r4, r3, r4
 8000eb6:	6154      	str	r4, [r2, #20]
    FLASH_FlushCaches();
 8000eb8:	f000 f952 	bl	8001160 <FLASH_FlushCaches>
 8000ebc:	e000      	b.n	8000ec0 <HAL_FLASH_Program+0xc4>
 8000ebe:	2703      	movs	r7, #3
  __HAL_UNLOCK(&pFlash);
 8000ec0:	2300      	movs	r3, #0
 8000ec2:	f888 3000 	strb.w	r3, [r8]
}
 8000ec6:	4638      	mov	r0, r7
 8000ec8:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  __HAL_LOCK(&pFlash);
 8000ecc:	2702      	movs	r7, #2
}
 8000ece:	4638      	mov	r0, r7
 8000ed0:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
{
  /* Check the parameters */
  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));

  /* Set PG bit */
  SET_BIT(FLASH->CR, FLASH_CR_PG);
 8000ed4:	4a24      	ldr	r2, [pc, #144]	; (8000f68 <HAL_FLASH_Program+0x16c>)
 8000ed6:	6953      	ldr	r3, [r2, #20]
 8000ed8:	f043 0301 	orr.w	r3, r3, #1
 8000edc:	6153      	str	r3, [r2, #20]

  /* Program first word */
  *(uint32_t *)Address = (uint32_t)Data;
 8000ede:	6037      	str	r7, [r6, #0]
 8000ee0:	f3bf 8f6f 	isb	sy
      prog_bit = FLASH_CR_PG;
 8000ee4:	2401      	movs	r4, #1
  /* Barrier to ensure programming is performed in 2 steps, in right order
    (independently of compiler optimization behavior) */
  __ISB();

  /* Program second word */
  *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
 8000ee6:	f8c6 a004 	str.w	sl, [r6, #4]
      prog_bit = FLASH_CR_PG;
 8000eea:	e7c5      	b.n	8000e78 <HAL_FLASH_Program+0x7c>
      return HAL_TIMEOUT;
 8000eec:	2703      	movs	r7, #3
 8000eee:	e7dd      	b.n	8000eac <HAL_FLASH_Program+0xb0>
    pFlash.ErrorCode |= error;
 8000ef0:	f8d8 3004 	ldr.w	r3, [r8, #4]
 8000ef4:	4323      	orrs	r3, r4
 8000ef6:	f8c8 3004 	str.w	r3, [r8, #4]
    return HAL_ERROR;
 8000efa:	2701      	movs	r7, #1
    __HAL_FLASH_CLEAR_FLAG(error);
 8000efc:	612c      	str	r4, [r5, #16]
  if (status == HAL_OK)
 8000efe:	e7df      	b.n	8000ec0 <HAL_FLASH_Program+0xc4>

  /* Check the parameters */
  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));

  /* Set FSTPG bit */
  SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
 8000f00:	4919      	ldr	r1, [pc, #100]	; (8000f68 <HAL_FLASH_Program+0x16c>)
 8000f02:	694a      	ldr	r2, [r1, #20]
 8000f04:	f442 2280 	orr.w	r2, r2, #262144	; 0x40000
  uint32_t *src_addr = (uint32_t *)DataAddress;
 8000f08:	463b      	mov	r3, r7
  SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
 8000f0a:	614a      	str	r2, [r1, #20]
  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
 8000f0c:	f3ef 8510 	mrs	r5, PRIMASK
  __ASM volatile ("cpsid i" : : : "memory");
 8000f10:	b672      	cpsid	i
 8000f12:	ea46 0207 	orr.w	r2, r6, r7
 8000f16:	0752      	lsls	r2, r2, #29
 8000f18:	d11d      	bne.n	8000f56 <HAL_FLASH_Program+0x15a>
 8000f1a:	1d3a      	adds	r2, r7, #4
 8000f1c:	42b2      	cmp	r2, r6
 8000f1e:	d01a      	beq.n	8000f56 <HAL_FLASH_Program+0x15a>
 8000f20:	f507 7780 	add.w	r7, r7, #256	; 0x100
 8000f24:	1af6      	subs	r6, r6, r3
  __disable_irq();

  /* Program the double words of the row */
  do
  {
    *dest_addr = *src_addr;
 8000f26:	e9d3 0100 	ldrd	r0, r1, [r3]
 8000f2a:	18f2      	adds	r2, r6, r3
 8000f2c:	3308      	adds	r3, #8
 8000f2e:	42bb      	cmp	r3, r7
 8000f30:	e9c2 0100 	strd	r0, r1, [r2]
    dest_addr++;
    src_addr++;
    row_index--;
  }
  while (row_index != 0U);
 8000f34:	d1f7      	bne.n	8000f26 <HAL_FLASH_Program+0x12a>
  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 8000f36:	f385 8810 	msr	PRIMASK, r5
        prog_bit = FLASH_CR_FSTPG;
 8000f3a:	f1b9 0f02 	cmp.w	r9, #2
 8000f3e:	bf08      	it	eq
 8000f40:	f44f 2480 	moveq.w	r4, #262144	; 0x40000
 8000f44:	e798      	b.n	8000e78 <HAL_FLASH_Program+0x7c>
    pFlash.ErrorCode |= error;
 8000f46:	f8d8 2004 	ldr.w	r2, [r8, #4]
 8000f4a:	431a      	orrs	r2, r3
 8000f4c:	f8c8 2004 	str.w	r2, [r8, #4]
    return HAL_ERROR;
 8000f50:	2701      	movs	r7, #1
    __HAL_FLASH_CLEAR_FLAG(error);
 8000f52:	6133      	str	r3, [r6, #16]
    return HAL_ERROR;
 8000f54:	e7aa      	b.n	8000eac <HAL_FLASH_Program+0xb0>
 8000f56:	1bf6      	subs	r6, r6, r7
 8000f58:	f507 7780 	add.w	r7, r7, #256	; 0x100
    *dest_addr = *src_addr;
 8000f5c:	681a      	ldr	r2, [r3, #0]
 8000f5e:	519a      	str	r2, [r3, r6]
    src_addr++;
 8000f60:	3304      	adds	r3, #4
  while (row_index != 0U);
 8000f62:	429f      	cmp	r7, r3
 8000f64:	d1fa      	bne.n	8000f5c <HAL_FLASH_Program+0x160>
 8000f66:	e7e6      	b.n	8000f36 <HAL_FLASH_Program+0x13a>
 8000f68:	40022000 	.word	0x40022000
 8000f6c:	2000000c 	.word	0x2000000c

08000f70 <HAL_FLASH_Unlock>:
  if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
 8000f70:	4b06      	ldr	r3, [pc, #24]	; (8000f8c <HAL_FLASH_Unlock+0x1c>)
 8000f72:	695a      	ldr	r2, [r3, #20]
 8000f74:	2a00      	cmp	r2, #0
 8000f76:	db01      	blt.n	8000f7c <HAL_FLASH_Unlock+0xc>
  HAL_StatusTypeDef status = HAL_OK;
 8000f78:	2000      	movs	r0, #0
}
 8000f7a:	4770      	bx	lr
    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
 8000f7c:	4904      	ldr	r1, [pc, #16]	; (8000f90 <HAL_FLASH_Unlock+0x20>)
    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
 8000f7e:	4a05      	ldr	r2, [pc, #20]	; (8000f94 <HAL_FLASH_Unlock+0x24>)
    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
 8000f80:	6099      	str	r1, [r3, #8]
    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
 8000f82:	609a      	str	r2, [r3, #8]
    if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
 8000f84:	6958      	ldr	r0, [r3, #20]
  HAL_StatusTypeDef status = HAL_OK;
 8000f86:	0fc0      	lsrs	r0, r0, #31
 8000f88:	4770      	bx	lr
 8000f8a:	bf00      	nop
 8000f8c:	40022000 	.word	0x40022000
 8000f90:	45670123 	.word	0x45670123
 8000f94:	cdef89ab 	.word	0xcdef89ab

08000f98 <HAL_FLASH_Lock>:
  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
 8000f98:	4b04      	ldr	r3, [pc, #16]	; (8000fac <HAL_FLASH_Lock+0x14>)
 8000f9a:	695a      	ldr	r2, [r3, #20]
 8000f9c:	f042 4200 	orr.w	r2, r2, #2147483648	; 0x80000000
 8000fa0:	615a      	str	r2, [r3, #20]
  if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
 8000fa2:	6958      	ldr	r0, [r3, #20]
}
 8000fa4:	43c0      	mvns	r0, r0
 8000fa6:	0fc0      	lsrs	r0, r0, #31
 8000fa8:	4770      	bx	lr
 8000faa:	bf00      	nop
 8000fac:	40022000 	.word	0x40022000

08000fb0 <FLASH_WaitForLastOperation>:
{
 8000fb0:	b570      	push	{r4, r5, r6, lr}
 8000fb2:	4605      	mov	r5, r0
  uint32_t tickstart = HAL_GetTick();
 8000fb4:	f7ff fe90 	bl	8000cd8 <HAL_GetTick>
  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
 8000fb8:	4e10      	ldr	r6, [pc, #64]	; (8000ffc <FLASH_WaitForLastOperation+0x4c>)
  uint32_t tickstart = HAL_GetTick();
 8000fba:	4604      	mov	r4, r0
  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
 8000fbc:	e004      	b.n	8000fc8 <FLASH_WaitForLastOperation+0x18>
    if ((HAL_GetTick() - tickstart) > Timeout)
 8000fbe:	f7ff fe8b 	bl	8000cd8 <HAL_GetTick>
 8000fc2:	1b03      	subs	r3, r0, r4
 8000fc4:	42ab      	cmp	r3, r5
 8000fc6:	d80f      	bhi.n	8000fe8 <FLASH_WaitForLastOperation+0x38>
  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
 8000fc8:	6933      	ldr	r3, [r6, #16]
 8000fca:	03db      	lsls	r3, r3, #15
 8000fcc:	d4f7      	bmi.n	8000fbe <FLASH_WaitForLastOperation+0xe>
  error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
 8000fce:	6933      	ldr	r3, [r6, #16]
 8000fd0:	f24c 32fa 	movw	r2, #50170	; 0xc3fa
  if (error != 0u)
 8000fd4:	4013      	ands	r3, r2
 8000fd6:	d109      	bne.n	8000fec <FLASH_WaitForLastOperation+0x3c>
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
 8000fd8:	6930      	ldr	r0, [r6, #16]
 8000fda:	f010 0001 	ands.w	r0, r0, #1
 8000fde:	d002      	beq.n	8000fe6 <FLASH_WaitForLastOperation+0x36>
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
 8000fe0:	2201      	movs	r2, #1
 8000fe2:	6132      	str	r2, [r6, #16]
 8000fe4:	4618      	mov	r0, r3
}
 8000fe6:	bd70      	pop	{r4, r5, r6, pc}
      return HAL_TIMEOUT;
 8000fe8:	2003      	movs	r0, #3
}
 8000fea:	bd70      	pop	{r4, r5, r6, pc}
    pFlash.ErrorCode |= error;
 8000fec:	4904      	ldr	r1, [pc, #16]	; (8001000 <FLASH_WaitForLastOperation+0x50>)
 8000fee:	684a      	ldr	r2, [r1, #4]
 8000ff0:	431a      	orrs	r2, r3
 8000ff2:	604a      	str	r2, [r1, #4]
    return HAL_ERROR;
 8000ff4:	2001      	movs	r0, #1
    __HAL_FLASH_CLEAR_FLAG(error);
 8000ff6:	6133      	str	r3, [r6, #16]
}
 8000ff8:	bd70      	pop	{r4, r5, r6, pc}
 8000ffa:	bf00      	nop
 8000ffc:	40022000 	.word	0x40022000
 8001000:	2000000c 	.word	0x2000000c

08001004 <HAL_FLASHEx_Erase>:
  *         information on faulty page in case of error (0xFFFFFFFF means that all
  *         the pages have been correctly erased).
  * @retval HAL_Status
  */
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
 8001004:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}

  /* Check the parameters */
  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));

  /* Process Locked */
  __HAL_LOCK(&pFlash);
 8001008:	4f53      	ldr	r7, [pc, #332]	; (8001158 <HAL_FLASHEx_Erase+0x154>)
 800100a:	783b      	ldrb	r3, [r7, #0]
 800100c:	2b01      	cmp	r3, #1
 800100e:	d07a      	beq.n	8001106 <HAL_FLASHEx_Erase+0x102>
 8001010:	4681      	mov	r9, r0
 8001012:	2401      	movs	r4, #1

  /* Wait for last operation to be completed */
  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 8001014:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
 8001018:	4688      	mov	r8, r1
  __HAL_LOCK(&pFlash);
 800101a:	703c      	strb	r4, [r7, #0]
  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 800101c:	f7ff ffc8 	bl	8000fb0 <FLASH_WaitForLastOperation>

  if (status == HAL_OK)
 8001020:	4606      	mov	r6, r0
 8001022:	b120      	cbz	r0, 800102e <HAL_FLASHEx_Erase+0x2a>
    /* Flush the caches to be sure of the data consistency */
    FLASH_FlushCaches();
  }

  /* Process Unlocked */
  __HAL_UNLOCK(&pFlash);
 8001024:	2300      	movs	r3, #0
 8001026:	703b      	strb	r3, [r7, #0]

  return status;
}
 8001028:	4630      	mov	r0, r6
 800102a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
 800102e:	4b4b      	ldr	r3, [pc, #300]	; (800115c <HAL_FLASHEx_Erase+0x158>)
    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 8001030:	6078      	str	r0, [r7, #4]
    if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
 8001032:	681a      	ldr	r2, [r3, #0]
 8001034:	f412 7f00 	tst.w	r2, #512	; 0x200
      if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
 8001038:	681a      	ldr	r2, [r3, #0]
    if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
 800103a:	d168      	bne.n	800110e <HAL_FLASHEx_Erase+0x10a>
    else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
 800103c:	0552      	lsls	r2, r2, #21
 800103e:	f140 8089 	bpl.w	8001154 <HAL_FLASHEx_Erase+0x150>
      __HAL_FLASH_DATA_CACHE_DISABLE();
 8001042:	681a      	ldr	r2, [r3, #0]
 8001044:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
 8001048:	601a      	str	r2, [r3, #0]
      pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
 800104a:	2302      	movs	r3, #2
 800104c:	773b      	strb	r3, [r7, #28]
    if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
 800104e:	f8d9 3000 	ldr.w	r3, [r9]
 8001052:	2b01      	cmp	r3, #1
 8001054:	d064      	beq.n	8001120 <HAL_FLASHEx_Erase+0x11c>
      *PageError = 0xFFFFFFFFU;
 8001056:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
 800105a:	f8c8 3000 	str.w	r3, [r8]
      for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
 800105e:	e9d9 5302 	ldrd	r5, r3, [r9, #8]
 8001062:	442b      	add	r3, r5
 8001064:	429d      	cmp	r5, r3
 8001066:	d224      	bcs.n	80010b2 <HAL_FLASHEx_Erase+0xae>
  /* Prevent unused argument(s) compilation warning */
  UNUSED(Banks);
#endif /* FLASH_OPTR_DBANK */

  /* Proceed to erase the page */
  MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));
 8001068:	4c3c      	ldr	r4, [pc, #240]	; (800115c <HAL_FLASHEx_Erase+0x158>)
 800106a:	e005      	b.n	8001078 <HAL_FLASHEx_Erase+0x74>
      for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
 800106c:	e9d9 3202 	ldrd	r3, r2, [r9, #8]
 8001070:	3501      	adds	r5, #1
 8001072:	4413      	add	r3, r2
 8001074:	42ab      	cmp	r3, r5
 8001076:	d91c      	bls.n	80010b2 <HAL_FLASHEx_Erase+0xae>
  MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));
 8001078:	6962      	ldr	r2, [r4, #20]
 800107a:	00eb      	lsls	r3, r5, #3
 800107c:	f422 72fc 	bic.w	r2, r2, #504	; 0x1f8
 8001080:	f403 63ff 	and.w	r3, r3, #2040	; 0x7f8
 8001084:	4313      	orrs	r3, r2
 8001086:	6163      	str	r3, [r4, #20]
  SET_BIT(FLASH->CR, FLASH_CR_PER);
 8001088:	6963      	ldr	r3, [r4, #20]
 800108a:	f043 0302 	orr.w	r3, r3, #2
 800108e:	6163      	str	r3, [r4, #20]
  SET_BIT(FLASH->CR, FLASH_CR_STRT);
 8001090:	6963      	ldr	r3, [r4, #20]
 8001092:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8001096:	6163      	str	r3, [r4, #20]
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 8001098:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
 800109c:	f7ff ff88 	bl	8000fb0 <FLASH_WaitForLastOperation>
        CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
 80010a0:	6963      	ldr	r3, [r4, #20]
 80010a2:	f423 73fd 	bic.w	r3, r3, #506	; 0x1fa
 80010a6:	6163      	str	r3, [r4, #20]
        if (status != HAL_OK)
 80010a8:	2800      	cmp	r0, #0
 80010aa:	d0df      	beq.n	800106c <HAL_FLASHEx_Erase+0x68>
          *PageError = page_index;
 80010ac:	f8c8 5000 	str.w	r5, [r8]
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 80010b0:	4606      	mov	r6, r0
  * @brief  Flush the instruction and data caches.
  * @retval None
  */
void FLASH_FlushCaches(void)
{
  FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
 80010b2:	7f3b      	ldrb	r3, [r7, #28]

  /* Flush instruction cache  */
  if ((cache == FLASH_CACHE_ICACHE_ENABLED) ||
 80010b4:	f003 02fd 	and.w	r2, r3, #253	; 0xfd
 80010b8:	2a01      	cmp	r2, #1
  FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
 80010ba:	b2db      	uxtb	r3, r3
  if ((cache == FLASH_CACHE_ICACHE_ENABLED) ||
 80010bc:	d110      	bne.n	80010e0 <HAL_FLASHEx_Erase+0xdc>
      (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
  {
    /* Disable instruction cache */
    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
 80010be:	4a27      	ldr	r2, [pc, #156]	; (800115c <HAL_FLASHEx_Erase+0x158>)
 80010c0:	6811      	ldr	r1, [r2, #0]
 80010c2:	f421 7100 	bic.w	r1, r1, #512	; 0x200
 80010c6:	6011      	str	r1, [r2, #0]
    /* Reset instruction cache */
    __HAL_FLASH_INSTRUCTION_CACHE_RESET();
 80010c8:	6811      	ldr	r1, [r2, #0]
 80010ca:	f441 6100 	orr.w	r1, r1, #2048	; 0x800
 80010ce:	6011      	str	r1, [r2, #0]
 80010d0:	6811      	ldr	r1, [r2, #0]
 80010d2:	f421 6100 	bic.w	r1, r1, #2048	; 0x800
 80010d6:	6011      	str	r1, [r2, #0]
    /* Enable instruction cache */
    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
 80010d8:	6811      	ldr	r1, [r2, #0]
 80010da:	f441 7100 	orr.w	r1, r1, #512	; 0x200
 80010de:	6011      	str	r1, [r2, #0]
  }

  /* Flush data cache */
  if ((cache == FLASH_CACHE_DCACHE_ENABLED) ||
 80010e0:	3b02      	subs	r3, #2
 80010e2:	2b01      	cmp	r3, #1
 80010e4:	d80c      	bhi.n	8001100 <HAL_FLASHEx_Erase+0xfc>
      (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
  {
    /* Reset data cache */
    __HAL_FLASH_DATA_CACHE_RESET();
 80010e6:	4b1d      	ldr	r3, [pc, #116]	; (800115c <HAL_FLASHEx_Erase+0x158>)
 80010e8:	681a      	ldr	r2, [r3, #0]
 80010ea:	f442 5280 	orr.w	r2, r2, #4096	; 0x1000
 80010ee:	601a      	str	r2, [r3, #0]
 80010f0:	681a      	ldr	r2, [r3, #0]
 80010f2:	f422 5280 	bic.w	r2, r2, #4096	; 0x1000
 80010f6:	601a      	str	r2, [r3, #0]
    /* Enable data cache */
    __HAL_FLASH_DATA_CACHE_ENABLE();
 80010f8:	681a      	ldr	r2, [r3, #0]
 80010fa:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
 80010fe:	601a      	str	r2, [r3, #0]
  }

  /* Reset internal variable */
  pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
 8001100:	2300      	movs	r3, #0
 8001102:	773b      	strb	r3, [r7, #28]
}
 8001104:	e78e      	b.n	8001024 <HAL_FLASHEx_Erase+0x20>
  __HAL_LOCK(&pFlash);
 8001106:	2602      	movs	r6, #2
}
 8001108:	4630      	mov	r0, r6
 800110a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
      if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
 800110e:	0551      	lsls	r1, r2, #21
 8001110:	d51e      	bpl.n	8001150 <HAL_FLASHEx_Erase+0x14c>
        __HAL_FLASH_DATA_CACHE_DISABLE();
 8001112:	681a      	ldr	r2, [r3, #0]
 8001114:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
 8001118:	601a      	str	r2, [r3, #0]
        pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
 800111a:	2303      	movs	r3, #3
 800111c:	773b      	strb	r3, [r7, #28]
 800111e:	e796      	b.n	800104e <HAL_FLASHEx_Erase+0x4a>
    if ((Banks & FLASH_BANK_1) != 0U)
 8001120:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8001124:	07db      	lsls	r3, r3, #31
 8001126:	d504      	bpl.n	8001132 <HAL_FLASHEx_Erase+0x12e>
      SET_BIT(FLASH->CR, FLASH_CR_MER1);
 8001128:	4a0c      	ldr	r2, [pc, #48]	; (800115c <HAL_FLASHEx_Erase+0x158>)
 800112a:	6953      	ldr	r3, [r2, #20]
 800112c:	f043 0304 	orr.w	r3, r3, #4
 8001130:	6153      	str	r3, [r2, #20]
  SET_BIT(FLASH->CR, FLASH_CR_STRT);
 8001132:	4c0a      	ldr	r4, [pc, #40]	; (800115c <HAL_FLASHEx_Erase+0x158>)
 8001134:	6963      	ldr	r3, [r4, #20]
 8001136:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 800113a:	6163      	str	r3, [r4, #20]
      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 800113c:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
 8001140:	f7ff ff36 	bl	8000fb0 <FLASH_WaitForLastOperation>
      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
 8001144:	6963      	ldr	r3, [r4, #20]
 8001146:	f023 0304 	bic.w	r3, r3, #4
      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 800114a:	4606      	mov	r6, r0
      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
 800114c:	6163      	str	r3, [r4, #20]
 800114e:	e7b0      	b.n	80010b2 <HAL_FLASHEx_Erase+0xae>
        pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
 8001150:	773c      	strb	r4, [r7, #28]
 8001152:	e77c      	b.n	800104e <HAL_FLASHEx_Erase+0x4a>
      pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
 8001154:	7738      	strb	r0, [r7, #28]
 8001156:	e77a      	b.n	800104e <HAL_FLASHEx_Erase+0x4a>
 8001158:	2000000c 	.word	0x2000000c
 800115c:	40022000 	.word	0x40022000

08001160 <FLASH_FlushCaches>:
  FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
 8001160:	4915      	ldr	r1, [pc, #84]	; (80011b8 <FLASH_FlushCaches+0x58>)
 8001162:	7f0b      	ldrb	r3, [r1, #28]
  if ((cache == FLASH_CACHE_ICACHE_ENABLED) ||
 8001164:	f003 02fd 	and.w	r2, r3, #253	; 0xfd
 8001168:	2a01      	cmp	r2, #1
  FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
 800116a:	b2db      	uxtb	r3, r3
  if ((cache == FLASH_CACHE_ICACHE_ENABLED) ||
 800116c:	d110      	bne.n	8001190 <FLASH_FlushCaches+0x30>
    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
 800116e:	4a13      	ldr	r2, [pc, #76]	; (80011bc <FLASH_FlushCaches+0x5c>)
 8001170:	6810      	ldr	r0, [r2, #0]
 8001172:	f420 7000 	bic.w	r0, r0, #512	; 0x200
 8001176:	6010      	str	r0, [r2, #0]
    __HAL_FLASH_INSTRUCTION_CACHE_RESET();
 8001178:	6810      	ldr	r0, [r2, #0]
 800117a:	f440 6000 	orr.w	r0, r0, #2048	; 0x800
 800117e:	6010      	str	r0, [r2, #0]
 8001180:	6810      	ldr	r0, [r2, #0]
 8001182:	f420 6000 	bic.w	r0, r0, #2048	; 0x800
 8001186:	6010      	str	r0, [r2, #0]
    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
 8001188:	6810      	ldr	r0, [r2, #0]
 800118a:	f440 7000 	orr.w	r0, r0, #512	; 0x200
 800118e:	6010      	str	r0, [r2, #0]
  if ((cache == FLASH_CACHE_DCACHE_ENABLED) ||
 8001190:	3b02      	subs	r3, #2
 8001192:	2b01      	cmp	r3, #1
 8001194:	d80c      	bhi.n	80011b0 <FLASH_FlushCaches+0x50>
    __HAL_FLASH_DATA_CACHE_RESET();
 8001196:	4b09      	ldr	r3, [pc, #36]	; (80011bc <FLASH_FlushCaches+0x5c>)
 8001198:	681a      	ldr	r2, [r3, #0]
 800119a:	f442 5280 	orr.w	r2, r2, #4096	; 0x1000
 800119e:	601a      	str	r2, [r3, #0]
 80011a0:	681a      	ldr	r2, [r3, #0]
 80011a2:	f422 5280 	bic.w	r2, r2, #4096	; 0x1000
 80011a6:	601a      	str	r2, [r3, #0]
    __HAL_FLASH_DATA_CACHE_ENABLE();
 80011a8:	681a      	ldr	r2, [r3, #0]
 80011aa:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
 80011ae:	601a      	str	r2, [r3, #0]
  pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
 80011b0:	2300      	movs	r3, #0
 80011b2:	770b      	strb	r3, [r1, #28]
}
 80011b4:	4770      	bx	lr
 80011b6:	bf00      	nop
 80011b8:	2000000c 	.word	0x2000000c
 80011bc:	40022000 	.word	0x40022000

080011c0 <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef const *GPIO_Init)
{
 80011c0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0U)
 80011c4:	680c      	ldr	r4, [r1, #0]
{
 80011c6:	b085      	sub	sp, #20
  while (((GPIO_Init->Pin) >> position) != 0U)
 80011c8:	2c00      	cmp	r4, #0
 80011ca:	f000 8097 	beq.w	80012fc <HAL_GPIO_Init+0x13c>
 80011ce:	2200      	movs	r2, #0
      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 80011d0:	f8df a20c 	ldr.w	sl, [pc, #524]	; 80013e0 <HAL_GPIO_Init+0x220>
  uint32_t position = 0x00U;
 80011d4:	4613      	mov	r3, r2
    iocurrent = (GPIO_Init->Pin) & (1UL << position);
 80011d6:	f04f 0b01 	mov.w	fp, #1

        temp = SYSCFG->EXTICR[position >> 2U];
        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
 80011da:	46a1      	mov	r9, r4
    iocurrent = (GPIO_Init->Pin) & (1UL << position);
 80011dc:	fa0b fc03 	lsl.w	ip, fp, r3
    if (iocurrent != 0x00u)
 80011e0:	ea1c 0809 	ands.w	r8, ip, r9
 80011e4:	f000 8083 	beq.w	80012ee <HAL_GPIO_Init+0x12e>
      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
 80011e8:	684f      	ldr	r7, [r1, #4]
 80011ea:	f007 0403 	and.w	r4, r7, #3
 80011ee:	1e65      	subs	r5, r4, #1
 80011f0:	2d01      	cmp	r5, #1
 80011f2:	f240 8086 	bls.w	8001302 <HAL_GPIO_Init+0x142>
      if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
 80011f6:	2c03      	cmp	r4, #3
 80011f8:	f040 80c7 	bne.w	800138a <HAL_GPIO_Init+0x1ca>
          (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP)))
 80011fc:	688d      	ldr	r5, [r1, #8]
      if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
 80011fe:	2d01      	cmp	r5, #1
        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 8001200:	fa04 f402 	lsl.w	r4, r4, r2
      if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
 8001204:	d007      	beq.n	8001216 <HAL_GPIO_Init+0x56>
        temp = GPIOx->PUPDR;
 8001206:	f8d0 c00c 	ldr.w	ip, [r0, #12]
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 800120a:	4095      	lsls	r5, r2
        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 800120c:	ea2c 0c04 	bic.w	ip, ip, r4
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 8001210:	ea45 050c 	orr.w	r5, r5, ip
        GPIOx->PUPDR = temp;
 8001214:	60c5      	str	r5, [r0, #12]
        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 8001216:	43e5      	mvns	r5, r4
      temp = GPIOx->MODER;
 8001218:	f8d0 c000 	ldr.w	ip, [r0]
      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
 800121c:	ea0c 0505 	and.w	r5, ip, r5
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
 8001220:	432c      	orrs	r4, r5
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
 8001222:	f417 3f40 	tst.w	r7, #196608	; 0x30000
      GPIOx->MODER = temp;
 8001226:	6004      	str	r4, [r0, #0]
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
 8001228:	d061      	beq.n	80012ee <HAL_GPIO_Init+0x12e>
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 800122a:	f8da 4060 	ldr.w	r4, [sl, #96]	; 0x60
 800122e:	f044 0401 	orr.w	r4, r4, #1
 8001232:	f8ca 4060 	str.w	r4, [sl, #96]	; 0x60
 8001236:	f8da 4060 	ldr.w	r4, [sl, #96]	; 0x60
 800123a:	f004 0401 	and.w	r4, r4, #1
 800123e:	9403      	str	r4, [sp, #12]
 8001240:	9c03      	ldr	r4, [sp, #12]
        temp = SYSCFG->EXTICR[position >> 2U];
 8001242:	f023 0403 	bic.w	r4, r3, #3
 8001246:	f104 4480 	add.w	r4, r4, #1073741824	; 0x40000000
 800124a:	f504 3480 	add.w	r4, r4, #65536	; 0x10000
        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
 800124e:	f003 0c03 	and.w	ip, r3, #3
        temp = SYSCFG->EXTICR[position >> 2U];
 8001252:	68a5      	ldr	r5, [r4, #8]
        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
 8001254:	ea4f 0c8c 	mov.w	ip, ip, lsl #2
 8001258:	260f      	movs	r6, #15
 800125a:	fa06 fe0c 	lsl.w	lr, r6, ip
        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
 800125e:	f1b0 4f90 	cmp.w	r0, #1207959552	; 0x48000000
        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
 8001262:	ea25 050e 	bic.w	r5, r5, lr
        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
 8001266:	d01a      	beq.n	800129e <HAL_GPIO_Init+0xde>
 8001268:	4e57      	ldr	r6, [pc, #348]	; (80013c8 <HAL_GPIO_Init+0x208>)
 800126a:	42b0      	cmp	r0, r6
 800126c:	f000 8098 	beq.w	80013a0 <HAL_GPIO_Init+0x1e0>
 8001270:	4e56      	ldr	r6, [pc, #344]	; (80013cc <HAL_GPIO_Init+0x20c>)
 8001272:	42b0      	cmp	r0, r6
 8001274:	f000 8099 	beq.w	80013aa <HAL_GPIO_Init+0x1ea>
 8001278:	4e55      	ldr	r6, [pc, #340]	; (80013d0 <HAL_GPIO_Init+0x210>)
 800127a:	42b0      	cmp	r0, r6
 800127c:	f000 8089 	beq.w	8001392 <HAL_GPIO_Init+0x1d2>
 8001280:	4e54      	ldr	r6, [pc, #336]	; (80013d4 <HAL_GPIO_Init+0x214>)
 8001282:	42b0      	cmp	r0, r6
 8001284:	f000 8098 	beq.w	80013b8 <HAL_GPIO_Init+0x1f8>
 8001288:	4e53      	ldr	r6, [pc, #332]	; (80013d8 <HAL_GPIO_Init+0x218>)
 800128a:	42b0      	cmp	r0, r6
 800128c:	bf0c      	ite	eq
 800128e:	f04f 0e05 	moveq.w	lr, #5
 8001292:	f04f 0e06 	movne.w	lr, #6
 8001296:	fa0e fc0c 	lsl.w	ip, lr, ip
 800129a:	ea45 050c 	orr.w	r5, r5, ip
        SYSCFG->EXTICR[position >> 2U] = temp;
 800129e:	60a5      	str	r5, [r4, #8]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR1;
 80012a0:	4c4e      	ldr	r4, [pc, #312]	; (80013dc <HAL_GPIO_Init+0x21c>)
        temp &= ~(iocurrent);
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
        {
          temp |= iocurrent;
        }
        EXTI->RTSR1 = temp;
 80012a2:	4d4e      	ldr	r5, [pc, #312]	; (80013dc <HAL_GPIO_Init+0x21c>)
        temp = EXTI->RTSR1;
 80012a4:	68a4      	ldr	r4, [r4, #8]
        temp &= ~(iocurrent);
 80012a6:	ea6f 0c08 	mvn.w	ip, r8
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
 80012aa:	02fe      	lsls	r6, r7, #11
        temp &= ~(iocurrent);
 80012ac:	bf54      	ite	pl
 80012ae:	ea0c 0404 	andpl.w	r4, ip, r4
          temp |= iocurrent;
 80012b2:	ea48 0404 	orrmi.w	r4, r8, r4
        EXTI->RTSR1 = temp;
 80012b6:	60ac      	str	r4, [r5, #8]

        temp = EXTI->FTSR1;
 80012b8:	68ec      	ldr	r4, [r5, #12]
        temp &= ~(iocurrent);
        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
 80012ba:	02bd      	lsls	r5, r7, #10
        {
          temp |= iocurrent;
        }
        EXTI->FTSR1 = temp;
 80012bc:	4d47      	ldr	r5, [pc, #284]	; (80013dc <HAL_GPIO_Init+0x21c>)
        temp &= ~(iocurrent);
 80012be:	bf54      	ite	pl
 80012c0:	ea0c 0404 	andpl.w	r4, ip, r4
          temp |= iocurrent;
 80012c4:	ea48 0404 	orrmi.w	r4, r8, r4
        EXTI->FTSR1 = temp;
 80012c8:	60ec      	str	r4, [r5, #12]

        temp = EXTI->EMR1;
 80012ca:	686d      	ldr	r5, [r5, #4]
        temp &= ~(iocurrent);
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
        {
          temp |= iocurrent;
        }
        EXTI->EMR1 = temp;
 80012cc:	4c43      	ldr	r4, [pc, #268]	; (80013dc <HAL_GPIO_Init+0x21c>)
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
 80012ce:	03be      	lsls	r6, r7, #14
        temp &= ~(iocurrent);
 80012d0:	bf54      	ite	pl
 80012d2:	ea0c 0505 	andpl.w	r5, ip, r5
          temp |= iocurrent;
 80012d6:	ea48 0505 	orrmi.w	r5, r8, r5
        EXTI->EMR1 = temp;
 80012da:	6065      	str	r5, [r4, #4]

        /* Clear EXTI line configuration */
        temp = EXTI->IMR1;
 80012dc:	6824      	ldr	r4, [r4, #0]
        temp &= ~(iocurrent);
        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
 80012de:	03fd      	lsls	r5, r7, #15
        {
          temp |= iocurrent;
        }
        EXTI->IMR1 = temp;
 80012e0:	4d3e      	ldr	r5, [pc, #248]	; (80013dc <HAL_GPIO_Init+0x21c>)
        temp &= ~(iocurrent);
 80012e2:	bf54      	ite	pl
 80012e4:	ea0c 0404 	andpl.w	r4, ip, r4
          temp |= iocurrent;
 80012e8:	ea48 0404 	orrmi.w	r4, r8, r4
        EXTI->IMR1 = temp;
 80012ec:	602c      	str	r4, [r5, #0]
      }
    }

    position++;
 80012ee:	3301      	adds	r3, #1
  while (((GPIO_Init->Pin) >> position) != 0U)
 80012f0:	fa39 f403 	lsrs.w	r4, r9, r3
 80012f4:	f102 0202 	add.w	r2, r2, #2
 80012f8:	f47f af70 	bne.w	80011dc <HAL_GPIO_Init+0x1c>
  }
}
 80012fc:	b005      	add	sp, #20
 80012fe:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        temp = GPIOx->OSPEEDR;
 8001302:	6885      	ldr	r5, [r0, #8]
        temp |= (GPIO_Init->Speed << (position * 2U));
 8001304:	68ce      	ldr	r6, [r1, #12]
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
 8001306:	f04f 0e03 	mov.w	lr, #3
 800130a:	fa0e fe02 	lsl.w	lr, lr, r2
 800130e:	ea25 050e 	bic.w	r5, r5, lr
        temp |= (GPIO_Init->Speed << (position * 2U));
 8001312:	4096      	lsls	r6, r2
 8001314:	4335      	orrs	r5, r6
        GPIOx->OSPEEDR = temp;
 8001316:	6085      	str	r5, [r0, #8]
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
 8001318:	ea6f 050e 	mvn.w	r5, lr
        temp = GPIOx->OTYPER;
 800131c:	f8d0 e004 	ldr.w	lr, [r0, #4]
        temp &= ~(GPIO_OTYPER_OT0 << position) ;
 8001320:	ea2e 0e0c 	bic.w	lr, lr, ip
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 8001324:	f3c7 1c00 	ubfx	ip, r7, #4, #1
 8001328:	fa0c fc03 	lsl.w	ip, ip, r3
 800132c:	ea4c 0c0e 	orr.w	ip, ip, lr
        GPIOx->OTYPER = temp;
 8001330:	f8c0 c004 	str.w	ip, [r0, #4]
        temp = GPIOx->PUPDR;
 8001334:	f8d0 c00c 	ldr.w	ip, [r0, #12]
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 8001338:	688e      	ldr	r6, [r1, #8]
        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 800133a:	ea0c 0c05 	and.w	ip, ip, r5
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 800133e:	fa06 fe02 	lsl.w	lr, r6, r2
 8001342:	ea4e 0c0c 	orr.w	ip, lr, ip
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8001346:	2c02      	cmp	r4, #2
        GPIOx->PUPDR = temp;
 8001348:	f8c0 c00c 	str.w	ip, [r0, #12]
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 800134c:	fa04 f402 	lsl.w	r4, r4, r2
 8001350:	f47f af62 	bne.w	8001218 <HAL_GPIO_Init+0x58>
        temp = GPIOx->AFR[position >> 3U];
 8001354:	ea4f 0ed3 	mov.w	lr, r3, lsr #3
 8001358:	eb00 0e8e 	add.w	lr, r0, lr, lsl #2
        temp &= ~(0xFU << ((position & 0x07U) * 4U));
 800135c:	f003 0c07 	and.w	ip, r3, #7
        temp = GPIOx->AFR[position >> 3U];
 8001360:	f8de 6020 	ldr.w	r6, [lr, #32]
 8001364:	9600      	str	r6, [sp, #0]
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
 8001366:	690e      	ldr	r6, [r1, #16]
        temp &= ~(0xFU << ((position & 0x07U) * 4U));
 8001368:	ea4f 0c8c 	mov.w	ip, ip, lsl #2
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
 800136c:	fa06 f60c 	lsl.w	r6, r6, ip
 8001370:	9601      	str	r6, [sp, #4]
        temp &= ~(0xFU << ((position & 0x07U) * 4U));
 8001372:	260f      	movs	r6, #15
 8001374:	fa06 fc0c 	lsl.w	ip, r6, ip
 8001378:	9e00      	ldr	r6, [sp, #0]
 800137a:	ea26 0c0c 	bic.w	ip, r6, ip
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
 800137e:	9e01      	ldr	r6, [sp, #4]
 8001380:	ea46 0c0c 	orr.w	ip, r6, ip
        GPIOx->AFR[position >> 3U] = temp;
 8001384:	f8ce c020 	str.w	ip, [lr, #32]
 8001388:	e746      	b.n	8001218 <HAL_GPIO_Init+0x58>
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
 800138a:	2503      	movs	r5, #3
 800138c:	4095      	lsls	r5, r2
 800138e:	43ed      	mvns	r5, r5
 8001390:	e7d0      	b.n	8001334 <HAL_GPIO_Init+0x174>
        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
 8001392:	f04f 0e03 	mov.w	lr, #3
 8001396:	fa0e fc0c 	lsl.w	ip, lr, ip
 800139a:	ea45 050c 	orr.w	r5, r5, ip
 800139e:	e77e      	b.n	800129e <HAL_GPIO_Init+0xde>
 80013a0:	fa0b fc0c 	lsl.w	ip, fp, ip
 80013a4:	ea45 050c 	orr.w	r5, r5, ip
 80013a8:	e779      	b.n	800129e <HAL_GPIO_Init+0xde>
 80013aa:	f04f 0e02 	mov.w	lr, #2
 80013ae:	fa0e fc0c 	lsl.w	ip, lr, ip
 80013b2:	ea45 050c 	orr.w	r5, r5, ip
 80013b6:	e772      	b.n	800129e <HAL_GPIO_Init+0xde>
 80013b8:	f04f 0e04 	mov.w	lr, #4
 80013bc:	fa0e fc0c 	lsl.w	ip, lr, ip
 80013c0:	ea45 050c 	orr.w	r5, r5, ip
 80013c4:	e76b      	b.n	800129e <HAL_GPIO_Init+0xde>
 80013c6:	bf00      	nop
 80013c8:	48000400 	.word	0x48000400
 80013cc:	48000800 	.word	0x48000800
 80013d0:	48000c00 	.word	0x48000c00
 80013d4:	48001000 	.word	0x48001000
 80013d8:	48001400 	.word	0x48001400
 80013dc:	40010400 	.word	0x40010400
 80013e0:	40021000 	.word	0x40021000

080013e4 <HAL_GPIO_DeInit>:
  /* Check the parameters */
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  /* Configure the port pins */
  while ((GPIO_Pin >> position) != 0U)
 80013e4:	2900      	cmp	r1, #0
 80013e6:	f000 8082 	beq.w	80014ee <HAL_GPIO_DeInit+0x10a>
{
 80013ea:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  uint32_t position = 0x00U;
 80013ee:	2300      	movs	r3, #0
      tmp = SYSCFG->EXTICR[position >> 2U];
      tmp &= (0x0FUL << (4U * (position & 0x03U)));
      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
      {
        /* Clear EXTI line configuration */
        EXTI->IMR1 &= ~(iocurrent);
 80013f0:	4e3f      	ldr	r6, [pc, #252]	; (80014f0 <HAL_GPIO_DeInit+0x10c>)
      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
 80013f2:	f8df b110 	ldr.w	fp, [pc, #272]	; 8001504 <HAL_GPIO_DeInit+0x120>
      tmp &= (0x0FUL << (4U * (position & 0x03U)));
 80013f6:	f04f 090f 	mov.w	r9, #15
        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
      }

      /*------------------------- GPIO Mode Configuration --------------------*/
      /* Configure IO in Analog Mode */
      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
 80013fa:	f04f 0a03 	mov.w	sl, #3
 80013fe:	e04c      	b.n	800149a <HAL_GPIO_DeInit+0xb6>
      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
 8001400:	4558      	cmp	r0, fp
 8001402:	d065      	beq.n	80014d0 <HAL_GPIO_DeInit+0xec>
 8001404:	4f3b      	ldr	r7, [pc, #236]	; (80014f4 <HAL_GPIO_DeInit+0x110>)
 8001406:	42b8      	cmp	r0, r7
 8001408:	d066      	beq.n	80014d8 <HAL_GPIO_DeInit+0xf4>
 800140a:	4f3b      	ldr	r7, [pc, #236]	; (80014f8 <HAL_GPIO_DeInit+0x114>)
 800140c:	42b8      	cmp	r0, r7
 800140e:	d067      	beq.n	80014e0 <HAL_GPIO_DeInit+0xfc>
 8001410:	4f3a      	ldr	r7, [pc, #232]	; (80014fc <HAL_GPIO_DeInit+0x118>)
 8001412:	42b8      	cmp	r0, r7
 8001414:	d067      	beq.n	80014e6 <HAL_GPIO_DeInit+0x102>
 8001416:	4f3a      	ldr	r7, [pc, #232]	; (8001500 <HAL_GPIO_DeInit+0x11c>)
 8001418:	42b8      	cmp	r0, r7
 800141a:	bf14      	ite	ne
 800141c:	2706      	movne	r7, #6
 800141e:	2705      	moveq	r7, #5
 8001420:	fa07 f404 	lsl.w	r4, r7, r4
 8001424:	45a4      	cmp	ip, r4
 8001426:	d113      	bne.n	8001450 <HAL_GPIO_DeInit+0x6c>
        EXTI->IMR1 &= ~(iocurrent);
 8001428:	6834      	ldr	r4, [r6, #0]
 800142a:	ea24 040e 	bic.w	r4, r4, lr
 800142e:	6034      	str	r4, [r6, #0]
        EXTI->EMR1 &= ~(iocurrent);
 8001430:	6874      	ldr	r4, [r6, #4]
 8001432:	ea24 040e 	bic.w	r4, r4, lr
 8001436:	6074      	str	r4, [r6, #4]
        EXTI->FTSR1 &= ~(iocurrent);
 8001438:	68f4      	ldr	r4, [r6, #12]
 800143a:	ea24 040e 	bic.w	r4, r4, lr
 800143e:	60f4      	str	r4, [r6, #12]
        EXTI->RTSR1 &= ~(iocurrent);
 8001440:	68b4      	ldr	r4, [r6, #8]
 8001442:	ea24 040e 	bic.w	r4, r4, lr
 8001446:	60b4      	str	r4, [r6, #8]
        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
 8001448:	68ac      	ldr	r4, [r5, #8]
 800144a:	ea24 0408 	bic.w	r4, r4, r8
 800144e:	60ac      	str	r4, [r5, #8]
      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
 8001450:	6805      	ldr	r5, [r0, #0]
 8001452:	005c      	lsls	r4, r3, #1
 8001454:	fa0a f404 	lsl.w	r4, sl, r4

      /* Configure the default Alternate Function in current IO */
      GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u));
 8001458:	ea4f 0cd3 	mov.w	ip, r3, lsr #3
      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
 800145c:	4325      	orrs	r5, r4
 800145e:	eb00 0c8c 	add.w	ip, r0, ip, lsl #2
 8001462:	6005      	str	r5, [r0, #0]
      GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u));
 8001464:	f003 0507 	and.w	r5, r3, #7
 8001468:	f8dc e020 	ldr.w	lr, [ip, #32]
 800146c:	00ad      	lsls	r5, r5, #2
 800146e:	fa09 f505 	lsl.w	r5, r9, r5
 8001472:	ea2e 0505 	bic.w	r5, lr, r5
 8001476:	f8cc 5020 	str.w	r5, [ip, #32]

      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
 800147a:	68c5      	ldr	r5, [r0, #12]
 800147c:	ea25 0504 	bic.w	r5, r5, r4
 8001480:	60c5      	str	r5, [r0, #12]

      /* Configure the default value IO Output Type */
      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position);
 8001482:	6845      	ldr	r5, [r0, #4]
 8001484:	ea25 0202 	bic.w	r2, r5, r2
 8001488:	6042      	str	r2, [r0, #4]

      /* Configure the default value for IO Speed */
      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
 800148a:	6882      	ldr	r2, [r0, #8]
 800148c:	ea22 0404 	bic.w	r4, r2, r4
 8001490:	6084      	str	r4, [r0, #8]
    }

    position++;
 8001492:	3301      	adds	r3, #1
  while ((GPIO_Pin >> position) != 0U)
 8001494:	fa31 f203 	lsrs.w	r2, r1, r3
 8001498:	d018      	beq.n	80014cc <HAL_GPIO_DeInit+0xe8>
    iocurrent = (GPIO_Pin) & (1UL << position);
 800149a:	2201      	movs	r2, #1
 800149c:	409a      	lsls	r2, r3
    if (iocurrent != 0x00u)
 800149e:	ea12 0e01 	ands.w	lr, r2, r1
 80014a2:	d0f6      	beq.n	8001492 <HAL_GPIO_DeInit+0xae>
      tmp = SYSCFG->EXTICR[position >> 2U];
 80014a4:	f023 0503 	bic.w	r5, r3, #3
 80014a8:	f105 4580 	add.w	r5, r5, #1073741824	; 0x40000000
 80014ac:	f505 3580 	add.w	r5, r5, #65536	; 0x10000
      tmp &= (0x0FUL << (4U * (position & 0x03U)));
 80014b0:	f003 0403 	and.w	r4, r3, #3
      tmp = SYSCFG->EXTICR[position >> 2U];
 80014b4:	f8d5 c008 	ldr.w	ip, [r5, #8]
      tmp &= (0x0FUL << (4U * (position & 0x03U)));
 80014b8:	00a4      	lsls	r4, r4, #2
 80014ba:	fa09 f804 	lsl.w	r8, r9, r4
      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
 80014be:	f1b0 4f90 	cmp.w	r0, #1207959552	; 0x48000000
      tmp &= (0x0FUL << (4U * (position & 0x03U)));
 80014c2:	ea08 0c0c 	and.w	ip, r8, ip
      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
 80014c6:	d19b      	bne.n	8001400 <HAL_GPIO_DeInit+0x1c>
 80014c8:	2400      	movs	r4, #0
 80014ca:	e7ab      	b.n	8001424 <HAL_GPIO_DeInit+0x40>
  }
}
 80014cc:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
 80014d0:	2701      	movs	r7, #1
 80014d2:	fa07 f404 	lsl.w	r4, r7, r4
 80014d6:	e7a5      	b.n	8001424 <HAL_GPIO_DeInit+0x40>
 80014d8:	2702      	movs	r7, #2
 80014da:	fa07 f404 	lsl.w	r4, r7, r4
 80014de:	e7a1      	b.n	8001424 <HAL_GPIO_DeInit+0x40>
 80014e0:	fa0a f404 	lsl.w	r4, sl, r4
 80014e4:	e79e      	b.n	8001424 <HAL_GPIO_DeInit+0x40>
 80014e6:	2704      	movs	r7, #4
 80014e8:	fa07 f404 	lsl.w	r4, r7, r4
 80014ec:	e79a      	b.n	8001424 <HAL_GPIO_DeInit+0x40>
 80014ee:	4770      	bx	lr
 80014f0:	40010400 	.word	0x40010400
 80014f4:	48000800 	.word	0x48000800
 80014f8:	48000c00 	.word	0x48000c00
 80014fc:	48001000 	.word	0x48001000
 8001500:	48001400 	.word	0x48001400
 8001504:	48000400 	.word	0x48000400

08001508 <HAL_GPIO_ReadPin>:
  GPIO_PinState bitstatus;

  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
 8001508:	6903      	ldr	r3, [r0, #16]
 800150a:	4219      	tst	r1, r3
  else
  {
    bitstatus = GPIO_PIN_RESET;
  }
  return bitstatus;
}
 800150c:	bf14      	ite	ne
 800150e:	2001      	movne	r0, #1
 8001510:	2000      	moveq	r0, #0
 8001512:	4770      	bx	lr

08001514 <HAL_GPIO_WritePin>:
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8001514:	b10a      	cbz	r2, 800151a <HAL_GPIO_WritePin+0x6>
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin;
 8001516:	6181      	str	r1, [r0, #24]
 8001518:	4770      	bx	lr
  }
  else
  {
    GPIOx->BRR = (uint32_t)GPIO_Pin;
 800151a:	6281      	str	r1, [r0, #40]	; 0x28
  }
}
 800151c:	4770      	bx	lr
 800151e:	bf00      	nop

08001520 <HAL_GPIO_TogglePin>:

  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  /* get current Output Data Register value */
  odr = GPIOx->ODR;
 8001520:	6943      	ldr	r3, [r0, #20]

  /* Set selected pins that were at low level, and reset ones that were high */
  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
 8001522:	ea01 0203 	and.w	r2, r1, r3
 8001526:	ea21 0103 	bic.w	r1, r1, r3
 800152a:	ea41 4102 	orr.w	r1, r1, r2, lsl #16
 800152e:	6181      	str	r1, [r0, #24]
}
 8001530:	4770      	bx	lr
 8001532:	bf00      	nop

08001534 <HAL_PWREx_ControlVoltageScaling>:
  *        cleared before returning the status. If the flag is not cleared within
  *        50 microseconds, HAL_TIMEOUT status is reported.
  * @retval HAL Status
  */
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
 8001534:	b410      	push	{r4}
  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));

  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
  {
    /* If current range is range 2 */
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
 8001536:	4a3b      	ldr	r2, [pc, #236]	; (8001624 <HAL_PWREx_ControlVoltageScaling+0xf0>)
  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
 8001538:	b970      	cbnz	r0, 8001558 <HAL_PWREx_ControlVoltageScaling+0x24>
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
 800153a:	6813      	ldr	r3, [r2, #0]
 800153c:	f403 63c0 	and.w	r3, r3, #1536	; 0x600
 8001540:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    {
      /* Make sure Range 1 Boost is enabled */
      CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
 8001544:	f8d2 3080 	ldr.w	r3, [r2, #128]	; 0x80
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
 8001548:	d023      	beq.n	8001592 <HAL_PWREx_ControlVoltageScaling+0x5e>
    }
    /* If current range is range 1 normal or boost mode */
    else
    {
      /* Enable Range 1 Boost (no issue if bit already reset) */
      CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
 800154a:	f423 7380 	bic.w	r3, r3, #256	; 0x100
    /* No need to wait for VOSF to be cleared for this transition */
    /* PWR_CR5_R1MODE bit setting has no effect in Range 2        */
  }

  return HAL_OK;
}
 800154e:	f85d 4b04 	ldr.w	r4, [sp], #4
      CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
 8001552:	f8c2 3080 	str.w	r3, [r2, #128]	; 0x80
}
 8001556:	4770      	bx	lr
  else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
 8001558:	f5b0 7f00 	cmp.w	r0, #512	; 0x200
 800155c:	d009      	beq.n	8001572 <HAL_PWREx_ControlVoltageScaling+0x3e>
    MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
 800155e:	6813      	ldr	r3, [r2, #0]
}
 8001560:	f85d 4b04 	ldr.w	r4, [sp], #4
    MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
 8001564:	f423 63c0 	bic.w	r3, r3, #1536	; 0x600
 8001568:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
  return HAL_OK;
 800156c:	2000      	movs	r0, #0
    MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
 800156e:	6013      	str	r3, [r2, #0]
}
 8001570:	4770      	bx	lr
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
 8001572:	6813      	ldr	r3, [r2, #0]
 8001574:	f403 63c0 	and.w	r3, r3, #1536	; 0x600
 8001578:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
      SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
 800157c:	f8d2 3080 	ldr.w	r3, [r2, #128]	; 0x80
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
 8001580:	d02f      	beq.n	80015e2 <HAL_PWREx_ControlVoltageScaling+0xae>
      SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
 8001582:	f443 7380 	orr.w	r3, r3, #256	; 0x100
  return HAL_OK;
 8001586:	2000      	movs	r0, #0
}
 8001588:	f85d 4b04 	ldr.w	r4, [sp], #4
      SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
 800158c:	f8c2 3080 	str.w	r3, [r2, #128]	; 0x80
}
 8001590:	4770      	bx	lr
      CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
 8001592:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 8001596:	f8c2 3080 	str.w	r3, [r2, #128]	; 0x80
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
 800159a:	6811      	ldr	r1, [r2, #0]
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 800159c:	4c22      	ldr	r4, [pc, #136]	; (8001628 <HAL_PWREx_ControlVoltageScaling+0xf4>)
 800159e:	4823      	ldr	r0, [pc, #140]	; (800162c <HAL_PWREx_ControlVoltageScaling+0xf8>)
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
 80015a0:	f421 61c0 	bic.w	r1, r1, #1536	; 0x600
 80015a4:	f441 7100 	orr.w	r1, r1, #512	; 0x200
 80015a8:	6011      	str	r1, [r2, #0]
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 80015aa:	6823      	ldr	r3, [r4, #0]
 80015ac:	2132      	movs	r1, #50	; 0x32
 80015ae:	fb01 f303 	mul.w	r3, r1, r3
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 80015b2:	6951      	ldr	r1, [r2, #20]
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 80015b4:	fba0 0303 	umull	r0, r3, r0, r3
 80015b8:	0c9b      	lsrs	r3, r3, #18
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 80015ba:	0548      	lsls	r0, r1, #21
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 80015bc:	f103 0301 	add.w	r3, r3, #1
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 80015c0:	d506      	bpl.n	80015d0 <HAL_PWREx_ControlVoltageScaling+0x9c>
 80015c2:	e000      	b.n	80015c6 <HAL_PWREx_ControlVoltageScaling+0x92>
 80015c4:	b123      	cbz	r3, 80015d0 <HAL_PWREx_ControlVoltageScaling+0x9c>
 80015c6:	6951      	ldr	r1, [r2, #20]
 80015c8:	0549      	lsls	r1, r1, #21
        wait_loop_index--;
 80015ca:	f103 33ff 	add.w	r3, r3, #4294967295	; 0xffffffff
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 80015ce:	d4f9      	bmi.n	80015c4 <HAL_PWREx_ControlVoltageScaling+0x90>
      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
 80015d0:	4b14      	ldr	r3, [pc, #80]	; (8001624 <HAL_PWREx_ControlVoltageScaling+0xf0>)
 80015d2:	695b      	ldr	r3, [r3, #20]
 80015d4:	055c      	lsls	r4, r3, #21
  return HAL_OK;
 80015d6:	bf54      	ite	pl
 80015d8:	2000      	movpl	r0, #0
        return HAL_TIMEOUT;
 80015da:	2003      	movmi	r0, #3
}
 80015dc:	f85d 4b04 	ldr.w	r4, [sp], #4
 80015e0:	4770      	bx	lr
      SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
 80015e2:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 80015e6:	f8c2 3080 	str.w	r3, [r2, #128]	; 0x80
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
 80015ea:	6811      	ldr	r1, [r2, #0]
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 80015ec:	4c0e      	ldr	r4, [pc, #56]	; (8001628 <HAL_PWREx_ControlVoltageScaling+0xf4>)
 80015ee:	480f      	ldr	r0, [pc, #60]	; (800162c <HAL_PWREx_ControlVoltageScaling+0xf8>)
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
 80015f0:	f421 61c0 	bic.w	r1, r1, #1536	; 0x600
 80015f4:	f441 7100 	orr.w	r1, r1, #512	; 0x200
 80015f8:	6011      	str	r1, [r2, #0]
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 80015fa:	6823      	ldr	r3, [r4, #0]
 80015fc:	2132      	movs	r1, #50	; 0x32
 80015fe:	fb01 f303 	mul.w	r3, r1, r3
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 8001602:	6951      	ldr	r1, [r2, #20]
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 8001604:	fba0 0303 	umull	r0, r3, r0, r3
 8001608:	0c9b      	lsrs	r3, r3, #18
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 800160a:	0548      	lsls	r0, r1, #21
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 800160c:	f103 0301 	add.w	r3, r3, #1
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 8001610:	d5de      	bpl.n	80015d0 <HAL_PWREx_ControlVoltageScaling+0x9c>
 8001612:	e001      	b.n	8001618 <HAL_PWREx_ControlVoltageScaling+0xe4>
 8001614:	2b00      	cmp	r3, #0
 8001616:	d0db      	beq.n	80015d0 <HAL_PWREx_ControlVoltageScaling+0x9c>
 8001618:	6951      	ldr	r1, [r2, #20]
 800161a:	0549      	lsls	r1, r1, #21
        wait_loop_index--;
 800161c:	f103 33ff 	add.w	r3, r3, #4294967295	; 0xffffffff
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 8001620:	d5d6      	bpl.n	80015d0 <HAL_PWREx_ControlVoltageScaling+0x9c>
 8001622:	e7f7      	b.n	8001614 <HAL_PWREx_ControlVoltageScaling+0xe0>
 8001624:	40007000 	.word	0x40007000
 8001628:	20000000 	.word	0x20000000
 800162c:	431bde83 	.word	0x431bde83

08001630 <HAL_PWREx_DisableUCPDDeadBattery>:
  * @retval None
  */
void HAL_PWREx_DisableUCPDDeadBattery(void)
{
  /* Write 1 to disable the USB Type-C dead battery pull-down behavior */
  SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
 8001630:	4a02      	ldr	r2, [pc, #8]	; (800163c <HAL_PWREx_DisableUCPDDeadBattery+0xc>)
 8001632:	6893      	ldr	r3, [r2, #8]
 8001634:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
 8001638:	6093      	str	r3, [r2, #8]
}
 800163a:	4770      	bx	lr
 800163c:	40007000 	.word	0x40007000

08001640 <HAL_RCC_OscConfig>:
  uint32_t tickstart;
  uint32_t temp_sysclksrc;
  uint32_t temp_pllckcfg;

  /* Check Null pointer */
  if (RCC_OscInitStruct == NULL)
 8001640:	2800      	cmp	r0, #0
 8001642:	f000 8200 	beq.w	8001a46 <HAL_RCC_OscConfig+0x406>
{
 8001646:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  /*------------------------------- HSE Configuration ------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 800164a:	6803      	ldr	r3, [r0, #0]
 800164c:	07d9      	lsls	r1, r3, #31
{
 800164e:	b082      	sub	sp, #8
 8001650:	4604      	mov	r4, r0
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8001652:	d52d      	bpl.n	80016b0 <HAL_RCC_OscConfig+0x70>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 8001654:	49af      	ldr	r1, [pc, #700]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
 8001656:	688a      	ldr	r2, [r1, #8]
    temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
 8001658:	68c9      	ldr	r1, [r1, #12]
    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 800165a:	f002 020c 	and.w	r2, r2, #12

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
 800165e:	2a0c      	cmp	r2, #12
 8001660:	f000 8106 	beq.w	8001870 <HAL_RCC_OscConfig+0x230>
 8001664:	2a08      	cmp	r2, #8
 8001666:	f000 8108 	beq.w	800187a <HAL_RCC_OscConfig+0x23a>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 800166a:	6863      	ldr	r3, [r4, #4]
 800166c:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8001670:	f000 8177 	beq.w	8001962 <HAL_RCC_OscConfig+0x322>
 8001674:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8001678:	f000 81d8 	beq.w	8001a2c <HAL_RCC_OscConfig+0x3ec>
 800167c:	4da5      	ldr	r5, [pc, #660]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
 800167e:	682a      	ldr	r2, [r5, #0]
 8001680:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
 8001684:	602a      	str	r2, [r5, #0]
 8001686:	682a      	ldr	r2, [r5, #0]
 8001688:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 800168c:	602a      	str	r2, [r5, #0]

      /* Check the HSE State */
      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 800168e:	2b00      	cmp	r3, #0
 8001690:	f040 816c 	bne.w	800196c <HAL_RCC_OscConfig+0x32c>
        }
      }
      else
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001694:	f7ff fb20 	bl	8000cd8 <HAL_GetTick>
 8001698:	4606      	mov	r6, r0

        /* Wait till HSE is disabled */
        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 800169a:	e005      	b.n	80016a8 <HAL_RCC_OscConfig+0x68>
        {
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 800169c:	f7ff fb1c 	bl	8000cd8 <HAL_GetTick>
 80016a0:	1b80      	subs	r0, r0, r6
 80016a2:	2864      	cmp	r0, #100	; 0x64
 80016a4:	f200 817f 	bhi.w	80019a6 <HAL_RCC_OscConfig+0x366>
        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 80016a8:	682b      	ldr	r3, [r5, #0]
 80016aa:	039f      	lsls	r7, r3, #14
 80016ac:	d4f6      	bmi.n	800169c <HAL_RCC_OscConfig+0x5c>
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 80016ae:	6823      	ldr	r3, [r4, #0]
 80016b0:	079e      	lsls	r6, r3, #30
 80016b2:	d528      	bpl.n	8001706 <HAL_RCC_OscConfig+0xc6>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 80016b4:	4a97      	ldr	r2, [pc, #604]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
 80016b6:	6893      	ldr	r3, [r2, #8]
    temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
 80016b8:	68d2      	ldr	r2, [r2, #12]
    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 80016ba:	f003 030c 	and.w	r3, r3, #12
    if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
 80016be:	2b0c      	cmp	r3, #12
 80016c0:	f000 8130 	beq.w	8001924 <HAL_RCC_OscConfig+0x2e4>
 80016c4:	2b04      	cmp	r3, #4
 80016c6:	f000 8132 	beq.w	800192e <HAL_RCC_OscConfig+0x2ee>
      }
    }
    else
    {
      /* Check the HSI State */
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 80016ca:	68e3      	ldr	r3, [r4, #12]
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 80016cc:	4d91      	ldr	r5, [pc, #580]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 80016ce:	2b00      	cmp	r3, #0
 80016d0:	f000 815a 	beq.w	8001988 <HAL_RCC_OscConfig+0x348>
        __HAL_RCC_HSI_ENABLE();
 80016d4:	682b      	ldr	r3, [r5, #0]
 80016d6:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 80016da:	602b      	str	r3, [r5, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80016dc:	f7ff fafc 	bl	8000cd8 <HAL_GetTick>
 80016e0:	4606      	mov	r6, r0

        /* Wait till HSI is ready */
        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 80016e2:	e005      	b.n	80016f0 <HAL_RCC_OscConfig+0xb0>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 80016e4:	f7ff faf8 	bl	8000cd8 <HAL_GetTick>
 80016e8:	1b80      	subs	r0, r0, r6
 80016ea:	2802      	cmp	r0, #2
 80016ec:	f200 815b 	bhi.w	80019a6 <HAL_RCC_OscConfig+0x366>
        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 80016f0:	682b      	ldr	r3, [r5, #0]
 80016f2:	0558      	lsls	r0, r3, #21
 80016f4:	d5f6      	bpl.n	80016e4 <HAL_RCC_OscConfig+0xa4>
            return HAL_TIMEOUT;
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80016f6:	686b      	ldr	r3, [r5, #4]
 80016f8:	6922      	ldr	r2, [r4, #16]
 80016fa:	f023 43fe 	bic.w	r3, r3, #2130706432	; 0x7f000000
 80016fe:	ea43 6302 	orr.w	r3, r3, r2, lsl #24
 8001702:	606b      	str	r3, [r5, #4]
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8001704:	6823      	ldr	r3, [r4, #0]
 8001706:	071a      	lsls	r2, r3, #28
 8001708:	d519      	bpl.n	800173e <HAL_RCC_OscConfig+0xfe>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 800170a:	6963      	ldr	r3, [r4, #20]
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 800170c:	4d81      	ldr	r5, [pc, #516]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 800170e:	2b00      	cmp	r3, #0
 8001710:	f000 8099 	beq.w	8001846 <HAL_RCC_OscConfig+0x206>
      __HAL_RCC_LSI_ENABLE();
 8001714:	f8d5 3094 	ldr.w	r3, [r5, #148]	; 0x94
 8001718:	f043 0301 	orr.w	r3, r3, #1
 800171c:	f8c5 3094 	str.w	r3, [r5, #148]	; 0x94

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8001720:	f7ff fada 	bl	8000cd8 <HAL_GetTick>
 8001724:	4606      	mov	r6, r0

      /* Wait till LSI is ready */
      while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8001726:	e005      	b.n	8001734 <HAL_RCC_OscConfig+0xf4>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8001728:	f7ff fad6 	bl	8000cd8 <HAL_GetTick>
 800172c:	1b80      	subs	r0, r0, r6
 800172e:	2802      	cmp	r0, #2
 8001730:	f200 8139 	bhi.w	80019a6 <HAL_RCC_OscConfig+0x366>
      while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8001734:	f8d5 3094 	ldr.w	r3, [r5, #148]	; 0x94
 8001738:	079b      	lsls	r3, r3, #30
 800173a:	d5f5      	bpl.n	8001728 <HAL_RCC_OscConfig+0xe8>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 800173c:	6823      	ldr	r3, [r4, #0]
 800173e:	075e      	lsls	r6, r3, #29
 8001740:	d541      	bpl.n	80017c6 <HAL_RCC_OscConfig+0x186>
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain if necessary */
    if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
 8001742:	4b74      	ldr	r3, [pc, #464]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
 8001744:	6d9a      	ldr	r2, [r3, #88]	; 0x58
 8001746:	00d5      	lsls	r5, r2, #3
 8001748:	f100 8131 	bmi.w	80019ae <HAL_RCC_OscConfig+0x36e>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 800174c:	6d9a      	ldr	r2, [r3, #88]	; 0x58
 800174e:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
 8001752:	659a      	str	r2, [r3, #88]	; 0x58
 8001754:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8001756:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 800175a:	9301      	str	r3, [sp, #4]
 800175c:	9b01      	ldr	r3, [sp, #4]
      pwrclkchanged = SET;
 800175e:	2501      	movs	r5, #1
    }

    if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8001760:	4e6d      	ldr	r6, [pc, #436]	; (8001918 <HAL_RCC_OscConfig+0x2d8>)
 8001762:	6833      	ldr	r3, [r6, #0]
 8001764:	05d8      	lsls	r0, r3, #23
 8001766:	f140 8150 	bpl.w	8001a0a <HAL_RCC_OscConfig+0x3ca>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 800176a:	68a3      	ldr	r3, [r4, #8]
 800176c:	2b01      	cmp	r3, #1
 800176e:	f000 8120 	beq.w	80019b2 <HAL_RCC_OscConfig+0x372>
 8001772:	2b05      	cmp	r3, #5
 8001774:	f000 8169 	beq.w	8001a4a <HAL_RCC_OscConfig+0x40a>
 8001778:	4e66      	ldr	r6, [pc, #408]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
 800177a:	f8d6 2090 	ldr.w	r2, [r6, #144]	; 0x90
 800177e:	f022 0201 	bic.w	r2, r2, #1
 8001782:	f8c6 2090 	str.w	r2, [r6, #144]	; 0x90
 8001786:	f8d6 2090 	ldr.w	r2, [r6, #144]	; 0x90
 800178a:	f022 0204 	bic.w	r2, r2, #4
 800178e:	f8c6 2090 	str.w	r2, [r6, #144]	; 0x90

    /* Check the LSE State */
    if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 8001792:	2b00      	cmp	r3, #0
 8001794:	f040 8114 	bne.w	80019c0 <HAL_RCC_OscConfig+0x380>
      }
    }
    else
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8001798:	f7ff fa9e 	bl	8000cd8 <HAL_GetTick>

      /* Wait till LSE is disabled */
      while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
      {
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800179c:	f241 3888 	movw	r8, #5000	; 0x1388
      tickstart = HAL_GetTick();
 80017a0:	4607      	mov	r7, r0
      while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 80017a2:	e005      	b.n	80017b0 <HAL_RCC_OscConfig+0x170>
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80017a4:	f7ff fa98 	bl	8000cd8 <HAL_GetTick>
 80017a8:	1bc0      	subs	r0, r0, r7
 80017aa:	4540      	cmp	r0, r8
 80017ac:	f200 80fb 	bhi.w	80019a6 <HAL_RCC_OscConfig+0x366>
      while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 80017b0:	f8d6 3090 	ldr.w	r3, [r6, #144]	; 0x90
 80017b4:	079b      	lsls	r3, r3, #30
 80017b6:	d4f5      	bmi.n	80017a4 <HAL_RCC_OscConfig+0x164>
        }
      }
    }

    /* Restore clock configuration if changed */
    if (pwrclkchanged == SET)
 80017b8:	b125      	cbz	r5, 80017c4 <HAL_RCC_OscConfig+0x184>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 80017ba:	4a56      	ldr	r2, [pc, #344]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
 80017bc:	6d93      	ldr	r3, [r2, #88]	; 0x58
 80017be:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 80017c2:	6593      	str	r3, [r2, #88]	; 0x58
    }
  }

  /*------------------------------ HSI48 Configuration -----------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
 80017c4:	6823      	ldr	r3, [r4, #0]
 80017c6:	069d      	lsls	r5, r3, #26
 80017c8:	d518      	bpl.n	80017fc <HAL_RCC_OscConfig+0x1bc>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));

    /* Check the HSI48 State */
    if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
 80017ca:	69a3      	ldr	r3, [r4, #24]
    {
      /* Enable the Internal Low Speed oscillator (HSI48). */
      __HAL_RCC_HSI48_ENABLE();
 80017cc:	4d51      	ldr	r5, [pc, #324]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
    if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
 80017ce:	2b00      	cmp	r3, #0
 80017d0:	f000 8107 	beq.w	80019e2 <HAL_RCC_OscConfig+0x3a2>
      __HAL_RCC_HSI48_ENABLE();
 80017d4:	f8d5 3098 	ldr.w	r3, [r5, #152]	; 0x98
 80017d8:	f043 0301 	orr.w	r3, r3, #1
 80017dc:	f8c5 3098 	str.w	r3, [r5, #152]	; 0x98

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 80017e0:	f7ff fa7a 	bl	8000cd8 <HAL_GetTick>
 80017e4:	4606      	mov	r6, r0

      /* Wait till HSI48 is ready */
      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
 80017e6:	e005      	b.n	80017f4 <HAL_RCC_OscConfig+0x1b4>
      {
        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 80017e8:	f7ff fa76 	bl	8000cd8 <HAL_GetTick>
 80017ec:	1b80      	subs	r0, r0, r6
 80017ee:	2802      	cmp	r0, #2
 80017f0:	f200 80d9 	bhi.w	80019a6 <HAL_RCC_OscConfig+0x366>
      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
 80017f4:	f8d5 3098 	ldr.w	r3, [r5, #152]	; 0x98
 80017f8:	0798      	lsls	r0, r3, #30
 80017fa:	d5f5      	bpl.n	80017e8 <HAL_RCC_OscConfig+0x1a8>

  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));

  if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
 80017fc:	69e0      	ldr	r0, [r4, #28]
 80017fe:	2800      	cmp	r0, #0
 8001800:	f000 8083 	beq.w	800190a <HAL_RCC_OscConfig+0x2ca>
  {
    /* Check if the PLL is used as system clock or not */
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
 8001804:	4d43      	ldr	r5, [pc, #268]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
 8001806:	68ab      	ldr	r3, [r5, #8]
 8001808:	f003 030c 	and.w	r3, r3, #12
 800180c:	2b0c      	cmp	r3, #12
 800180e:	f000 812a 	beq.w	8001a66 <HAL_RCC_OscConfig+0x426>
        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8001812:	682b      	ldr	r3, [r5, #0]
      if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
 8001814:	2802      	cmp	r0, #2
        __HAL_RCC_PLL_DISABLE();
 8001816:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
 800181a:	602b      	str	r3, [r5, #0]
      if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
 800181c:	d03a      	beq.n	8001894 <HAL_RCC_OscConfig+0x254>
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800181e:	f7ff fa5b 	bl	8000cd8 <HAL_GetTick>
 8001822:	4604      	mov	r4, r0

        /* Wait till PLL is disabled */
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8001824:	e005      	b.n	8001832 <HAL_RCC_OscConfig+0x1f2>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8001826:	f7ff fa57 	bl	8000cd8 <HAL_GetTick>
 800182a:	1b00      	subs	r0, r0, r4
 800182c:	2802      	cmp	r0, #2
 800182e:	f200 80ba 	bhi.w	80019a6 <HAL_RCC_OscConfig+0x366>
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8001832:	682b      	ldr	r3, [r5, #0]
 8001834:	f013 7300 	ands.w	r3, r3, #33554432	; 0x2000000
 8001838:	d1f5      	bne.n	8001826 <HAL_RCC_OscConfig+0x1e6>
            return HAL_TIMEOUT;
          }
        }

        /* Unselect PLL clock source and disable outputs to save power */
        RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
 800183a:	68e9      	ldr	r1, [r5, #12]
 800183c:	4a37      	ldr	r2, [pc, #220]	; (800191c <HAL_RCC_OscConfig+0x2dc>)
 800183e:	400a      	ands	r2, r1
      }
    }
  }
  }

  return HAL_OK;
 8001840:	4618      	mov	r0, r3
        RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
 8001842:	60ea      	str	r2, [r5, #12]
 8001844:	e062      	b.n	800190c <HAL_RCC_OscConfig+0x2cc>
      __HAL_RCC_LSI_DISABLE();
 8001846:	f8d5 3094 	ldr.w	r3, [r5, #148]	; 0x94
 800184a:	f023 0301 	bic.w	r3, r3, #1
 800184e:	f8c5 3094 	str.w	r3, [r5, #148]	; 0x94
      tickstart = HAL_GetTick();
 8001852:	f7ff fa41 	bl	8000cd8 <HAL_GetTick>
 8001856:	4606      	mov	r6, r0
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 8001858:	e005      	b.n	8001866 <HAL_RCC_OscConfig+0x226>
        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 800185a:	f7ff fa3d 	bl	8000cd8 <HAL_GetTick>
 800185e:	1b80      	subs	r0, r0, r6
 8001860:	2802      	cmp	r0, #2
 8001862:	f200 80a0 	bhi.w	80019a6 <HAL_RCC_OscConfig+0x366>
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 8001866:	f8d5 3094 	ldr.w	r3, [r5, #148]	; 0x94
 800186a:	079f      	lsls	r7, r3, #30
 800186c:	d4f5      	bmi.n	800185a <HAL_RCC_OscConfig+0x21a>
 800186e:	e765      	b.n	800173c <HAL_RCC_OscConfig+0xfc>
    temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
 8001870:	f001 0103 	and.w	r1, r1, #3
    if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
 8001874:	2903      	cmp	r1, #3
 8001876:	f47f aef8 	bne.w	800166a <HAL_RCC_OscConfig+0x2a>
      if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 800187a:	4a26      	ldr	r2, [pc, #152]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
 800187c:	6812      	ldr	r2, [r2, #0]
 800187e:	0392      	lsls	r2, r2, #14
 8001880:	f57f af16 	bpl.w	80016b0 <HAL_RCC_OscConfig+0x70>
 8001884:	6862      	ldr	r2, [r4, #4]
 8001886:	2a00      	cmp	r2, #0
 8001888:	f47f af12 	bne.w	80016b0 <HAL_RCC_OscConfig+0x70>
        return HAL_ERROR;
 800188c:	2001      	movs	r0, #1
}
 800188e:	b002      	add	sp, #8
 8001890:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        tickstart = HAL_GetTick();
 8001894:	f7ff fa20 	bl	8000cd8 <HAL_GetTick>
 8001898:	4606      	mov	r6, r0
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 800189a:	e004      	b.n	80018a6 <HAL_RCC_OscConfig+0x266>
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 800189c:	f7ff fa1c 	bl	8000cd8 <HAL_GetTick>
 80018a0:	1b80      	subs	r0, r0, r6
 80018a2:	2802      	cmp	r0, #2
 80018a4:	d87f      	bhi.n	80019a6 <HAL_RCC_OscConfig+0x366>
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 80018a6:	682b      	ldr	r3, [r5, #0]
 80018a8:	019a      	lsls	r2, r3, #6
 80018aa:	d4f7      	bmi.n	800189c <HAL_RCC_OscConfig+0x25c>
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 80018ac:	68e9      	ldr	r1, [r5, #12]
 80018ae:	4b1c      	ldr	r3, [pc, #112]	; (8001920 <HAL_RCC_OscConfig+0x2e0>)
 80018b0:	6a22      	ldr	r2, [r4, #32]
 80018b2:	6a60      	ldr	r0, [r4, #36]	; 0x24
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 80018b4:	4e17      	ldr	r6, [pc, #92]	; (8001914 <HAL_RCC_OscConfig+0x2d4>)
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 80018b6:	400b      	ands	r3, r1
 80018b8:	4313      	orrs	r3, r2
 80018ba:	e9d4 120a 	ldrd	r1, r2, [r4, #40]	; 0x28
 80018be:	ea43 2301 	orr.w	r3, r3, r1, lsl #8
 80018c2:	ea43 63c2 	orr.w	r3, r3, r2, lsl #27
 80018c6:	e9d4 120c 	ldrd	r1, r2, [r4, #48]	; 0x30
 80018ca:	3801      	subs	r0, #1
 80018cc:	0849      	lsrs	r1, r1, #1
 80018ce:	ea43 1300 	orr.w	r3, r3, r0, lsl #4
 80018d2:	3901      	subs	r1, #1
 80018d4:	0852      	lsrs	r2, r2, #1
 80018d6:	ea43 5341 	orr.w	r3, r3, r1, lsl #21
 80018da:	3a01      	subs	r2, #1
 80018dc:	ea43 6342 	orr.w	r3, r3, r2, lsl #25
 80018e0:	60eb      	str	r3, [r5, #12]
        __HAL_RCC_PLL_ENABLE();
 80018e2:	682b      	ldr	r3, [r5, #0]
 80018e4:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
 80018e8:	602b      	str	r3, [r5, #0]
         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
 80018ea:	68eb      	ldr	r3, [r5, #12]
 80018ec:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
 80018f0:	60eb      	str	r3, [r5, #12]
        tickstart = HAL_GetTick();
 80018f2:	f7ff f9f1 	bl	8000cd8 <HAL_GetTick>
 80018f6:	4604      	mov	r4, r0
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 80018f8:	e004      	b.n	8001904 <HAL_RCC_OscConfig+0x2c4>
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 80018fa:	f7ff f9ed 	bl	8000cd8 <HAL_GetTick>
 80018fe:	1b00      	subs	r0, r0, r4
 8001900:	2802      	cmp	r0, #2
 8001902:	d850      	bhi.n	80019a6 <HAL_RCC_OscConfig+0x366>
        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001904:	6833      	ldr	r3, [r6, #0]
 8001906:	019b      	lsls	r3, r3, #6
 8001908:	d5f7      	bpl.n	80018fa <HAL_RCC_OscConfig+0x2ba>
  return HAL_OK;
 800190a:	2000      	movs	r0, #0
}
 800190c:	b002      	add	sp, #8
 800190e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8001912:	bf00      	nop
 8001914:	40021000 	.word	0x40021000
 8001918:	40007000 	.word	0x40007000
 800191c:	feeefffc 	.word	0xfeeefffc
 8001920:	019f800c 	.word	0x019f800c
    temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
 8001924:	f002 0203 	and.w	r2, r2, #3
    if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
 8001928:	2a02      	cmp	r2, #2
 800192a:	f47f aece 	bne.w	80016ca <HAL_RCC_OscConfig+0x8a>
      if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 800192e:	4b68      	ldr	r3, [pc, #416]	; (8001ad0 <HAL_RCC_OscConfig+0x490>)
 8001930:	681b      	ldr	r3, [r3, #0]
 8001932:	055d      	lsls	r5, r3, #21
 8001934:	d502      	bpl.n	800193c <HAL_RCC_OscConfig+0x2fc>
 8001936:	68e3      	ldr	r3, [r4, #12]
 8001938:	2b00      	cmp	r3, #0
 800193a:	d0a7      	beq.n	800188c <HAL_RCC_OscConfig+0x24c>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 800193c:	4a64      	ldr	r2, [pc, #400]	; (8001ad0 <HAL_RCC_OscConfig+0x490>)
 800193e:	6920      	ldr	r0, [r4, #16]
 8001940:	6853      	ldr	r3, [r2, #4]
        if (HAL_InitTick(uwTickPrio) != HAL_OK)
 8001942:	4964      	ldr	r1, [pc, #400]	; (8001ad4 <HAL_RCC_OscConfig+0x494>)
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8001944:	f023 43fe 	bic.w	r3, r3, #2130706432	; 0x7f000000
 8001948:	ea43 6300 	orr.w	r3, r3, r0, lsl #24
 800194c:	6053      	str	r3, [r2, #4]
        if (HAL_InitTick(uwTickPrio) != HAL_OK)
 800194e:	6808      	ldr	r0, [r1, #0]
 8001950:	f7ff f980 	bl	8000c54 <HAL_InitTick>
 8001954:	2800      	cmp	r0, #0
 8001956:	d199      	bne.n	800188c <HAL_RCC_OscConfig+0x24c>
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8001958:	6823      	ldr	r3, [r4, #0]
 800195a:	071a      	lsls	r2, r3, #28
 800195c:	f57f aeef 	bpl.w	800173e <HAL_RCC_OscConfig+0xfe>
 8001960:	e6d3      	b.n	800170a <HAL_RCC_OscConfig+0xca>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8001962:	4a5b      	ldr	r2, [pc, #364]	; (8001ad0 <HAL_RCC_OscConfig+0x490>)
 8001964:	6813      	ldr	r3, [r2, #0]
 8001966:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 800196a:	6013      	str	r3, [r2, #0]
        tickstart = HAL_GetTick();
 800196c:	f7ff f9b4 	bl	8000cd8 <HAL_GetTick>
        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8001970:	4e57      	ldr	r6, [pc, #348]	; (8001ad0 <HAL_RCC_OscConfig+0x490>)
        tickstart = HAL_GetTick();
 8001972:	4605      	mov	r5, r0
        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8001974:	e004      	b.n	8001980 <HAL_RCC_OscConfig+0x340>
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8001976:	f7ff f9af 	bl	8000cd8 <HAL_GetTick>
 800197a:	1b40      	subs	r0, r0, r5
 800197c:	2864      	cmp	r0, #100	; 0x64
 800197e:	d812      	bhi.n	80019a6 <HAL_RCC_OscConfig+0x366>
        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8001980:	6833      	ldr	r3, [r6, #0]
 8001982:	039b      	lsls	r3, r3, #14
 8001984:	d5f7      	bpl.n	8001976 <HAL_RCC_OscConfig+0x336>
 8001986:	e692      	b.n	80016ae <HAL_RCC_OscConfig+0x6e>
        __HAL_RCC_HSI_DISABLE();
 8001988:	682b      	ldr	r3, [r5, #0]
 800198a:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 800198e:	602b      	str	r3, [r5, #0]
        tickstart = HAL_GetTick();
 8001990:	f7ff f9a2 	bl	8000cd8 <HAL_GetTick>
 8001994:	4606      	mov	r6, r0
        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 8001996:	682b      	ldr	r3, [r5, #0]
 8001998:	0559      	lsls	r1, r3, #21
 800199a:	d5dd      	bpl.n	8001958 <HAL_RCC_OscConfig+0x318>
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 800199c:	f7ff f99c 	bl	8000cd8 <HAL_GetTick>
 80019a0:	1b80      	subs	r0, r0, r6
 80019a2:	2802      	cmp	r0, #2
 80019a4:	d9f7      	bls.n	8001996 <HAL_RCC_OscConfig+0x356>
            return HAL_TIMEOUT;
 80019a6:	2003      	movs	r0, #3
}
 80019a8:	b002      	add	sp, #8
 80019aa:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    FlagStatus       pwrclkchanged = RESET;
 80019ae:	2500      	movs	r5, #0
 80019b0:	e6d6      	b.n	8001760 <HAL_RCC_OscConfig+0x120>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 80019b2:	4a47      	ldr	r2, [pc, #284]	; (8001ad0 <HAL_RCC_OscConfig+0x490>)
 80019b4:	f8d2 3090 	ldr.w	r3, [r2, #144]	; 0x90
 80019b8:	f043 0301 	orr.w	r3, r3, #1
 80019bc:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
      tickstart = HAL_GetTick();
 80019c0:	f7ff f98a 	bl	8000cd8 <HAL_GetTick>
      while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 80019c4:	4f42      	ldr	r7, [pc, #264]	; (8001ad0 <HAL_RCC_OscConfig+0x490>)
      tickstart = HAL_GetTick();
 80019c6:	4606      	mov	r6, r0
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80019c8:	f241 3888 	movw	r8, #5000	; 0x1388
      while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 80019cc:	e004      	b.n	80019d8 <HAL_RCC_OscConfig+0x398>
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80019ce:	f7ff f983 	bl	8000cd8 <HAL_GetTick>
 80019d2:	1b80      	subs	r0, r0, r6
 80019d4:	4540      	cmp	r0, r8
 80019d6:	d8e6      	bhi.n	80019a6 <HAL_RCC_OscConfig+0x366>
      while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 80019d8:	f8d7 3090 	ldr.w	r3, [r7, #144]	; 0x90
 80019dc:	079a      	lsls	r2, r3, #30
 80019de:	d5f6      	bpl.n	80019ce <HAL_RCC_OscConfig+0x38e>
 80019e0:	e6ea      	b.n	80017b8 <HAL_RCC_OscConfig+0x178>
      __HAL_RCC_HSI48_DISABLE();
 80019e2:	f8d5 3098 	ldr.w	r3, [r5, #152]	; 0x98
 80019e6:	f023 0301 	bic.w	r3, r3, #1
 80019ea:	f8c5 3098 	str.w	r3, [r5, #152]	; 0x98
      tickstart = HAL_GetTick();
 80019ee:	f7ff f973 	bl	8000cd8 <HAL_GetTick>
 80019f2:	4606      	mov	r6, r0
      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
 80019f4:	e004      	b.n	8001a00 <HAL_RCC_OscConfig+0x3c0>
        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 80019f6:	f7ff f96f 	bl	8000cd8 <HAL_GetTick>
 80019fa:	1b80      	subs	r0, r0, r6
 80019fc:	2802      	cmp	r0, #2
 80019fe:	d8d2      	bhi.n	80019a6 <HAL_RCC_OscConfig+0x366>
      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
 8001a00:	f8d5 3098 	ldr.w	r3, [r5, #152]	; 0x98
 8001a04:	0799      	lsls	r1, r3, #30
 8001a06:	d4f6      	bmi.n	80019f6 <HAL_RCC_OscConfig+0x3b6>
 8001a08:	e6f8      	b.n	80017fc <HAL_RCC_OscConfig+0x1bc>
      SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8001a0a:	6833      	ldr	r3, [r6, #0]
 8001a0c:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8001a10:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 8001a12:	f7ff f961 	bl	8000cd8 <HAL_GetTick>
 8001a16:	4607      	mov	r7, r0
      while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8001a18:	6833      	ldr	r3, [r6, #0]
 8001a1a:	05d9      	lsls	r1, r3, #23
 8001a1c:	f53f aea5 	bmi.w	800176a <HAL_RCC_OscConfig+0x12a>
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8001a20:	f7ff f95a 	bl	8000cd8 <HAL_GetTick>
 8001a24:	1bc0      	subs	r0, r0, r7
 8001a26:	2802      	cmp	r0, #2
 8001a28:	d9f6      	bls.n	8001a18 <HAL_RCC_OscConfig+0x3d8>
 8001a2a:	e7bc      	b.n	80019a6 <HAL_RCC_OscConfig+0x366>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8001a2c:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
 8001a30:	f5a3 333c 	sub.w	r3, r3, #192512	; 0x2f000
 8001a34:	681a      	ldr	r2, [r3, #0]
 8001a36:	f442 2280 	orr.w	r2, r2, #262144	; 0x40000
 8001a3a:	601a      	str	r2, [r3, #0]
 8001a3c:	681a      	ldr	r2, [r3, #0]
 8001a3e:	f442 3280 	orr.w	r2, r2, #65536	; 0x10000
 8001a42:	601a      	str	r2, [r3, #0]
      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 8001a44:	e792      	b.n	800196c <HAL_RCC_OscConfig+0x32c>
    return HAL_ERROR;
 8001a46:	2001      	movs	r0, #1
}
 8001a48:	4770      	bx	lr
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8001a4a:	4b21      	ldr	r3, [pc, #132]	; (8001ad0 <HAL_RCC_OscConfig+0x490>)
 8001a4c:	f8d3 2090 	ldr.w	r2, [r3, #144]	; 0x90
 8001a50:	f042 0204 	orr.w	r2, r2, #4
 8001a54:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
 8001a58:	f8d3 2090 	ldr.w	r2, [r3, #144]	; 0x90
 8001a5c:	f042 0201 	orr.w	r2, r2, #1
 8001a60:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 8001a64:	e7ac      	b.n	80019c0 <HAL_RCC_OscConfig+0x380>
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8001a66:	2801      	cmp	r0, #1
 8001a68:	f43f af50 	beq.w	800190c <HAL_RCC_OscConfig+0x2cc>
      temp_pllckcfg = RCC->PLLCFGR;
 8001a6c:	68eb      	ldr	r3, [r5, #12]
      if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8001a6e:	6a22      	ldr	r2, [r4, #32]
 8001a70:	f003 0103 	and.w	r1, r3, #3
 8001a74:	4291      	cmp	r1, r2
 8001a76:	f47f af09 	bne.w	800188c <HAL_RCC_OscConfig+0x24c>
         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
 8001a7a:	6a61      	ldr	r1, [r4, #36]	; 0x24
 8001a7c:	f003 02f0 	and.w	r2, r3, #240	; 0xf0
 8001a80:	3901      	subs	r1, #1
      if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8001a82:	ebb2 1f01 	cmp.w	r2, r1, lsl #4
 8001a86:	f47f af01 	bne.w	800188c <HAL_RCC_OscConfig+0x24c>
         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
 8001a8a:	6aa1      	ldr	r1, [r4, #40]	; 0x28
 8001a8c:	f403 42fe 	and.w	r2, r3, #32512	; 0x7f00
         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
 8001a90:	ebb2 2f01 	cmp.w	r2, r1, lsl #8
 8001a94:	f47f aefa 	bne.w	800188c <HAL_RCC_OscConfig+0x24c>
         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
 8001a98:	6ae1      	ldr	r1, [r4, #44]	; 0x2c
 8001a9a:	f003 4278 	and.w	r2, r3, #4160749568	; 0xf8000000
         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
 8001a9e:	ebb2 6fc1 	cmp.w	r2, r1, lsl #27
 8001aa2:	f47f aef3 	bne.w	800188c <HAL_RCC_OscConfig+0x24c>
         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
 8001aa6:	6b22      	ldr	r2, [r4, #48]	; 0x30
 8001aa8:	0852      	lsrs	r2, r2, #1
 8001aaa:	f403 01c0 	and.w	r1, r3, #6291456	; 0x600000
 8001aae:	3a01      	subs	r2, #1
         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
 8001ab0:	ebb1 5f42 	cmp.w	r1, r2, lsl #21
 8001ab4:	f47f aeea 	bne.w	800188c <HAL_RCC_OscConfig+0x24c>
         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
 8001ab8:	6b62      	ldr	r2, [r4, #52]	; 0x34
 8001aba:	0852      	lsrs	r2, r2, #1
 8001abc:	f003 63c0 	and.w	r3, r3, #100663296	; 0x6000000
 8001ac0:	3a01      	subs	r2, #1
         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
 8001ac2:	ebb3 6f42 	cmp.w	r3, r2, lsl #25
        return HAL_ERROR;
 8001ac6:	bf14      	ite	ne
 8001ac8:	2001      	movne	r0, #1
 8001aca:	2000      	moveq	r0, #0
 8001acc:	e71e      	b.n	800190c <HAL_RCC_OscConfig+0x2cc>
 8001ace:	bf00      	nop
 8001ad0:	40021000 	.word	0x40021000
 8001ad4:	20000008 	.word	0x20000008

08001ad8 <HAL_RCC_GetSysClockFreq>:
uint32_t HAL_RCC_GetSysClockFreq(void)
{
  uint32_t pllvco, pllsource, pllr, pllm;
  uint32_t sysclockfreq;

  if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
 8001ad8:	4b18      	ldr	r3, [pc, #96]	; (8001b3c <HAL_RCC_GetSysClockFreq+0x64>)
 8001ada:	689a      	ldr	r2, [r3, #8]
 8001adc:	f002 020c 	and.w	r2, r2, #12
 8001ae0:	2a04      	cmp	r2, #4
 8001ae2:	d027      	beq.n	8001b34 <HAL_RCC_GetSysClockFreq+0x5c>
  {
    /* HSI used as system clock source */
    sysclockfreq = HSI_VALUE;
  }
  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
 8001ae4:	689a      	ldr	r2, [r3, #8]
 8001ae6:	f002 020c 	and.w	r2, r2, #12
 8001aea:	2a08      	cmp	r2, #8
 8001aec:	d024      	beq.n	8001b38 <HAL_RCC_GetSysClockFreq+0x60>
  {
    /* HSE used as system clock source */
    sysclockfreq = HSE_VALUE;
  }
  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
 8001aee:	689a      	ldr	r2, [r3, #8]
 8001af0:	f002 020c 	and.w	r2, r2, #12
 8001af4:	2a0c      	cmp	r2, #12
 8001af6:	d001      	beq.n	8001afc <HAL_RCC_GetSysClockFreq+0x24>
    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
    sysclockfreq = pllvco/pllr;
  }
  else
  {
    sysclockfreq = 0U;
 8001af8:	2000      	movs	r0, #0
  }

  return sysclockfreq;
}
 8001afa:	4770      	bx	lr
    pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
 8001afc:	68d9      	ldr	r1, [r3, #12]
    pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
 8001afe:	68d8      	ldr	r0, [r3, #12]
    pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
 8001b00:	f001 0103 	and.w	r1, r1, #3
    switch (pllsource)
 8001b04:	2903      	cmp	r1, #3
    pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
 8001b06:	f3c0 1003 	ubfx	r0, r0, #4, #4
 8001b0a:	f100 0201 	add.w	r2, r0, #1
      pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001b0e:	68d8      	ldr	r0, [r3, #12]
      pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001b10:	bf0c      	ite	eq
 8001b12:	4b0b      	ldreq	r3, [pc, #44]	; (8001b40 <HAL_RCC_GetSysClockFreq+0x68>)
      pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001b14:	4b0b      	ldrne	r3, [pc, #44]	; (8001b44 <HAL_RCC_GetSysClockFreq+0x6c>)
 8001b16:	fbb3 f2f2 	udiv	r2, r3, r2
    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
 8001b1a:	4b08      	ldr	r3, [pc, #32]	; (8001b3c <HAL_RCC_GetSysClockFreq+0x64>)
 8001b1c:	68db      	ldr	r3, [r3, #12]
 8001b1e:	f3c3 6341 	ubfx	r3, r3, #25, #2
      pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001b22:	f3c0 2006 	ubfx	r0, r0, #8, #7
    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
 8001b26:	3301      	adds	r3, #1
      pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001b28:	fb02 f000 	mul.w	r0, r2, r0
    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
 8001b2c:	005b      	lsls	r3, r3, #1
    sysclockfreq = pllvco/pllr;
 8001b2e:	fbb0 f0f3 	udiv	r0, r0, r3
  return sysclockfreq;
 8001b32:	4770      	bx	lr
    sysclockfreq = HSI_VALUE;
 8001b34:	4803      	ldr	r0, [pc, #12]	; (8001b44 <HAL_RCC_GetSysClockFreq+0x6c>)
 8001b36:	4770      	bx	lr
    sysclockfreq = HSE_VALUE;
 8001b38:	4801      	ldr	r0, [pc, #4]	; (8001b40 <HAL_RCC_GetSysClockFreq+0x68>)
 8001b3a:	4770      	bx	lr
 8001b3c:	40021000 	.word	0x40021000
 8001b40:	007a1200 	.word	0x007a1200
 8001b44:	00f42400 	.word	0x00f42400

08001b48 <HAL_RCC_ClockConfig>:
  if (RCC_ClkInitStruct == NULL)
 8001b48:	2800      	cmp	r0, #0
 8001b4a:	f000 80ee 	beq.w	8001d2a <HAL_RCC_ClockConfig+0x1e2>
  if (FLatency > __HAL_FLASH_GET_LATENCY())
 8001b4e:	4a7f      	ldr	r2, [pc, #508]	; (8001d4c <HAL_RCC_ClockConfig+0x204>)
{
 8001b50:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  if (FLatency > __HAL_FLASH_GET_LATENCY())
 8001b54:	6813      	ldr	r3, [r2, #0]
 8001b56:	f003 030f 	and.w	r3, r3, #15
 8001b5a:	428b      	cmp	r3, r1
 8001b5c:	460d      	mov	r5, r1
 8001b5e:	4604      	mov	r4, r0
 8001b60:	d20c      	bcs.n	8001b7c <HAL_RCC_ClockConfig+0x34>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8001b62:	6813      	ldr	r3, [r2, #0]
 8001b64:	f023 030f 	bic.w	r3, r3, #15
 8001b68:	430b      	orrs	r3, r1
 8001b6a:	6013      	str	r3, [r2, #0]
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 8001b6c:	6813      	ldr	r3, [r2, #0]
 8001b6e:	f003 030f 	and.w	r3, r3, #15
 8001b72:	428b      	cmp	r3, r1
 8001b74:	d002      	beq.n	8001b7c <HAL_RCC_ClockConfig+0x34>
    return HAL_ERROR;
 8001b76:	2001      	movs	r0, #1
}
 8001b78:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8001b7c:	6823      	ldr	r3, [r4, #0]
 8001b7e:	07df      	lsls	r7, r3, #31
 8001b80:	d563      	bpl.n	8001c4a <HAL_RCC_ClockConfig+0x102>
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8001b82:	6862      	ldr	r2, [r4, #4]
 8001b84:	2a03      	cmp	r2, #3
 8001b86:	f000 809a 	beq.w	8001cbe <HAL_RCC_ClockConfig+0x176>
        if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8001b8a:	4b71      	ldr	r3, [pc, #452]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
      if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8001b8c:	2a02      	cmp	r2, #2
        if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8001b8e:	681b      	ldr	r3, [r3, #0]
      if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8001b90:	f000 8091 	beq.w	8001cb6 <HAL_RCC_ClockConfig+0x16e>
        if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8001b94:	055b      	lsls	r3, r3, #21
 8001b96:	d5ee      	bpl.n	8001b76 <HAL_RCC_ClockConfig+0x2e>
      pllfreq = HAL_RCC_GetSysClockFreq();
 8001b98:	f7ff ff9e 	bl	8001ad8 <HAL_RCC_GetSysClockFreq>
      if(pllfreq > 80000000U)
 8001b9c:	4b6d      	ldr	r3, [pc, #436]	; (8001d54 <HAL_RCC_ClockConfig+0x20c>)
 8001b9e:	4298      	cmp	r0, r3
 8001ba0:	f200 80c5 	bhi.w	8001d2e <HAL_RCC_ClockConfig+0x1e6>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 8001ba4:	6862      	ldr	r2, [r4, #4]
  uint32_t hpre = RCC_SYSCLK_DIV1;
 8001ba6:	f04f 0900 	mov.w	r9, #0
    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 8001baa:	4e69      	ldr	r6, [pc, #420]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
 8001bac:	68b3      	ldr	r3, [r6, #8]
 8001bae:	f023 0303 	bic.w	r3, r3, #3
 8001bb2:	431a      	orrs	r2, r3
 8001bb4:	60b2      	str	r2, [r6, #8]
    tickstart = HAL_GetTick();
 8001bb6:	f7ff f88f 	bl	8000cd8 <HAL_GetTick>
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001bba:	f241 3888 	movw	r8, #5000	; 0x1388
    tickstart = HAL_GetTick();
 8001bbe:	4607      	mov	r7, r0
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8001bc0:	e004      	b.n	8001bcc <HAL_RCC_ClockConfig+0x84>
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001bc2:	f7ff f889 	bl	8000cd8 <HAL_GetTick>
 8001bc6:	1bc0      	subs	r0, r0, r7
 8001bc8:	4540      	cmp	r0, r8
 8001bca:	d871      	bhi.n	8001cb0 <HAL_RCC_ClockConfig+0x168>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8001bcc:	68b3      	ldr	r3, [r6, #8]
 8001bce:	6862      	ldr	r2, [r4, #4]
 8001bd0:	f003 030c 	and.w	r3, r3, #12
 8001bd4:	ebb3 0f82 	cmp.w	r3, r2, lsl #2
 8001bd8:	d1f3      	bne.n	8001bc2 <HAL_RCC_ClockConfig+0x7a>
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8001bda:	6823      	ldr	r3, [r4, #0]
 8001bdc:	079f      	lsls	r7, r3, #30
 8001bde:	d436      	bmi.n	8001c4e <HAL_RCC_ClockConfig+0x106>
    if(hpre == RCC_SYSCLK_DIV2)
 8001be0:	f1b9 0f80 	cmp.w	r9, #128	; 0x80
 8001be4:	d103      	bne.n	8001bee <HAL_RCC_ClockConfig+0xa6>
      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
 8001be6:	68b3      	ldr	r3, [r6, #8]
 8001be8:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
 8001bec:	60b3      	str	r3, [r6, #8]
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 8001bee:	4e57      	ldr	r6, [pc, #348]	; (8001d4c <HAL_RCC_ClockConfig+0x204>)
 8001bf0:	6833      	ldr	r3, [r6, #0]
 8001bf2:	f003 030f 	and.w	r3, r3, #15
 8001bf6:	42ab      	cmp	r3, r5
 8001bf8:	d846      	bhi.n	8001c88 <HAL_RCC_ClockConfig+0x140>
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8001bfa:	6823      	ldr	r3, [r4, #0]
 8001bfc:	075a      	lsls	r2, r3, #29
 8001bfe:	d506      	bpl.n	8001c0e <HAL_RCC_ClockConfig+0xc6>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8001c00:	4953      	ldr	r1, [pc, #332]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
 8001c02:	68e0      	ldr	r0, [r4, #12]
 8001c04:	688a      	ldr	r2, [r1, #8]
 8001c06:	f422 62e0 	bic.w	r2, r2, #1792	; 0x700
 8001c0a:	4302      	orrs	r2, r0
 8001c0c:	608a      	str	r2, [r1, #8]
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8001c0e:	071b      	lsls	r3, r3, #28
 8001c10:	d507      	bpl.n	8001c22 <HAL_RCC_ClockConfig+0xda>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 8001c12:	4a4f      	ldr	r2, [pc, #316]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
 8001c14:	6921      	ldr	r1, [r4, #16]
 8001c16:	6893      	ldr	r3, [r2, #8]
 8001c18:	f423 5360 	bic.w	r3, r3, #14336	; 0x3800
 8001c1c:	ea43 03c1 	orr.w	r3, r3, r1, lsl #3
 8001c20:	6093      	str	r3, [r2, #8]
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
 8001c22:	f7ff ff59 	bl	8001ad8 <HAL_RCC_GetSysClockFreq>
 8001c26:	4a4a      	ldr	r2, [pc, #296]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
 8001c28:	4c4b      	ldr	r4, [pc, #300]	; (8001d58 <HAL_RCC_ClockConfig+0x210>)
 8001c2a:	6892      	ldr	r2, [r2, #8]
 8001c2c:	494b      	ldr	r1, [pc, #300]	; (8001d5c <HAL_RCC_ClockConfig+0x214>)
 8001c2e:	f3c2 1203 	ubfx	r2, r2, #4, #4
 8001c32:	4603      	mov	r3, r0
 8001c34:	5ca2      	ldrb	r2, [r4, r2]
  return HAL_InitTick(uwTickPrio);
 8001c36:	484a      	ldr	r0, [pc, #296]	; (8001d60 <HAL_RCC_ClockConfig+0x218>)
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
 8001c38:	f002 021f 	and.w	r2, r2, #31
 8001c3c:	40d3      	lsrs	r3, r2
 8001c3e:	600b      	str	r3, [r1, #0]
  return HAL_InitTick(uwTickPrio);
 8001c40:	6800      	ldr	r0, [r0, #0]
}
 8001c42:	e8bd 43f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  return HAL_InitTick(uwTickPrio);
 8001c46:	f7ff b805 	b.w	8000c54 <HAL_InitTick>
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8001c4a:	079e      	lsls	r6, r3, #30
 8001c4c:	d5cf      	bpl.n	8001bee <HAL_RCC_ClockConfig+0xa6>
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8001c4e:	0758      	lsls	r0, r3, #29
 8001c50:	d504      	bpl.n	8001c5c <HAL_RCC_ClockConfig+0x114>
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 8001c52:	493f      	ldr	r1, [pc, #252]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
 8001c54:	688a      	ldr	r2, [r1, #8]
 8001c56:	f442 62e0 	orr.w	r2, r2, #1792	; 0x700
 8001c5a:	608a      	str	r2, [r1, #8]
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8001c5c:	0719      	lsls	r1, r3, #28
 8001c5e:	d506      	bpl.n	8001c6e <HAL_RCC_ClockConfig+0x126>
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
 8001c60:	4a3b      	ldr	r2, [pc, #236]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
 8001c62:	6893      	ldr	r3, [r2, #8]
 8001c64:	f423 537c 	bic.w	r3, r3, #16128	; 0x3f00
 8001c68:	f443 63e0 	orr.w	r3, r3, #1792	; 0x700
 8001c6c:	6093      	str	r3, [r2, #8]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8001c6e:	4a38      	ldr	r2, [pc, #224]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
 8001c70:	68a1      	ldr	r1, [r4, #8]
 8001c72:	6893      	ldr	r3, [r2, #8]
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 8001c74:	4e35      	ldr	r6, [pc, #212]	; (8001d4c <HAL_RCC_ClockConfig+0x204>)
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8001c76:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
 8001c7a:	430b      	orrs	r3, r1
 8001c7c:	6093      	str	r3, [r2, #8]
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 8001c7e:	6833      	ldr	r3, [r6, #0]
 8001c80:	f003 030f 	and.w	r3, r3, #15
 8001c84:	42ab      	cmp	r3, r5
 8001c86:	d9b8      	bls.n	8001bfa <HAL_RCC_ClockConfig+0xb2>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8001c88:	6833      	ldr	r3, [r6, #0]
 8001c8a:	f023 030f 	bic.w	r3, r3, #15
 8001c8e:	432b      	orrs	r3, r5
 8001c90:	6033      	str	r3, [r6, #0]
    tickstart = HAL_GetTick();
 8001c92:	f7ff f821 	bl	8000cd8 <HAL_GetTick>
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001c96:	f241 3888 	movw	r8, #5000	; 0x1388
    tickstart = HAL_GetTick();
 8001c9a:	4607      	mov	r7, r0
    while (__HAL_FLASH_GET_LATENCY() != FLatency)
 8001c9c:	6833      	ldr	r3, [r6, #0]
 8001c9e:	f003 030f 	and.w	r3, r3, #15
 8001ca2:	42ab      	cmp	r3, r5
 8001ca4:	d0a9      	beq.n	8001bfa <HAL_RCC_ClockConfig+0xb2>
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001ca6:	f7ff f817 	bl	8000cd8 <HAL_GetTick>
 8001caa:	1bc0      	subs	r0, r0, r7
 8001cac:	4540      	cmp	r0, r8
 8001cae:	d9f5      	bls.n	8001c9c <HAL_RCC_ClockConfig+0x154>
        return HAL_TIMEOUT;
 8001cb0:	2003      	movs	r0, #3
}
 8001cb2:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8001cb6:	039a      	lsls	r2, r3, #14
 8001cb8:	f53f af6e 	bmi.w	8001b98 <HAL_RCC_ClockConfig+0x50>
 8001cbc:	e75b      	b.n	8001b76 <HAL_RCC_ClockConfig+0x2e>
      if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001cbe:	4924      	ldr	r1, [pc, #144]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
 8001cc0:	6808      	ldr	r0, [r1, #0]
 8001cc2:	0180      	lsls	r0, r0, #6
 8001cc4:	f57f af57 	bpl.w	8001b76 <HAL_RCC_ClockConfig+0x2e>
  uint32_t sysclockfreq;

  /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
     SYSCLK = PLL_VCO / PLLR
   */
  pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
 8001cc8:	68ce      	ldr	r6, [r1, #12]
  pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
 8001cca:	68c8      	ldr	r0, [r1, #12]
    pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
    break;

  case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
  default:
    pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001ccc:	68c9      	ldr	r1, [r1, #12]
      if(pllfreq > 80000000U)
 8001cce:	4f21      	ldr	r7, [pc, #132]	; (8001d54 <HAL_RCC_ClockConfig+0x20c>)
  pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
 8001cd0:	f006 0603 	and.w	r6, r6, #3
  switch (pllsource)
 8001cd4:	2e03      	cmp	r6, #3
  pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
 8001cd6:	f3c0 1003 	ubfx	r0, r0, #4, #4
    pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001cda:	bf0c      	ite	eq
 8001cdc:	4e21      	ldreq	r6, [pc, #132]	; (8001d64 <HAL_RCC_ClockConfig+0x21c>)
    pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001cde:	4e22      	ldrne	r6, [pc, #136]	; (8001d68 <HAL_RCC_ClockConfig+0x220>)
  pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
 8001ce0:	3001      	adds	r0, #1
    pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001ce2:	fbb6 f0f0 	udiv	r0, r6, r0
    break;
  }

  pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
 8001ce6:	4e1a      	ldr	r6, [pc, #104]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
    pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
 8001ce8:	f3c1 2106 	ubfx	r1, r1, #8, #7
 8001cec:	fb00 f101 	mul.w	r1, r0, r1
  pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
 8001cf0:	68f0      	ldr	r0, [r6, #12]
 8001cf2:	f3c0 6041 	ubfx	r0, r0, #25, #2
 8001cf6:	3001      	adds	r0, #1
 8001cf8:	0040      	lsls	r0, r0, #1
  sysclockfreq = pllvco/pllr;
 8001cfa:	fbb1 f1f0 	udiv	r1, r1, r0
      if(pllfreq > 80000000U)
 8001cfe:	42b9      	cmp	r1, r7
 8001d00:	d920      	bls.n	8001d44 <HAL_RCC_ClockConfig+0x1fc>
        if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
 8001d02:	68b1      	ldr	r1, [r6, #8]
 8001d04:	f011 0ff0 	tst.w	r1, #240	; 0xf0
 8001d08:	d005      	beq.n	8001d16 <HAL_RCC_ClockConfig+0x1ce>
 8001d0a:	f013 0902 	ands.w	r9, r3, #2
 8001d0e:	f43f af4c 	beq.w	8001baa <HAL_RCC_ClockConfig+0x62>
            (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
 8001d12:	68a3      	ldr	r3, [r4, #8]
 8001d14:	b9b3      	cbnz	r3, 8001d44 <HAL_RCC_ClockConfig+0x1fc>
          MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
 8001d16:	490e      	ldr	r1, [pc, #56]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
 8001d18:	688b      	ldr	r3, [r1, #8]
 8001d1a:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
 8001d1e:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8001d22:	608b      	str	r3, [r1, #8]
          hpre = RCC_SYSCLK_DIV2;
 8001d24:	f04f 0980 	mov.w	r9, #128	; 0x80
 8001d28:	e73f      	b.n	8001baa <HAL_RCC_ClockConfig+0x62>
    return HAL_ERROR;
 8001d2a:	2001      	movs	r0, #1
}
 8001d2c:	4770      	bx	lr
        MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
 8001d2e:	4a08      	ldr	r2, [pc, #32]	; (8001d50 <HAL_RCC_ClockConfig+0x208>)
 8001d30:	6893      	ldr	r3, [r2, #8]
        hpre = RCC_SYSCLK_DIV2;
 8001d32:	f04f 0980 	mov.w	r9, #128	; 0x80
        MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
 8001d36:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
 8001d3a:	ea43 0309 	orr.w	r3, r3, r9
 8001d3e:	6093      	str	r3, [r2, #8]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 8001d40:	6862      	ldr	r2, [r4, #4]
 8001d42:	e732      	b.n	8001baa <HAL_RCC_ClockConfig+0x62>
  uint32_t hpre = RCC_SYSCLK_DIV1;
 8001d44:	f04f 0900 	mov.w	r9, #0
 8001d48:	e72f      	b.n	8001baa <HAL_RCC_ClockConfig+0x62>
 8001d4a:	bf00      	nop
 8001d4c:	40022000 	.word	0x40022000
 8001d50:	40021000 	.word	0x40021000
 8001d54:	04c4b400 	.word	0x04c4b400
 8001d58:	08003068 	.word	0x08003068
 8001d5c:	20000000 	.word	0x20000000
 8001d60:	20000008 	.word	0x20000008
 8001d64:	007a1200 	.word	0x007a1200
 8001d68:	00f42400 	.word	0x00f42400

08001d6c <HAL_RCC_GetPCLK1Freq>:
  return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
 8001d6c:	4b05      	ldr	r3, [pc, #20]	; (8001d84 <HAL_RCC_GetPCLK1Freq+0x18>)
 8001d6e:	4a06      	ldr	r2, [pc, #24]	; (8001d88 <HAL_RCC_GetPCLK1Freq+0x1c>)
 8001d70:	689b      	ldr	r3, [r3, #8]
  return SystemCoreClock;
 8001d72:	4906      	ldr	r1, [pc, #24]	; (8001d8c <HAL_RCC_GetPCLK1Freq+0x20>)
  return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
 8001d74:	f3c3 2302 	ubfx	r3, r3, #8, #3
 8001d78:	6808      	ldr	r0, [r1, #0]
 8001d7a:	5cd3      	ldrb	r3, [r2, r3]
 8001d7c:	f003 031f 	and.w	r3, r3, #31
}
 8001d80:	40d8      	lsrs	r0, r3
 8001d82:	4770      	bx	lr
 8001d84:	40021000 	.word	0x40021000
 8001d88:	08003078 	.word	0x08003078
 8001d8c:	20000000 	.word	0x20000000

08001d90 <HAL_RCC_GetPCLK2Freq>:
  return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
 8001d90:	4b05      	ldr	r3, [pc, #20]	; (8001da8 <HAL_RCC_GetPCLK2Freq+0x18>)
 8001d92:	4a06      	ldr	r2, [pc, #24]	; (8001dac <HAL_RCC_GetPCLK2Freq+0x1c>)
 8001d94:	689b      	ldr	r3, [r3, #8]
  return SystemCoreClock;
 8001d96:	4906      	ldr	r1, [pc, #24]	; (8001db0 <HAL_RCC_GetPCLK2Freq+0x20>)
  return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
 8001d98:	f3c3 23c2 	ubfx	r3, r3, #11, #3
 8001d9c:	6808      	ldr	r0, [r1, #0]
 8001d9e:	5cd3      	ldrb	r3, [r2, r3]
 8001da0:	f003 031f 	and.w	r3, r3, #31
}
 8001da4:	40d8      	lsrs	r0, r3
 8001da6:	4770      	bx	lr
 8001da8:	40021000 	.word	0x40021000
 8001dac:	08003078 	.word	0x08003078
 8001db0:	20000000 	.word	0x20000000

08001db4 <HAL_RCCEx_PeriphCLKConfig>:
  *         the RTC clock source: in this case the access to Backup domain is enabled.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef const *PeriphClkInit)
{
 8001db4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

  /*-------------------------- RTC clock source configuration ----------------------*/
  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 8001db8:	6803      	ldr	r3, [r0, #0]
{
 8001dba:	4604      	mov	r4, r0
  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 8001dbc:	f413 2000 	ands.w	r0, r3, #524288	; 0x80000
{
 8001dc0:	b082      	sub	sp, #8
  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 8001dc2:	d056      	beq.n	8001e72 <HAL_RCCEx_PeriphCLKConfig+0xbe>
    
    /* Check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));

    /* Enable Power Clock */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8001dc4:	4b9f      	ldr	r3, [pc, #636]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001dc6:	6d9a      	ldr	r2, [r3, #88]	; 0x58
 8001dc8:	00d5      	lsls	r5, r2, #3
 8001dca:	f140 810c 	bpl.w	8001fe6 <HAL_RCCEx_PeriphCLKConfig+0x232>
    FlagStatus       pwrclkchanged = RESET;
 8001dce:	2700      	movs	r7, #0
      __HAL_RCC_PWR_CLK_ENABLE();
      pwrclkchanged = SET;
    }
      
    /* Enable write access to Backup domain */
    SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8001dd0:	4d9d      	ldr	r5, [pc, #628]	; (8002048 <HAL_RCCEx_PeriphCLKConfig+0x294>)
 8001dd2:	682b      	ldr	r3, [r5, #0]
 8001dd4:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8001dd8:	602b      	str	r3, [r5, #0]

    /* Wait for Backup domain Write protection disable */
    tickstart = HAL_GetTick();
 8001dda:	f7fe ff7d 	bl	8000cd8 <HAL_GetTick>
 8001dde:	4606      	mov	r6, r0

    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
 8001de0:	e005      	b.n	8001dee <HAL_RCCEx_PeriphCLKConfig+0x3a>
    {
      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8001de2:	f7fe ff79 	bl	8000cd8 <HAL_GetTick>
 8001de6:	1b83      	subs	r3, r0, r6
 8001de8:	2b02      	cmp	r3, #2
 8001dea:	f200 8107 	bhi.w	8001ffc <HAL_RCCEx_PeriphCLKConfig+0x248>
    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
 8001dee:	682b      	ldr	r3, [r5, #0]
 8001df0:	05d8      	lsls	r0, r3, #23
 8001df2:	d5f6      	bpl.n	8001de2 <HAL_RCCEx_PeriphCLKConfig+0x2e>
    }

    if(ret == HAL_OK)
    { 
      /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
      tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
 8001df4:	4d93      	ldr	r5, [pc, #588]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001df6:	f8d5 3090 	ldr.w	r3, [r5, #144]	; 0x90
      
      if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
 8001dfa:	f413 7340 	ands.w	r3, r3, #768	; 0x300
 8001dfe:	d027      	beq.n	8001e50 <HAL_RCCEx_PeriphCLKConfig+0x9c>
 8001e00:	6c22      	ldr	r2, [r4, #64]	; 0x40
 8001e02:	429a      	cmp	r2, r3
 8001e04:	d025      	beq.n	8001e52 <HAL_RCCEx_PeriphCLKConfig+0x9e>
      {
        /* Store the content of BDCR register before the reset of Backup Domain */
        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
 8001e06:	f8d5 1090 	ldr.w	r1, [r5, #144]	; 0x90
        /* RTC Clock selection can be changed only if the Backup Domain is reset */
        __HAL_RCC_BACKUPRESET_FORCE();
 8001e0a:	f8d5 3090 	ldr.w	r3, [r5, #144]	; 0x90
 8001e0e:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8001e12:	f8c5 3090 	str.w	r3, [r5, #144]	; 0x90
        __HAL_RCC_BACKUPRESET_RELEASE();
 8001e16:	f8d5 3090 	ldr.w	r3, [r5, #144]	; 0x90
 8001e1a:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8001e1e:	f8c5 3090 	str.w	r3, [r5, #144]	; 0x90
        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
 8001e22:	f421 7340 	bic.w	r3, r1, #768	; 0x300
        /* Restore the Content of BDCR register */
        RCC->BDCR = tmpregister;
      }

      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
 8001e26:	07c9      	lsls	r1, r1, #31
        RCC->BDCR = tmpregister;
 8001e28:	f8c5 3090 	str.w	r3, [r5, #144]	; 0x90
      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
 8001e2c:	f140 8108 	bpl.w	8002040 <HAL_RCCEx_PeriphCLKConfig+0x28c>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001e30:	f7fe ff52 	bl	8000cd8 <HAL_GetTick>

        /* Wait till LSE is ready */
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
        {
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8001e34:	f241 3888 	movw	r8, #5000	; 0x1388
        tickstart = HAL_GetTick();
 8001e38:	4606      	mov	r6, r0
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8001e3a:	e005      	b.n	8001e48 <HAL_RCCEx_PeriphCLKConfig+0x94>
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8001e3c:	f7fe ff4c 	bl	8000cd8 <HAL_GetTick>
 8001e40:	1b80      	subs	r0, r0, r6
 8001e42:	4540      	cmp	r0, r8
 8001e44:	f200 80da 	bhi.w	8001ffc <HAL_RCCEx_PeriphCLKConfig+0x248>
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8001e48:	f8d5 3090 	ldr.w	r3, [r5, #144]	; 0x90
 8001e4c:	079b      	lsls	r3, r3, #30
 8001e4e:	d5f5      	bpl.n	8001e3c <HAL_RCCEx_PeriphCLKConfig+0x88>
      }
      
      if(ret == HAL_OK)
      {
        /* Apply new RTC clock source selection */
        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 8001e50:	6c23      	ldr	r3, [r4, #64]	; 0x40
 8001e52:	497c      	ldr	r1, [pc, #496]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001e54:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90
 8001e58:	f422 7240 	bic.w	r2, r2, #768	; 0x300
 8001e5c:	4313      	orrs	r3, r2
 8001e5e:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
 8001e62:	2000      	movs	r0, #0
      /* set overall return value */
      status = ret;
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 8001e64:	b127      	cbz	r7, 8001e70 <HAL_RCCEx_PeriphCLKConfig+0xbc>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8001e66:	4a77      	ldr	r2, [pc, #476]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001e68:	6d93      	ldr	r3, [r2, #88]	; 0x58
 8001e6a:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8001e6e:	6593      	str	r3, [r2, #88]	; 0x58
    }
  }

  /*-------------------------- USART1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
 8001e70:	6823      	ldr	r3, [r4, #0]
 8001e72:	07de      	lsls	r6, r3, #31
 8001e74:	d508      	bpl.n	8001e88 <HAL_RCCEx_PeriphCLKConfig+0xd4>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));

    /* Configure the USART1 clock source */
    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
 8001e76:	4973      	ldr	r1, [pc, #460]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001e78:	6865      	ldr	r5, [r4, #4]
 8001e7a:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001e7e:	f022 0203 	bic.w	r2, r2, #3
 8001e82:	432a      	orrs	r2, r5
 8001e84:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
  }

  /*-------------------------- USART2 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
 8001e88:	079d      	lsls	r5, r3, #30
 8001e8a:	d508      	bpl.n	8001e9e <HAL_RCCEx_PeriphCLKConfig+0xea>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));

    /* Configure the USART2 clock source */
    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
 8001e8c:	496d      	ldr	r1, [pc, #436]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001e8e:	68a5      	ldr	r5, [r4, #8]
 8001e90:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001e94:	f022 020c 	bic.w	r2, r2, #12
 8001e98:	432a      	orrs	r2, r5
 8001e9a:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
  }

#if defined(USART3)

  /*-------------------------- USART3 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
 8001e9e:	0759      	lsls	r1, r3, #29
 8001ea0:	d508      	bpl.n	8001eb4 <HAL_RCCEx_PeriphCLKConfig+0x100>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));

    /* Configure the USART3 clock source */
    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
 8001ea2:	4968      	ldr	r1, [pc, #416]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001ea4:	68e5      	ldr	r5, [r4, #12]
 8001ea6:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001eaa:	f022 0230 	bic.w	r2, r2, #48	; 0x30
 8001eae:	432a      	orrs	r2, r5
 8001eb0:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88

#endif /* USART3 */

#if defined(UART4)
  /*-------------------------- UART4 clock source configuration --------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
 8001eb4:	071a      	lsls	r2, r3, #28
 8001eb6:	d508      	bpl.n	8001eca <HAL_RCCEx_PeriphCLKConfig+0x116>
  {
    /* Check the parameters */
    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));

    /* Configure the UART4 clock source */
    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
 8001eb8:	4962      	ldr	r1, [pc, #392]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001eba:	6925      	ldr	r5, [r4, #16]
 8001ebc:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001ec0:	f022 02c0 	bic.w	r2, r2, #192	; 0xc0
 8001ec4:	432a      	orrs	r2, r5
 8001ec6:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
  }

#endif /* UART5 */

  /*-------------------------- LPUART1 clock source configuration ------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
 8001eca:	069f      	lsls	r7, r3, #26
 8001ecc:	d508      	bpl.n	8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x12c>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));

    /* Configure the LPUAR1 clock source */
    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
 8001ece:	495d      	ldr	r1, [pc, #372]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001ed0:	6965      	ldr	r5, [r4, #20]
 8001ed2:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001ed6:	f422 6240 	bic.w	r2, r2, #3072	; 0xc00
 8001eda:	432a      	orrs	r2, r5
 8001edc:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
  }

  /*-------------------------- I2C1 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
 8001ee0:	065e      	lsls	r6, r3, #25
 8001ee2:	d508      	bpl.n	8001ef6 <HAL_RCCEx_PeriphCLKConfig+0x142>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));

    /* Configure the I2C1 clock source */
    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
 8001ee4:	4957      	ldr	r1, [pc, #348]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001ee6:	69a5      	ldr	r5, [r4, #24]
 8001ee8:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001eec:	f422 5240 	bic.w	r2, r2, #12288	; 0x3000
 8001ef0:	432a      	orrs	r2, r5
 8001ef2:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
  }

  /*-------------------------- I2C2 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
 8001ef6:	061d      	lsls	r5, r3, #24
 8001ef8:	d508      	bpl.n	8001f0c <HAL_RCCEx_PeriphCLKConfig+0x158>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));

    /* Configure the I2C2 clock source */
    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
 8001efa:	4952      	ldr	r1, [pc, #328]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001efc:	69e5      	ldr	r5, [r4, #28]
 8001efe:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001f02:	f422 4240 	bic.w	r2, r2, #49152	; 0xc000
 8001f06:	432a      	orrs	r2, r5
 8001f08:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
  }
#if defined(I2C3)

  /*-------------------------- I2C3 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
 8001f0c:	05d9      	lsls	r1, r3, #23
 8001f0e:	d508      	bpl.n	8001f22 <HAL_RCCEx_PeriphCLKConfig+0x16e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));

    /* Configure the I2C3 clock source */
    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
 8001f10:	494c      	ldr	r1, [pc, #304]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001f12:	6a25      	ldr	r5, [r4, #32]
 8001f14:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001f18:	f422 3240 	bic.w	r2, r2, #196608	; 0x30000
 8001f1c:	432a      	orrs	r2, r5
 8001f1e:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
  }

#endif /* I2C4 */

  /*-------------------------- LPTIM1 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
 8001f22:	059a      	lsls	r2, r3, #22
 8001f24:	d508      	bpl.n	8001f38 <HAL_RCCEx_PeriphCLKConfig+0x184>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));

    /* Configure the LPTIM1 clock source */
    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
 8001f26:	4947      	ldr	r1, [pc, #284]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001f28:	6a65      	ldr	r5, [r4, #36]	; 0x24
 8001f2a:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001f2e:	f422 2240 	bic.w	r2, r2, #786432	; 0xc0000
 8001f32:	432a      	orrs	r2, r5
 8001f34:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
  }

#if defined(SAI1) 
  /*-------------------------- SAI1 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
 8001f38:	055f      	lsls	r7, r3, #21
 8001f3a:	d50b      	bpl.n	8001f54 <HAL_RCCEx_PeriphCLKConfig+0x1a0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));

    /* Configure the SAI1 interface clock source */
    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
 8001f3c:	4941      	ldr	r1, [pc, #260]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001f3e:	6aa5      	ldr	r5, [r4, #40]	; 0x28
 8001f40:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001f44:	f422 1240 	bic.w	r2, r2, #3145728	; 0x300000
 8001f48:	432a      	orrs	r2, r5
    
    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
 8001f4a:	f5b5 1f80 	cmp.w	r5, #1048576	; 0x100000
    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
 8001f4e:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
 8001f52:	d055      	beq.n	8002000 <HAL_RCCEx_PeriphCLKConfig+0x24c>

#endif /* SAI1 */

#if defined(SPI_I2S_SUPPORT)
  /*-------------------------- I2S clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
 8001f54:	051e      	lsls	r6, r3, #20
 8001f56:	d50b      	bpl.n	8001f70 <HAL_RCCEx_PeriphCLKConfig+0x1bc>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));

    /* Configure the I2S interface clock source */
    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
 8001f58:	493a      	ldr	r1, [pc, #232]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001f5a:	6ae5      	ldr	r5, [r4, #44]	; 0x2c
 8001f5c:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001f60:	f422 0240 	bic.w	r2, r2, #12582912	; 0xc00000
 8001f64:	432a      	orrs	r2, r5
    
    if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
 8001f66:	f5b5 0f80 	cmp.w	r5, #4194304	; 0x400000
    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
 8001f6a:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
    if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
 8001f6e:	d04c      	beq.n	800200a <HAL_RCCEx_PeriphCLKConfig+0x256>

#endif /* SPI_I2S_SUPPORT */

#if defined(FDCAN1)
  /*-------------------------- FDCAN clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
 8001f70:	04dd      	lsls	r5, r3, #19
 8001f72:	d50b      	bpl.n	8001f8c <HAL_RCCEx_PeriphCLKConfig+0x1d8>
  {
    /* Check the parameters */
    assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));

    /* Configure the FDCAN interface clock source */
    __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
 8001f74:	4933      	ldr	r1, [pc, #204]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001f76:	6b25      	ldr	r5, [r4, #48]	; 0x30
 8001f78:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001f7c:	f022 7240 	bic.w	r2, r2, #50331648	; 0x3000000
 8001f80:	432a      	orrs	r2, r5
    
    if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
 8001f82:	f1b5 7f80 	cmp.w	r5, #16777216	; 0x1000000
    __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
 8001f86:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
    if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
 8001f8a:	d043      	beq.n	8002014 <HAL_RCCEx_PeriphCLKConfig+0x260>
#endif /* FDCAN1 */

#if defined(USB)

  /*-------------------------- USB clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
 8001f8c:	0499      	lsls	r1, r3, #18
 8001f8e:	d50b      	bpl.n	8001fa8 <HAL_RCCEx_PeriphCLKConfig+0x1f4>
  {
    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8001f90:	492c      	ldr	r1, [pc, #176]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001f92:	6b65      	ldr	r5, [r4, #52]	; 0x34
 8001f94:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001f98:	f022 6240 	bic.w	r2, r2, #201326592	; 0xc000000
 8001f9c:	432a      	orrs	r2, r5

    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
 8001f9e:	f1b5 6f00 	cmp.w	r5, #134217728	; 0x8000000
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8001fa2:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
 8001fa6:	d03a      	beq.n	800201e <HAL_RCCEx_PeriphCLKConfig+0x26a>
  }

#endif /* USB */

  /*-------------------------- RNG clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
 8001fa8:	045a      	lsls	r2, r3, #17
 8001faa:	d50b      	bpl.n	8001fc4 <HAL_RCCEx_PeriphCLKConfig+0x210>
  {
    assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
 8001fac:	4925      	ldr	r1, [pc, #148]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001fae:	6ba5      	ldr	r5, [r4, #56]	; 0x38
 8001fb0:	f8d1 2088 	ldr.w	r2, [r1, #136]	; 0x88
 8001fb4:	f022 6240 	bic.w	r2, r2, #201326592	; 0xc000000
 8001fb8:	432a      	orrs	r2, r5

    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
 8001fba:	f1b5 6f00 	cmp.w	r5, #134217728	; 0x8000000
    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
 8001fbe:	f8c1 2088 	str.w	r2, [r1, #136]	; 0x88
    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
 8001fc2:	d031      	beq.n	8002028 <HAL_RCCEx_PeriphCLKConfig+0x274>
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
    }
  }

  /*-------------------------- ADC12 clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
 8001fc4:	041b      	lsls	r3, r3, #16
 8001fc6:	d50b      	bpl.n	8001fe0 <HAL_RCCEx_PeriphCLKConfig+0x22c>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));

    /* Configure the ADC12 interface clock source */
    __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
 8001fc8:	4a1e      	ldr	r2, [pc, #120]	; (8002044 <HAL_RCCEx_PeriphCLKConfig+0x290>)
 8001fca:	6be1      	ldr	r1, [r4, #60]	; 0x3c
 8001fcc:	f8d2 3088 	ldr.w	r3, [r2, #136]	; 0x88
 8001fd0:	f023 5340 	bic.w	r3, r3, #805306368	; 0x30000000
 8001fd4:	430b      	orrs	r3, r1
    
    if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
 8001fd6:	f1b1 5f80 	cmp.w	r1, #268435456	; 0x10000000
    __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
 8001fda:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
    if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
 8001fde:	d028      	beq.n	8002032 <HAL_RCCEx_PeriphCLKConfig+0x27e>
  }

#endif /* QUADSPI */

  return status;
}
 8001fe0:	b002      	add	sp, #8
 8001fe2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      __HAL_RCC_PWR_CLK_ENABLE();
 8001fe6:	6d9a      	ldr	r2, [r3, #88]	; 0x58
 8001fe8:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
 8001fec:	659a      	str	r2, [r3, #88]	; 0x58
 8001fee:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8001ff0:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001ff4:	9301      	str	r3, [sp, #4]
 8001ff6:	9b01      	ldr	r3, [sp, #4]
      pwrclkchanged = SET;
 8001ff8:	2701      	movs	r7, #1
 8001ffa:	e6e9      	b.n	8001dd0 <HAL_RCCEx_PeriphCLKConfig+0x1c>
        ret = HAL_TIMEOUT;
 8001ffc:	2003      	movs	r0, #3
 8001ffe:	e731      	b.n	8001e64 <HAL_RCCEx_PeriphCLKConfig+0xb0>
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8002000:	68ca      	ldr	r2, [r1, #12]
 8002002:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
 8002006:	60ca      	str	r2, [r1, #12]
 8002008:	e7a4      	b.n	8001f54 <HAL_RCCEx_PeriphCLKConfig+0x1a0>
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 800200a:	68ca      	ldr	r2, [r1, #12]
 800200c:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
 8002010:	60ca      	str	r2, [r1, #12]
 8002012:	e7ad      	b.n	8001f70 <HAL_RCCEx_PeriphCLKConfig+0x1bc>
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8002014:	68ca      	ldr	r2, [r1, #12]
 8002016:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
 800201a:	60ca      	str	r2, [r1, #12]
 800201c:	e7b6      	b.n	8001f8c <HAL_RCCEx_PeriphCLKConfig+0x1d8>
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 800201e:	68ca      	ldr	r2, [r1, #12]
 8002020:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
 8002024:	60ca      	str	r2, [r1, #12]
 8002026:	e7bf      	b.n	8001fa8 <HAL_RCCEx_PeriphCLKConfig+0x1f4>
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8002028:	68ca      	ldr	r2, [r1, #12]
 800202a:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
 800202e:	60ca      	str	r2, [r1, #12]
 8002030:	e7c8      	b.n	8001fc4 <HAL_RCCEx_PeriphCLKConfig+0x210>
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
 8002032:	68d3      	ldr	r3, [r2, #12]
 8002034:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8002038:	60d3      	str	r3, [r2, #12]
}
 800203a:	b002      	add	sp, #8
 800203c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8002040:	4613      	mov	r3, r2
 8002042:	e706      	b.n	8001e52 <HAL_RCCEx_PeriphCLKConfig+0x9e>
 8002044:	40021000 	.word	0x40021000
 8002048:	40007000 	.word	0x40007000

0800204c <HAL_TIM_Base_Init>:
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
  /* Check the TIM handle allocation */
  if (htim == NULL)
 800204c:	2800      	cmp	r0, #0
 800204e:	f000 808a 	beq.w	8002166 <HAL_TIM_Base_Init+0x11a>
{
 8002052:	b538      	push	{r3, r4, r5, lr}
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 8002054:	f890 303d 	ldrb.w	r3, [r0, #61]	; 0x3d
 8002058:	4604      	mov	r4, r0
 800205a:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 800205e:	2b00      	cmp	r3, #0
 8002060:	d05c      	beq.n	800211c <HAL_TIM_Base_Init+0xd0>

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8002062:	6822      	ldr	r2, [r4, #0]
{
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8002064:	4949      	ldr	r1, [pc, #292]	; (800218c <HAL_TIM_Base_Init+0x140>)
  htim->State = HAL_TIM_STATE_BUSY;
 8002066:	2302      	movs	r3, #2
 8002068:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 800206c:	428a      	cmp	r2, r1
  tmpcr1 = TIMx->CR1;
 800206e:	6813      	ldr	r3, [r2, #0]
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8002070:	d059      	beq.n	8002126 <HAL_TIM_Base_Init+0xda>
 8002072:	f1b2 4f80 	cmp.w	r2, #1073741824	; 0x40000000
 8002076:	d020      	beq.n	80020ba <HAL_TIM_Base_Init+0x6e>
 8002078:	f5a1 3194 	sub.w	r1, r1, #75776	; 0x12800
 800207c:	428a      	cmp	r2, r1
 800207e:	d01c      	beq.n	80020ba <HAL_TIM_Base_Init+0x6e>
 8002080:	f501 6180 	add.w	r1, r1, #1024	; 0x400
 8002084:	428a      	cmp	r2, r1
 8002086:	d018      	beq.n	80020ba <HAL_TIM_Base_Init+0x6e>
 8002088:	f501 3196 	add.w	r1, r1, #76800	; 0x12c00
 800208c:	428a      	cmp	r2, r1
 800208e:	d06c      	beq.n	800216a <HAL_TIM_Base_Init+0x11e>
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
    tmpcr1 |= Structure->CounterMode;
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 8002090:	f501 6140 	add.w	r1, r1, #3072	; 0xc00
 8002094:	428a      	cmp	r2, r1
 8002096:	d059      	beq.n	800214c <HAL_TIM_Base_Init+0x100>
 8002098:	f501 6180 	add.w	r1, r1, #1024	; 0x400
 800209c:	428a      	cmp	r2, r1
 800209e:	d055      	beq.n	800214c <HAL_TIM_Base_Init+0x100>
 80020a0:	f501 6180 	add.w	r1, r1, #1024	; 0x400
 80020a4:	428a      	cmp	r2, r1
 80020a6:	d051      	beq.n	800214c <HAL_TIM_Base_Init+0x100>
    tmpcr1 &= ~TIM_CR1_CKD;
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 80020a8:	69a1      	ldr	r1, [r4, #24]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 80020aa:	68e0      	ldr	r0, [r4, #12]
 80020ac:	62d0      	str	r0, [r2, #44]	; 0x2c
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 80020ae:	f023 0380 	bic.w	r3, r3, #128	; 0x80

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 80020b2:	6860      	ldr	r0, [r4, #4]
 80020b4:	6290      	str	r0, [r2, #40]	; 0x28
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 80020b6:	4319      	orrs	r1, r3

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 80020b8:	e00f      	b.n	80020da <HAL_TIM_Base_Init+0x8e>
    tmpcr1 |= Structure->CounterMode;
 80020ba:	68a1      	ldr	r1, [r4, #8]
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 80020bc:	69a0      	ldr	r0, [r4, #24]
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 80020be:	f023 0370 	bic.w	r3, r3, #112	; 0x70
    tmpcr1 |= Structure->CounterMode;
 80020c2:	430b      	orrs	r3, r1
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 80020c4:	6921      	ldr	r1, [r4, #16]
    tmpcr1 &= ~TIM_CR1_CKD;
 80020c6:	f423 7340 	bic.w	r3, r3, #768	; 0x300
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 80020ca:	4319      	orrs	r1, r3
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 80020cc:	f021 0180 	bic.w	r1, r1, #128	; 0x80
  TIMx->PSC = Structure->Prescaler;
 80020d0:	6863      	ldr	r3, [r4, #4]
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 80020d2:	4301      	orrs	r1, r0
  TIMx->ARR = (uint32_t)Structure->Period ;
 80020d4:	68e0      	ldr	r0, [r4, #12]
 80020d6:	62d0      	str	r0, [r2, #44]	; 0x2c
  TIMx->PSC = Structure->Prescaler;
 80020d8:	6293      	str	r3, [r2, #40]	; 0x28
    TIMx->RCR = Structure->RepetitionCounter;
  }

  /* Disable Update Event (UEV) with Update Generation (UG)
     by changing Update Request Source (URS) to avoid Update flag (UIF) */
  SET_BIT(TIMx->CR1, TIM_CR1_URS);
 80020da:	6810      	ldr	r0, [r2, #0]

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 80020dc:	2301      	movs	r3, #1
  SET_BIT(TIMx->CR1, TIM_CR1_URS);
 80020de:	f040 0004 	orr.w	r0, r0, #4
 80020e2:	6010      	str	r0, [r2, #0]
  TIMx->EGR = TIM_EGR_UG;
 80020e4:	6153      	str	r3, [r2, #20]

  TIMx->CR1 = tmpcr1;
 80020e6:	6011      	str	r1, [r2, #0]
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 80020e8:	f884 3048 	strb.w	r3, [r4, #72]	; 0x48
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 80020ec:	f884 303e 	strb.w	r3, [r4, #62]	; 0x3e
 80020f0:	f884 303f 	strb.w	r3, [r4, #63]	; 0x3f
 80020f4:	f884 3040 	strb.w	r3, [r4, #64]	; 0x40
 80020f8:	f884 3041 	strb.w	r3, [r4, #65]	; 0x41
 80020fc:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 8002100:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8002104:	f884 3044 	strb.w	r3, [r4, #68]	; 0x44
 8002108:	f884 3045 	strb.w	r3, [r4, #69]	; 0x45
 800210c:	f884 3046 	strb.w	r3, [r4, #70]	; 0x46
 8002110:	f884 3047 	strb.w	r3, [r4, #71]	; 0x47
  htim->State = HAL_TIM_STATE_READY;
 8002114:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  return HAL_OK;
 8002118:	2000      	movs	r0, #0
}
 800211a:	bd38      	pop	{r3, r4, r5, pc}
    htim->Lock = HAL_UNLOCKED;
 800211c:	f880 203c 	strb.w	r2, [r0, #60]	; 0x3c
    HAL_TIM_Base_MspInit(htim);
 8002120:	f7fe fc84 	bl	8000a2c <HAL_TIM_Base_MspInit>
 8002124:	e79d      	b.n	8002062 <HAL_TIM_Base_Init+0x16>
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8002126:	f023 0170 	bic.w	r1, r3, #112	; 0x70
    tmpcr1 |= Structure->CounterMode;
 800212a:	68a3      	ldr	r3, [r4, #8]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800212c:	6920      	ldr	r0, [r4, #16]
    tmpcr1 |= Structure->CounterMode;
 800212e:	4319      	orrs	r1, r3
    tmpcr1 &= ~TIM_CR1_CKD;
 8002130:	f421 7140 	bic.w	r1, r1, #768	; 0x300
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8002134:	4301      	orrs	r1, r0
  TIMx->ARR = (uint32_t)Structure->Period ;
 8002136:	68e0      	ldr	r0, [r4, #12]
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8002138:	69a3      	ldr	r3, [r4, #24]
  TIMx->ARR = (uint32_t)Structure->Period ;
 800213a:	62d0      	str	r0, [r2, #44]	; 0x2c
  TIMx->PSC = Structure->Prescaler;
 800213c:	6860      	ldr	r0, [r4, #4]
 800213e:	6290      	str	r0, [r2, #40]	; 0x28
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8002140:	f021 0180 	bic.w	r1, r1, #128	; 0x80
 8002144:	4319      	orrs	r1, r3
    TIMx->RCR = Structure->RepetitionCounter;
 8002146:	6963      	ldr	r3, [r4, #20]
 8002148:	6313      	str	r3, [r2, #48]	; 0x30
 800214a:	e7c6      	b.n	80020da <HAL_TIM_Base_Init+0x8e>
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800214c:	6920      	ldr	r0, [r4, #16]
  TIMx->ARR = (uint32_t)Structure->Period ;
 800214e:	68e5      	ldr	r5, [r4, #12]
    tmpcr1 &= ~TIM_CR1_CKD;
 8002150:	f423 7140 	bic.w	r1, r3, #768	; 0x300
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8002154:	4301      	orrs	r1, r0
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8002156:	69a3      	ldr	r3, [r4, #24]
  TIMx->ARR = (uint32_t)Structure->Period ;
 8002158:	62d5      	str	r5, [r2, #44]	; 0x2c
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 800215a:	f021 0180 	bic.w	r1, r1, #128	; 0x80
 800215e:	4319      	orrs	r1, r3
  TIMx->PSC = Structure->Prescaler;
 8002160:	6863      	ldr	r3, [r4, #4]
 8002162:	6293      	str	r3, [r2, #40]	; 0x28
  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 8002164:	e7ef      	b.n	8002146 <HAL_TIM_Base_Init+0xfa>
    return HAL_ERROR;
 8002166:	2001      	movs	r0, #1
}
 8002168:	4770      	bx	lr
    tmpcr1 |= Structure->CounterMode;
 800216a:	68a0      	ldr	r0, [r4, #8]
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 800216c:	f023 0170 	bic.w	r1, r3, #112	; 0x70
    tmpcr1 |= Structure->CounterMode;
 8002170:	4301      	orrs	r1, r0
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8002172:	6923      	ldr	r3, [r4, #16]
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8002174:	69a0      	ldr	r0, [r4, #24]
    tmpcr1 &= ~TIM_CR1_CKD;
 8002176:	f421 7140 	bic.w	r1, r1, #768	; 0x300
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800217a:	4319      	orrs	r1, r3
  TIMx->ARR = (uint32_t)Structure->Period ;
 800217c:	68e3      	ldr	r3, [r4, #12]
 800217e:	62d3      	str	r3, [r2, #44]	; 0x2c
  TIMx->PSC = Structure->Prescaler;
 8002180:	6863      	ldr	r3, [r4, #4]
 8002182:	6293      	str	r3, [r2, #40]	; 0x28
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8002184:	f021 0180 	bic.w	r1, r1, #128	; 0x80
 8002188:	4301      	orrs	r1, r0
  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 800218a:	e7dc      	b.n	8002146 <HAL_TIM_Base_Init+0xfa>
 800218c:	40012c00 	.word	0x40012c00

08002190 <HAL_TIM_Base_DeInit>:
  htim->State = HAL_TIM_STATE_BUSY;
 8002190:	2302      	movs	r3, #2
  __HAL_TIM_DISABLE(htim);
 8002192:	6802      	ldr	r2, [r0, #0]
{
 8002194:	b510      	push	{r4, lr}
  htim->State = HAL_TIM_STATE_BUSY;
 8002196:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d
  __HAL_TIM_DISABLE(htim);
 800219a:	6a13      	ldr	r3, [r2, #32]
 800219c:	f003 3311 	and.w	r3, r3, #286331153	; 0x11111111
 80021a0:	f023 5388 	bic.w	r3, r3, #285212672	; 0x11000000
{
 80021a4:	4604      	mov	r4, r0
  __HAL_TIM_DISABLE(htim);
 80021a6:	b943      	cbnz	r3, 80021ba <HAL_TIM_Base_DeInit+0x2a>
 80021a8:	6a11      	ldr	r1, [r2, #32]
 80021aa:	f244 4344 	movw	r3, #17476	; 0x4444
 80021ae:	4219      	tst	r1, r3
 80021b0:	d103      	bne.n	80021ba <HAL_TIM_Base_DeInit+0x2a>
 80021b2:	6813      	ldr	r3, [r2, #0]
 80021b4:	f023 0301 	bic.w	r3, r3, #1
 80021b8:	6013      	str	r3, [r2, #0]
  HAL_TIM_Base_MspDeInit(htim);
 80021ba:	4620      	mov	r0, r4
 80021bc:	f7fe fc56 	bl	8000a6c <HAL_TIM_Base_MspDeInit>
  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
 80021c0:	2000      	movs	r0, #0
 80021c2:	f884 0048 	strb.w	r0, [r4, #72]	; 0x48
  __HAL_UNLOCK(htim);
 80021c6:	f884 003c 	strb.w	r0, [r4, #60]	; 0x3c
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
 80021ca:	f884 003e 	strb.w	r0, [r4, #62]	; 0x3e
 80021ce:	f884 003f 	strb.w	r0, [r4, #63]	; 0x3f
 80021d2:	f884 0040 	strb.w	r0, [r4, #64]	; 0x40
 80021d6:	f884 0041 	strb.w	r0, [r4, #65]	; 0x41
 80021da:	f884 0042 	strb.w	r0, [r4, #66]	; 0x42
 80021de:	f884 0043 	strb.w	r0, [r4, #67]	; 0x43
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
 80021e2:	f884 0044 	strb.w	r0, [r4, #68]	; 0x44
 80021e6:	f884 0045 	strb.w	r0, [r4, #69]	; 0x45
 80021ea:	f884 0046 	strb.w	r0, [r4, #70]	; 0x46
 80021ee:	f884 0047 	strb.w	r0, [r4, #71]	; 0x47
  htim->State = HAL_TIM_STATE_RESET;
 80021f2:	f884 003d 	strb.w	r0, [r4, #61]	; 0x3d
}
 80021f6:	bd10      	pop	{r4, pc}

080021f8 <HAL_TIM_Base_Stop>:
  __HAL_TIM_DISABLE(htim);
 80021f8:	6802      	ldr	r2, [r0, #0]
 80021fa:	6a13      	ldr	r3, [r2, #32]
 80021fc:	f003 3311 	and.w	r3, r3, #286331153	; 0x11111111
 8002200:	f023 5388 	bic.w	r3, r3, #285212672	; 0x11000000
 8002204:	b943      	cbnz	r3, 8002218 <HAL_TIM_Base_Stop+0x20>
 8002206:	6a11      	ldr	r1, [r2, #32]
 8002208:	f244 4344 	movw	r3, #17476	; 0x4444
 800220c:	4219      	tst	r1, r3
 800220e:	d103      	bne.n	8002218 <HAL_TIM_Base_Stop+0x20>
 8002210:	6813      	ldr	r3, [r2, #0]
 8002212:	f023 0301 	bic.w	r3, r3, #1
 8002216:	6013      	str	r3, [r2, #0]
  htim->State = HAL_TIM_STATE_READY;
 8002218:	2301      	movs	r3, #1
 800221a:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d
}
 800221e:	2000      	movs	r0, #0
 8002220:	4770      	bx	lr
 8002222:	bf00      	nop

08002224 <HAL_TIM_Base_Start_IT>:
  if (htim->State != HAL_TIM_STATE_READY)
 8002224:	f890 303d 	ldrb.w	r3, [r0, #61]	; 0x3d
 8002228:	2b01      	cmp	r3, #1
 800222a:	d122      	bne.n	8002272 <HAL_TIM_Base_Start_IT+0x4e>
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 800222c:	6803      	ldr	r3, [r0, #0]
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800222e:	4917      	ldr	r1, [pc, #92]	; (800228c <HAL_TIM_Base_Start_IT+0x68>)
  htim->State = HAL_TIM_STATE_BUSY;
 8002230:	2202      	movs	r2, #2
 8002232:	f880 203d 	strb.w	r2, [r0, #61]	; 0x3d
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 8002236:	68da      	ldr	r2, [r3, #12]
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8002238:	428b      	cmp	r3, r1
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 800223a:	f042 0201 	orr.w	r2, r2, #1
 800223e:	60da      	str	r2, [r3, #12]
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8002240:	d019      	beq.n	8002276 <HAL_TIM_Base_Start_IT+0x52>
 8002242:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8002246:	d016      	beq.n	8002276 <HAL_TIM_Base_Start_IT+0x52>
 8002248:	4a11      	ldr	r2, [pc, #68]	; (8002290 <HAL_TIM_Base_Start_IT+0x6c>)
 800224a:	4293      	cmp	r3, r2
 800224c:	d013      	beq.n	8002276 <HAL_TIM_Base_Start_IT+0x52>
 800224e:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 8002252:	4293      	cmp	r3, r2
 8002254:	d00f      	beq.n	8002276 <HAL_TIM_Base_Start_IT+0x52>
 8002256:	f502 3296 	add.w	r2, r2, #76800	; 0x12c00
 800225a:	4293      	cmp	r3, r2
 800225c:	d00b      	beq.n	8002276 <HAL_TIM_Base_Start_IT+0x52>
 800225e:	f502 6240 	add.w	r2, r2, #3072	; 0xc00
 8002262:	4293      	cmp	r3, r2
 8002264:	d007      	beq.n	8002276 <HAL_TIM_Base_Start_IT+0x52>
    __HAL_TIM_ENABLE(htim);
 8002266:	681a      	ldr	r2, [r3, #0]
 8002268:	f042 0201 	orr.w	r2, r2, #1
  return HAL_OK;
 800226c:	2000      	movs	r0, #0
    __HAL_TIM_ENABLE(htim);
 800226e:	601a      	str	r2, [r3, #0]
 8002270:	4770      	bx	lr
    return HAL_ERROR;
 8002272:	2001      	movs	r0, #1
 8002274:	4770      	bx	lr
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 8002276:	6899      	ldr	r1, [r3, #8]
 8002278:	4a06      	ldr	r2, [pc, #24]	; (8002294 <HAL_TIM_Base_Start_IT+0x70>)
 800227a:	400a      	ands	r2, r1
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800227c:	2a06      	cmp	r2, #6
 800227e:	d002      	beq.n	8002286 <HAL_TIM_Base_Start_IT+0x62>
 8002280:	f5b2 3f80 	cmp.w	r2, #65536	; 0x10000
 8002284:	d1ef      	bne.n	8002266 <HAL_TIM_Base_Start_IT+0x42>
  return HAL_OK;
 8002286:	2000      	movs	r0, #0
}
 8002288:	4770      	bx	lr
 800228a:	bf00      	nop
 800228c:	40012c00 	.word	0x40012c00
 8002290:	40000400 	.word	0x40000400
 8002294:	00010007 	.word	0x00010007

08002298 <HAL_TIM_PeriodElapsedCallback>:
 8002298:	4770      	bx	lr
 800229a:	bf00      	nop

0800229c <HAL_TIM_OC_DelayElapsedCallback>:
 800229c:	4770      	bx	lr
 800229e:	bf00      	nop

080022a0 <HAL_TIM_IC_CaptureCallback>:
 80022a0:	4770      	bx	lr
 80022a2:	bf00      	nop

080022a4 <HAL_TIM_PWM_PulseFinishedCallback>:
 80022a4:	4770      	bx	lr
 80022a6:	bf00      	nop

080022a8 <HAL_TIM_TriggerCallback>:
 80022a8:	4770      	bx	lr
 80022aa:	bf00      	nop

080022ac <HAL_TIM_IRQHandler>:
  uint32_t itsource = htim->Instance->DIER;
 80022ac:	6803      	ldr	r3, [r0, #0]
{
 80022ae:	b570      	push	{r4, r5, r6, lr}
  uint32_t itsource = htim->Instance->DIER;
 80022b0:	68de      	ldr	r6, [r3, #12]
  uint32_t itflag   = htim->Instance->SR;
 80022b2:	691c      	ldr	r4, [r3, #16]
  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
 80022b4:	07a2      	lsls	r2, r4, #30
{
 80022b6:	4605      	mov	r5, r0
  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
 80022b8:	d501      	bpl.n	80022be <HAL_TIM_IRQHandler+0x12>
    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
 80022ba:	07b1      	lsls	r1, r6, #30
 80022bc:	d46c      	bmi.n	8002398 <HAL_TIM_IRQHandler+0xec>
  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
 80022be:	0763      	lsls	r3, r4, #29
 80022c0:	d501      	bpl.n	80022c6 <HAL_TIM_IRQHandler+0x1a>
    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
 80022c2:	0770      	lsls	r0, r6, #29
 80022c4:	d455      	bmi.n	8002372 <HAL_TIM_IRQHandler+0xc6>
  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
 80022c6:	0721      	lsls	r1, r4, #28
 80022c8:	d501      	bpl.n	80022ce <HAL_TIM_IRQHandler+0x22>
    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
 80022ca:	0732      	lsls	r2, r6, #28
 80022cc:	d43e      	bmi.n	800234c <HAL_TIM_IRQHandler+0xa0>
  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
 80022ce:	06e0      	lsls	r0, r4, #27
 80022d0:	d501      	bpl.n	80022d6 <HAL_TIM_IRQHandler+0x2a>
    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
 80022d2:	06f1      	lsls	r1, r6, #27
 80022d4:	d426      	bmi.n	8002324 <HAL_TIM_IRQHandler+0x78>
  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
 80022d6:	07e2      	lsls	r2, r4, #31
 80022d8:	d501      	bpl.n	80022de <HAL_TIM_IRQHandler+0x32>
    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
 80022da:	07f3      	lsls	r3, r6, #31
 80022dc:	d47a      	bmi.n	80023d4 <HAL_TIM_IRQHandler+0x128>
  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
 80022de:	f414 5f02 	tst.w	r4, #8320	; 0x2080
 80022e2:	d069      	beq.n	80023b8 <HAL_TIM_IRQHandler+0x10c>
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 80022e4:	0630      	lsls	r0, r6, #24
 80022e6:	d47d      	bmi.n	80023e4 <HAL_TIM_IRQHandler+0x138>
  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
 80022e8:	0660      	lsls	r0, r4, #25
 80022ea:	d502      	bpl.n	80022f2 <HAL_TIM_IRQHandler+0x46>
    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
 80022ec:	0671      	lsls	r1, r6, #25
 80022ee:	f100 808b 	bmi.w	8002408 <HAL_TIM_IRQHandler+0x15c>
  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
 80022f2:	06a2      	lsls	r2, r4, #26
 80022f4:	d502      	bpl.n	80022fc <HAL_TIM_IRQHandler+0x50>
    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
 80022f6:	06b3      	lsls	r3, r6, #26
 80022f8:	f100 808e 	bmi.w	8002418 <HAL_TIM_IRQHandler+0x16c>
  if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
 80022fc:	02e0      	lsls	r0, r4, #11
 80022fe:	d502      	bpl.n	8002306 <HAL_TIM_IRQHandler+0x5a>
    if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
 8002300:	02f1      	lsls	r1, r6, #11
 8002302:	f100 8091 	bmi.w	8002428 <HAL_TIM_IRQHandler+0x17c>
  if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
 8002306:	02a2      	lsls	r2, r4, #10
 8002308:	d502      	bpl.n	8002310 <HAL_TIM_IRQHandler+0x64>
    if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
 800230a:	02b3      	lsls	r3, r6, #10
 800230c:	f100 8094 	bmi.w	8002438 <HAL_TIM_IRQHandler+0x18c>
  if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
 8002310:	0260      	lsls	r0, r4, #9
 8002312:	d502      	bpl.n	800231a <HAL_TIM_IRQHandler+0x6e>
    if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
 8002314:	0271      	lsls	r1, r6, #9
 8002316:	f100 8097 	bmi.w	8002448 <HAL_TIM_IRQHandler+0x19c>
  if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
 800231a:	0222      	lsls	r2, r4, #8
 800231c:	d501      	bpl.n	8002322 <HAL_TIM_IRQHandler+0x76>
    if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
 800231e:	0233      	lsls	r3, r6, #8
 8002320:	d44f      	bmi.n	80023c2 <HAL_TIM_IRQHandler+0x116>
}
 8002322:	bd70      	pop	{r4, r5, r6, pc}
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
 8002324:	682b      	ldr	r3, [r5, #0]
 8002326:	f06f 0210 	mvn.w	r2, #16
 800232a:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 800232c:	2208      	movs	r2, #8
 800232e:	772a      	strb	r2, [r5, #28]
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8002330:	69db      	ldr	r3, [r3, #28]
 8002332:	f413 7f40 	tst.w	r3, #768	; 0x300
        HAL_TIM_IC_CaptureCallback(htim);
 8002336:	4628      	mov	r0, r5
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8002338:	f040 8097 	bne.w	800246a <HAL_TIM_IRQHandler+0x1be>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800233c:	f7ff ffae 	bl	800229c <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8002340:	4628      	mov	r0, r5
 8002342:	f7ff ffaf 	bl	80022a4 <HAL_TIM_PWM_PulseFinishedCallback>
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8002346:	2300      	movs	r3, #0
 8002348:	772b      	strb	r3, [r5, #28]
 800234a:	e7c4      	b.n	80022d6 <HAL_TIM_IRQHandler+0x2a>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
 800234c:	682b      	ldr	r3, [r5, #0]
 800234e:	f06f 0208 	mvn.w	r2, #8
 8002352:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8002354:	2204      	movs	r2, #4
 8002356:	772a      	strb	r2, [r5, #28]
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 8002358:	69db      	ldr	r3, [r3, #28]
 800235a:	079b      	lsls	r3, r3, #30
        HAL_TIM_IC_CaptureCallback(htim);
 800235c:	4628      	mov	r0, r5
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800235e:	f040 8081 	bne.w	8002464 <HAL_TIM_IRQHandler+0x1b8>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8002362:	f7ff ff9b 	bl	800229c <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8002366:	4628      	mov	r0, r5
 8002368:	f7ff ff9c 	bl	80022a4 <HAL_TIM_PWM_PulseFinishedCallback>
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800236c:	2300      	movs	r3, #0
 800236e:	772b      	strb	r3, [r5, #28]
 8002370:	e7ad      	b.n	80022ce <HAL_TIM_IRQHandler+0x22>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
 8002372:	682b      	ldr	r3, [r5, #0]
 8002374:	f06f 0204 	mvn.w	r2, #4
 8002378:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 800237a:	2202      	movs	r2, #2
 800237c:	772a      	strb	r2, [r5, #28]
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800237e:	699b      	ldr	r3, [r3, #24]
 8002380:	f413 7f40 	tst.w	r3, #768	; 0x300
        HAL_TIM_IC_CaptureCallback(htim);
 8002384:	4628      	mov	r0, r5
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8002386:	d16a      	bne.n	800245e <HAL_TIM_IRQHandler+0x1b2>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8002388:	f7ff ff88 	bl	800229c <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800238c:	4628      	mov	r0, r5
 800238e:	f7ff ff89 	bl	80022a4 <HAL_TIM_PWM_PulseFinishedCallback>
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8002392:	2300      	movs	r3, #0
 8002394:	772b      	strb	r3, [r5, #28]
 8002396:	e796      	b.n	80022c6 <HAL_TIM_IRQHandler+0x1a>
        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
 8002398:	f06f 0202 	mvn.w	r2, #2
 800239c:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 800239e:	2201      	movs	r2, #1
 80023a0:	7702      	strb	r2, [r0, #28]
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80023a2:	699b      	ldr	r3, [r3, #24]
 80023a4:	079a      	lsls	r2, r3, #30
 80023a6:	d157      	bne.n	8002458 <HAL_TIM_IRQHandler+0x1ac>
          HAL_TIM_OC_DelayElapsedCallback(htim);
 80023a8:	f7ff ff78 	bl	800229c <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 80023ac:	4628      	mov	r0, r5
 80023ae:	f7ff ff79 	bl	80022a4 <HAL_TIM_PWM_PulseFinishedCallback>
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80023b2:	2300      	movs	r3, #0
 80023b4:	772b      	strb	r3, [r5, #28]
 80023b6:	e782      	b.n	80022be <HAL_TIM_IRQHandler+0x12>
  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
 80023b8:	05e2      	lsls	r2, r4, #23
 80023ba:	d595      	bpl.n	80022e8 <HAL_TIM_IRQHandler+0x3c>
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 80023bc:	0633      	lsls	r3, r6, #24
 80023be:	d41b      	bmi.n	80023f8 <HAL_TIM_IRQHandler+0x14c>
 80023c0:	e792      	b.n	80022e8 <HAL_TIM_IRQHandler+0x3c>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
 80023c2:	682b      	ldr	r3, [r5, #0]
 80023c4:	f46f 0200 	mvn.w	r2, #8388608	; 0x800000
      HAL_TIMEx_TransitionErrorCallback(htim);
 80023c8:	4628      	mov	r0, r5
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
 80023ca:	611a      	str	r2, [r3, #16]
}
 80023cc:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
      HAL_TIMEx_TransitionErrorCallback(htim);
 80023d0:	f000 b8a4 	b.w	800251c <HAL_TIMEx_TransitionErrorCallback>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
 80023d4:	682b      	ldr	r3, [r5, #0]
 80023d6:	f06f 0201 	mvn.w	r2, #1
 80023da:	611a      	str	r2, [r3, #16]
      HAL_TIM_PeriodElapsedCallback(htim);
 80023dc:	4628      	mov	r0, r5
 80023de:	f7ff ff5b 	bl	8002298 <HAL_TIM_PeriodElapsedCallback>
 80023e2:	e77c      	b.n	80022de <HAL_TIM_IRQHandler+0x32>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
 80023e4:	682b      	ldr	r3, [r5, #0]
 80023e6:	f46f 5202 	mvn.w	r2, #8320	; 0x2080
 80023ea:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_BreakCallback(htim);
 80023ec:	4628      	mov	r0, r5
 80023ee:	f000 f88b 	bl	8002508 <HAL_TIMEx_BreakCallback>
  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
 80023f2:	05e1      	lsls	r1, r4, #23
 80023f4:	f57f af78 	bpl.w	80022e8 <HAL_TIM_IRQHandler+0x3c>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
 80023f8:	682b      	ldr	r3, [r5, #0]
 80023fa:	f46f 7280 	mvn.w	r2, #256	; 0x100
 80023fe:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_Break2Callback(htim);
 8002400:	4628      	mov	r0, r5
 8002402:	f000 f883 	bl	800250c <HAL_TIMEx_Break2Callback>
 8002406:	e76f      	b.n	80022e8 <HAL_TIM_IRQHandler+0x3c>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
 8002408:	682b      	ldr	r3, [r5, #0]
 800240a:	f06f 0240 	mvn.w	r2, #64	; 0x40
 800240e:	611a      	str	r2, [r3, #16]
      HAL_TIM_TriggerCallback(htim);
 8002410:	4628      	mov	r0, r5
 8002412:	f7ff ff49 	bl	80022a8 <HAL_TIM_TriggerCallback>
 8002416:	e76c      	b.n	80022f2 <HAL_TIM_IRQHandler+0x46>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
 8002418:	682b      	ldr	r3, [r5, #0]
 800241a:	f06f 0220 	mvn.w	r2, #32
 800241e:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_CommutCallback(htim);
 8002420:	4628      	mov	r0, r5
 8002422:	f000 f86f 	bl	8002504 <HAL_TIMEx_CommutCallback>
 8002426:	e769      	b.n	80022fc <HAL_TIM_IRQHandler+0x50>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
 8002428:	682b      	ldr	r3, [r5, #0]
 800242a:	f46f 1280 	mvn.w	r2, #1048576	; 0x100000
 800242e:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_EncoderIndexCallback(htim);
 8002430:	4628      	mov	r0, r5
 8002432:	f000 f86d 	bl	8002510 <HAL_TIMEx_EncoderIndexCallback>
 8002436:	e766      	b.n	8002306 <HAL_TIM_IRQHandler+0x5a>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
 8002438:	682b      	ldr	r3, [r5, #0]
 800243a:	f46f 1200 	mvn.w	r2, #2097152	; 0x200000
 800243e:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_DirectionChangeCallback(htim);
 8002440:	4628      	mov	r0, r5
 8002442:	f000 f867 	bl	8002514 <HAL_TIMEx_DirectionChangeCallback>
 8002446:	e763      	b.n	8002310 <HAL_TIM_IRQHandler+0x64>
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
 8002448:	682b      	ldr	r3, [r5, #0]
 800244a:	f46f 0280 	mvn.w	r2, #4194304	; 0x400000
 800244e:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_IndexErrorCallback(htim);
 8002450:	4628      	mov	r0, r5
 8002452:	f000 f861 	bl	8002518 <HAL_TIMEx_IndexErrorCallback>
 8002456:	e760      	b.n	800231a <HAL_TIM_IRQHandler+0x6e>
          HAL_TIM_IC_CaptureCallback(htim);
 8002458:	f7ff ff22 	bl	80022a0 <HAL_TIM_IC_CaptureCallback>
 800245c:	e7a9      	b.n	80023b2 <HAL_TIM_IRQHandler+0x106>
        HAL_TIM_IC_CaptureCallback(htim);
 800245e:	f7ff ff1f 	bl	80022a0 <HAL_TIM_IC_CaptureCallback>
 8002462:	e796      	b.n	8002392 <HAL_TIM_IRQHandler+0xe6>
        HAL_TIM_IC_CaptureCallback(htim);
 8002464:	f7ff ff1c 	bl	80022a0 <HAL_TIM_IC_CaptureCallback>
 8002468:	e780      	b.n	800236c <HAL_TIM_IRQHandler+0xc0>
        HAL_TIM_IC_CaptureCallback(htim);
 800246a:	f7ff ff19 	bl	80022a0 <HAL_TIM_IC_CaptureCallback>
 800246e:	e76a      	b.n	8002346 <HAL_TIM_IRQHandler+0x9a>

08002470 <HAL_TIMEx_MasterConfigSynchronization>:
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);
 8002470:	f890 303c 	ldrb.w	r3, [r0, #60]	; 0x3c
 8002474:	2b01      	cmp	r3, #1
 8002476:	d03e      	beq.n	80024f6 <HAL_TIMEx_MasterConfigSynchronization+0x86>
{
 8002478:	b470      	push	{r4, r5, r6}

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;
 800247a:	6802      	ldr	r2, [r0, #0]

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;

  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
 800247c:	4d1f      	ldr	r5, [pc, #124]	; (80024fc <HAL_TIMEx_MasterConfigSynchronization+0x8c>)
  htim->State = HAL_TIM_STATE_BUSY;
 800247e:	2302      	movs	r3, #2
 8002480:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d
  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
 8002484:	42aa      	cmp	r2, r5
  tmpcr2 = htim->Instance->CR2;
 8002486:	6853      	ldr	r3, [r2, #4]
  tmpsmcr = htim->Instance->SMCR;
 8002488:	6894      	ldr	r4, [r2, #8]
  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
 800248a:	d028      	beq.n	80024de <HAL_TIMEx_MasterConfigSynchronization+0x6e>
 800248c:	f505 6500 	add.w	r5, r5, #2048	; 0x800
 8002490:	42aa      	cmp	r2, r5
 8002492:	d024      	beq.n	80024de <HAL_TIMEx_MasterConfigSynchronization+0x6e>
  }

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
  /* Select the TRGO source */
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 8002494:	680e      	ldr	r6, [r1, #0]
  tmpcr2 &= ~TIM_CR2_MMS;
 8002496:	f023 7300 	bic.w	r3, r3, #33554432	; 0x2000000
 800249a:	f023 0370 	bic.w	r3, r3, #112	; 0x70
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 800249e:	4333      	orrs	r3, r6

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;

  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 80024a0:	f1b2 4f80 	cmp.w	r2, #1073741824	; 0x40000000
  htim->Instance->CR2 = tmpcr2;
 80024a4:	6053      	str	r3, [r2, #4]
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 80024a6:	d00c      	beq.n	80024c2 <HAL_TIMEx_MasterConfigSynchronization+0x52>
 80024a8:	4b15      	ldr	r3, [pc, #84]	; (8002500 <HAL_TIMEx_MasterConfigSynchronization+0x90>)
 80024aa:	429a      	cmp	r2, r3
 80024ac:	d009      	beq.n	80024c2 <HAL_TIMEx_MasterConfigSynchronization+0x52>
 80024ae:	f503 6380 	add.w	r3, r3, #1024	; 0x400
 80024b2:	429a      	cmp	r2, r3
 80024b4:	d005      	beq.n	80024c2 <HAL_TIMEx_MasterConfigSynchronization+0x52>
 80024b6:	42aa      	cmp	r2, r5
 80024b8:	d003      	beq.n	80024c2 <HAL_TIMEx_MasterConfigSynchronization+0x52>
 80024ba:	f503 339c 	add.w	r3, r3, #79872	; 0x13800
 80024be:	429a      	cmp	r2, r3
 80024c0:	d104      	bne.n	80024cc <HAL_TIMEx_MasterConfigSynchronization+0x5c>
  {
    /* Reset the MSM Bit */
    tmpsmcr &= ~TIM_SMCR_MSM;
    /* Set master mode */
    tmpsmcr |= sMasterConfig->MasterSlaveMode;
 80024c2:	688b      	ldr	r3, [r1, #8]
    tmpsmcr &= ~TIM_SMCR_MSM;
 80024c4:	f024 0480 	bic.w	r4, r4, #128	; 0x80
    tmpsmcr |= sMasterConfig->MasterSlaveMode;
 80024c8:	431c      	orrs	r4, r3

    /* Update TIMx SMCR */
    htim->Instance->SMCR = tmpsmcr;
 80024ca:	6094      	str	r4, [r2, #8]
  }

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;

  __HAL_UNLOCK(htim);
 80024cc:	2300      	movs	r3, #0
  htim->State = HAL_TIM_STATE_READY;
 80024ce:	2201      	movs	r2, #1
 80024d0:	f880 203d 	strb.w	r2, [r0, #61]	; 0x3d
  __HAL_UNLOCK(htim);
 80024d4:	f880 303c 	strb.w	r3, [r0, #60]	; 0x3c

  return HAL_OK;
}
 80024d8:	bc70      	pop	{r4, r5, r6}
  return HAL_OK;
 80024da:	4618      	mov	r0, r3
}
 80024dc:	4770      	bx	lr
    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
 80024de:	684d      	ldr	r5, [r1, #4]
    tmpcr2 &= ~TIM_CR2_MMS2;
 80024e0:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
 80024e4:	432b      	orrs	r3, r5
  tmpcr2 &= ~TIM_CR2_MMS;
 80024e6:	f023 7300 	bic.w	r3, r3, #33554432	; 0x2000000
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 80024ea:	680d      	ldr	r5, [r1, #0]
  tmpcr2 &= ~TIM_CR2_MMS;
 80024ec:	f023 0370 	bic.w	r3, r3, #112	; 0x70
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 80024f0:	432b      	orrs	r3, r5
  htim->Instance->CR2 = tmpcr2;
 80024f2:	6053      	str	r3, [r2, #4]
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 80024f4:	e7e5      	b.n	80024c2 <HAL_TIMEx_MasterConfigSynchronization+0x52>
  __HAL_LOCK(htim);
 80024f6:	2002      	movs	r0, #2
}
 80024f8:	4770      	bx	lr
 80024fa:	bf00      	nop
 80024fc:	40012c00 	.word	0x40012c00
 8002500:	40000400 	.word	0x40000400

08002504 <HAL_TIMEx_CommutCallback>:
 8002504:	4770      	bx	lr
 8002506:	bf00      	nop

08002508 <HAL_TIMEx_BreakCallback>:
 8002508:	4770      	bx	lr
 800250a:	bf00      	nop

0800250c <HAL_TIMEx_Break2Callback>:
 800250c:	4770      	bx	lr
 800250e:	bf00      	nop

08002510 <HAL_TIMEx_EncoderIndexCallback>:
 8002510:	4770      	bx	lr
 8002512:	bf00      	nop

08002514 <HAL_TIMEx_DirectionChangeCallback>:
 8002514:	4770      	bx	lr
 8002516:	bf00      	nop

08002518 <HAL_TIMEx_IndexErrorCallback>:
 8002518:	4770      	bx	lr
 800251a:	bf00      	nop

0800251c <HAL_TIMEx_TransitionErrorCallback>:
 800251c:	4770      	bx	lr
 800251e:	bf00      	nop

08002520 <HAL_UART_DeInit>:
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
{
  /* Check the UART handle allocation */
  if (huart == NULL)
 8002520:	b1d8      	cbz	r0, 800255a <HAL_UART_DeInit+0x3a>
{
 8002522:	b538      	push	{r3, r4, r5, lr}
  }

  /* Check the parameters */
  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));

  huart->gState = HAL_UART_STATE_BUSY;
 8002524:	2224      	movs	r2, #36	; 0x24

  __HAL_UART_DISABLE(huart);
 8002526:	6803      	ldr	r3, [r0, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 8002528:	f8c0 2088 	str.w	r2, [r0, #136]	; 0x88
  __HAL_UART_DISABLE(huart);
 800252c:	681a      	ldr	r2, [r3, #0]

  huart->Instance->CR1 = 0x0U;
 800252e:	2500      	movs	r5, #0
 8002530:	4604      	mov	r4, r0
  __HAL_UART_DISABLE(huart);
 8002532:	f022 0201 	bic.w	r2, r2, #1
 8002536:	601a      	str	r2, [r3, #0]
  huart->Instance->CR1 = 0x0U;
 8002538:	601d      	str	r5, [r3, #0]
  huart->Instance->CR2 = 0x0U;
 800253a:	605d      	str	r5, [r3, #4]
  huart->Instance->CR3 = 0x0U;
 800253c:	609d      	str	r5, [r3, #8]
  }
  /* DeInit the low level hardware */
  huart->MspDeInitCallback(huart);
#else
  /* DeInit the low level hardware */
  HAL_UART_MspDeInit(huart);
 800253e:	f7fe faf5 	bl	8000b2c <HAL_UART_MspDeInit>
  huart->gState = HAL_UART_STATE_RESET;
  huart->RxState = HAL_UART_STATE_RESET;
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  huart->RxEventType = HAL_UART_RXEVENT_TC;

  __HAL_UNLOCK(huart);
 8002542:	f884 5084 	strb.w	r5, [r4, #132]	; 0x84
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8002546:	f8c4 5090 	str.w	r5, [r4, #144]	; 0x90

  return HAL_OK;
 800254a:	4628      	mov	r0, r5
  huart->gState = HAL_UART_STATE_RESET;
 800254c:	f8c4 5088 	str.w	r5, [r4, #136]	; 0x88
  huart->RxState = HAL_UART_STATE_RESET;
 8002550:	f8c4 508c 	str.w	r5, [r4, #140]	; 0x8c
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002554:	66e5      	str	r5, [r4, #108]	; 0x6c
  huart->RxEventType = HAL_UART_RXEVENT_TC;
 8002556:	6725      	str	r5, [r4, #112]	; 0x70
}
 8002558:	bd38      	pop	{r3, r4, r5, pc}
    return HAL_ERROR;
 800255a:	2001      	movs	r0, #1
}
 800255c:	4770      	bx	lr
 800255e:	bf00      	nop

08002560 <HAL_UART_Transmit>:
  * @param Size    Amount of data elements (u8 or u16) to be sent.
  * @param Timeout Timeout duration.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 8002560:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8002564:	4605      	mov	r5, r0
  const uint8_t  *pdata8bits;
  const uint16_t *pdata16bits;
  uint32_t tickstart;

  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 8002566:	f8d0 0088 	ldr.w	r0, [r0, #136]	; 0x88
 800256a:	2820      	cmp	r0, #32
 800256c:	d159      	bne.n	8002622 <HAL_UART_Transmit+0xc2>
  {
    if ((pData == NULL) || (Size == 0U))
 800256e:	4689      	mov	r9, r1
 8002570:	b109      	cbz	r1, 8002576 <HAL_UART_Transmit+0x16>
 8002572:	4614      	mov	r4, r2
 8002574:	b912      	cbnz	r2, 800257c <HAL_UART_Transmit+0x1c>
    {
      return  HAL_ERROR;
 8002576:	2001      	movs	r0, #1
  }
  else
  {
    return HAL_BUSY;
  }
}
 8002578:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 800257c:	4698      	mov	r8, r3
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 800257e:	2700      	movs	r7, #0
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8002580:	2321      	movs	r3, #33	; 0x21
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8002582:	f8c5 7090 	str.w	r7, [r5, #144]	; 0x90
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8002586:	f8c5 3088 	str.w	r3, [r5, #136]	; 0x88
    tickstart = HAL_GetTick();
 800258a:	f7fe fba5 	bl	8000cd8 <HAL_GetTick>
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 800258e:	68ab      	ldr	r3, [r5, #8]
    huart->TxXferSize  = Size;
 8002590:	f8a5 4054 	strh.w	r4, [r5, #84]	; 0x54
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 8002594:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
    huart->TxXferCount = Size;
 8002598:	f8a5 4056 	strh.w	r4, [r5, #86]	; 0x56
    tickstart = HAL_GetTick();
 800259c:	4606      	mov	r6, r0
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 800259e:	d043      	beq.n	8002628 <HAL_UART_Transmit+0xc8>
    while (huart->TxXferCount > 0U)
 80025a0:	f8b5 3056 	ldrh.w	r3, [r5, #86]	; 0x56
  */
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
                                              uint32_t Tickstart, uint32_t Timeout)
{
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80025a4:	682c      	ldr	r4, [r5, #0]
    while (huart->TxXferCount > 0U)
 80025a6:	b29b      	uxth	r3, r3
 80025a8:	b1e3      	cbz	r3, 80025e4 <HAL_UART_Transmit+0x84>
 80025aa:	f1b8 3fff 	cmp.w	r8, #4294967295	; 0xffffffff
 80025ae:	d124      	bne.n	80025fa <HAL_UART_Transmit+0x9a>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80025b0:	69e2      	ldr	r2, [r4, #28]
 80025b2:	0610      	lsls	r0, r2, #24
 80025b4:	d5fc      	bpl.n	80025b0 <HAL_UART_Transmit+0x50>
      if (pdata8bits == NULL)
 80025b6:	f1b9 0f00 	cmp.w	r9, #0
 80025ba:	d02c      	beq.n	8002616 <HAL_UART_Transmit+0xb6>
        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
 80025bc:	f819 3b01 	ldrb.w	r3, [r9], #1
 80025c0:	62a3      	str	r3, [r4, #40]	; 0x28
      if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX)
 80025c2:	f8d5 3088 	ldr.w	r3, [r5, #136]	; 0x88
 80025c6:	f003 0321 	and.w	r3, r3, #33	; 0x21
 80025ca:	2b21      	cmp	r3, #33	; 0x21
 80025cc:	d1d3      	bne.n	8002576 <HAL_UART_Transmit+0x16>
        huart->TxXferCount--;
 80025ce:	f8b5 2056 	ldrh.w	r2, [r5, #86]	; 0x56
 80025d2:	3a01      	subs	r2, #1
 80025d4:	b292      	uxth	r2, r2
 80025d6:	f8a5 2056 	strh.w	r2, [r5, #86]	; 0x56
    while (huart->TxXferCount > 0U)
 80025da:	f8b5 3056 	ldrh.w	r3, [r5, #86]	; 0x56
 80025de:	b29b      	uxth	r3, r3
 80025e0:	2b00      	cmp	r3, #0
 80025e2:	d1e2      	bne.n	80025aa <HAL_UART_Transmit+0x4a>
 80025e4:	f1b8 3fff 	cmp.w	r8, #4294967295	; 0xffffffff
 80025e8:	d12a      	bne.n	8002640 <HAL_UART_Transmit+0xe0>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80025ea:	69e3      	ldr	r3, [r4, #28]
 80025ec:	065a      	lsls	r2, r3, #25
 80025ee:	d5fc      	bpl.n	80025ea <HAL_UART_Transmit+0x8a>
    huart->gState = HAL_UART_STATE_READY;
 80025f0:	2320      	movs	r3, #32
 80025f2:	f8c5 3088 	str.w	r3, [r5, #136]	; 0x88
    return HAL_OK;
 80025f6:	2000      	movs	r0, #0
 80025f8:	e7be      	b.n	8002578 <HAL_UART_Transmit+0x18>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80025fa:	69e3      	ldr	r3, [r4, #28]
 80025fc:	0619      	lsls	r1, r3, #24
 80025fe:	d4da      	bmi.n	80025b6 <HAL_UART_Transmit+0x56>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8002600:	f7fe fb6a 	bl	8000cd8 <HAL_GetTick>
 8002604:	1b80      	subs	r0, r0, r6
 8002606:	4580      	cmp	r8, r0
 8002608:	d314      	bcc.n	8002634 <HAL_UART_Transmit+0xd4>
 800260a:	f1b8 0f00 	cmp.w	r8, #0
 800260e:	d011      	beq.n	8002634 <HAL_UART_Transmit+0xd4>
      {

        return HAL_TIMEOUT;
      }

      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
 8002610:	682c      	ldr	r4, [r5, #0]
 8002612:	6823      	ldr	r3, [r4, #0]
 8002614:	e7c9      	b.n	80025aa <HAL_UART_Transmit+0x4a>
        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
 8002616:	f837 3b02 	ldrh.w	r3, [r7], #2
 800261a:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800261e:	62a3      	str	r3, [r4, #40]	; 0x28
        pdata16bits++;
 8002620:	e7cf      	b.n	80025c2 <HAL_UART_Transmit+0x62>
    return HAL_BUSY;
 8002622:	2002      	movs	r0, #2
}
 8002624:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 8002628:	692b      	ldr	r3, [r5, #16]
 800262a:	2b00      	cmp	r3, #0
 800262c:	d1b8      	bne.n	80025a0 <HAL_UART_Transmit+0x40>
 800262e:	464f      	mov	r7, r9
      pdata8bits  = NULL;
 8002630:	4699      	mov	r9, r3
 8002632:	e7b5      	b.n	80025a0 <HAL_UART_Transmit+0x40>
      huart->gState = HAL_UART_STATE_READY;
 8002634:	2320      	movs	r3, #32
 8002636:	f8c5 3088 	str.w	r3, [r5, #136]	; 0x88
      return HAL_TIMEOUT;
 800263a:	2003      	movs	r0, #3
}
 800263c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8002640:	69e3      	ldr	r3, [r4, #28]
 8002642:	065b      	lsls	r3, r3, #25
 8002644:	d4d4      	bmi.n	80025f0 <HAL_UART_Transmit+0x90>
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8002646:	f7fe fb47 	bl	8000cd8 <HAL_GetTick>
 800264a:	1b80      	subs	r0, r0, r6
 800264c:	4580      	cmp	r8, r0
 800264e:	d3f1      	bcc.n	8002634 <HAL_UART_Transmit+0xd4>
 8002650:	f1b8 0f00 	cmp.w	r8, #0
 8002654:	d0ee      	beq.n	8002634 <HAL_UART_Transmit+0xd4>
      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
 8002656:	682c      	ldr	r4, [r5, #0]
 8002658:	6823      	ldr	r3, [r4, #0]
 800265a:	e7c3      	b.n	80025e4 <HAL_UART_Transmit+0x84>

0800265c <HAL_UART_Receive>:
{
 800265c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8002660:	4605      	mov	r5, r0
  if (huart->RxState == HAL_UART_STATE_READY)
 8002662:	f8d0 008c 	ldr.w	r0, [r0, #140]	; 0x8c
 8002666:	2820      	cmp	r0, #32
 8002668:	d143      	bne.n	80026f2 <HAL_UART_Receive+0x96>
    if ((pData == NULL) || (Size == 0U))
 800266a:	468a      	mov	sl, r1
 800266c:	b109      	cbz	r1, 8002672 <HAL_UART_Receive+0x16>
 800266e:	4614      	mov	r4, r2
 8002670:	b912      	cbnz	r2, 8002678 <HAL_UART_Receive+0x1c>
      return  HAL_ERROR;
 8002672:	2001      	movs	r0, #1
}
 8002674:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8002678:	2600      	movs	r6, #0
 800267a:	4699      	mov	r9, r3
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 800267c:	2322      	movs	r3, #34	; 0x22
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 800267e:	f8c5 6090 	str.w	r6, [r5, #144]	; 0x90
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 8002682:	f8c5 308c 	str.w	r3, [r5, #140]	; 0x8c
    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002686:	66ee      	str	r6, [r5, #108]	; 0x6c
    tickstart = HAL_GetTick();
 8002688:	f7fe fb26 	bl	8000cd8 <HAL_GetTick>
    UART_MASK_COMPUTATION(huart);
 800268c:	68ab      	ldr	r3, [r5, #8]
    huart->RxXferSize  = Size;
 800268e:	f8a5 405c 	strh.w	r4, [r5, #92]	; 0x5c
    UART_MASK_COMPUTATION(huart);
 8002692:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
    huart->RxXferCount = Size;
 8002696:	f8a5 405e 	strh.w	r4, [r5, #94]	; 0x5e
    tickstart = HAL_GetTick();
 800269a:	4607      	mov	r7, r0
    UART_MASK_COMPUTATION(huart);
 800269c:	d02c      	beq.n	80026f8 <HAL_UART_Receive+0x9c>
 800269e:	2b00      	cmp	r3, #0
 80026a0:	f040 8084 	bne.w	80027ac <HAL_UART_Receive+0x150>
 80026a4:	692b      	ldr	r3, [r5, #16]
 80026a6:	2b00      	cmp	r3, #0
 80026a8:	f000 808b 	beq.w	80027c2 <HAL_UART_Receive+0x166>
 80026ac:	267f      	movs	r6, #127	; 0x7f
 80026ae:	f8a5 6060 	strh.w	r6, [r5, #96]	; 0x60
      pdata16bits = NULL;
 80026b2:	f04f 0800 	mov.w	r8, #0
    while (huart->RxXferCount > 0U)
 80026b6:	f8b5 305e 	ldrh.w	r3, [r5, #94]	; 0x5e
 80026ba:	b29b      	uxth	r3, r3
 80026bc:	2b00      	cmp	r3, #0
 80026be:	d070      	beq.n	80027a2 <HAL_UART_Receive+0x146>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80026c0:	682c      	ldr	r4, [r5, #0]
 80026c2:	f1b9 3fff 	cmp.w	r9, #4294967295	; 0xffffffff
 80026c6:	d121      	bne.n	800270c <HAL_UART_Receive+0xb0>
 80026c8:	69e2      	ldr	r2, [r4, #28]
 80026ca:	0692      	lsls	r2, r2, #26
 80026cc:	d5fc      	bpl.n	80026c8 <HAL_UART_Receive+0x6c>
      if (pdata8bits == NULL)
 80026ce:	f1ba 0f00 	cmp.w	sl, #0
 80026d2:	d061      	beq.n	8002798 <HAL_UART_Receive+0x13c>
        *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
 80026d4:	6a63      	ldr	r3, [r4, #36]	; 0x24
 80026d6:	4033      	ands	r3, r6
 80026d8:	f80a 3b01 	strb.w	r3, [sl], #1
      if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 80026dc:	f8d5 308c 	ldr.w	r3, [r5, #140]	; 0x8c
 80026e0:	2b22      	cmp	r3, #34	; 0x22
 80026e2:	d1c6      	bne.n	8002672 <HAL_UART_Receive+0x16>
        huart->RxXferCount--;
 80026e4:	f8b5 205e 	ldrh.w	r2, [r5, #94]	; 0x5e
 80026e8:	3a01      	subs	r2, #1
 80026ea:	b292      	uxth	r2, r2
 80026ec:	f8a5 205e 	strh.w	r2, [r5, #94]	; 0x5e
 80026f0:	e7e1      	b.n	80026b6 <HAL_UART_Receive+0x5a>
    return HAL_BUSY;
 80026f2:	2002      	movs	r0, #2
}
 80026f4:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    UART_MASK_COMPUTATION(huart);
 80026f8:	692b      	ldr	r3, [r5, #16]
 80026fa:	2b00      	cmp	r3, #0
 80026fc:	d15c      	bne.n	80027b8 <HAL_UART_Receive+0x15c>
 80026fe:	f240 16ff 	movw	r6, #511	; 0x1ff
 8002702:	46d0      	mov	r8, sl
 8002704:	f8a5 6060 	strh.w	r6, [r5, #96]	; 0x60
      pdata8bits  = NULL;
 8002708:	469a      	mov	sl, r3
 800270a:	e7d4      	b.n	80026b6 <HAL_UART_Receive+0x5a>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 800270c:	69e3      	ldr	r3, [r4, #28]
 800270e:	069b      	lsls	r3, r3, #26
 8002710:	d4dd      	bmi.n	80026ce <HAL_UART_Receive+0x72>
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8002712:	f7fe fae1 	bl	8000cd8 <HAL_GetTick>
 8002716:	1bc0      	subs	r0, r0, r7
 8002718:	4581      	cmp	r9, r0
 800271a:	d338      	bcc.n	800278e <HAL_UART_Receive+0x132>
 800271c:	f1b9 0f00 	cmp.w	r9, #0
 8002720:	d035      	beq.n	800278e <HAL_UART_Receive+0x132>
      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
 8002722:	682b      	ldr	r3, [r5, #0]
 8002724:	681a      	ldr	r2, [r3, #0]
 8002726:	0752      	lsls	r2, r2, #29
 8002728:	461c      	mov	r4, r3
 800272a:	d5ca      	bpl.n	80026c2 <HAL_UART_Receive+0x66>
      {
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
 800272c:	69da      	ldr	r2, [r3, #28]
 800272e:	0710      	lsls	r0, r2, #28
 8002730:	d45c      	bmi.n	80027ec <HAL_UART_Receive+0x190>
          /* Process Unlocked */
          __HAL_UNLOCK(huart);

          return HAL_ERROR;
        }
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
 8002732:	69da      	ldr	r2, [r3, #28]
 8002734:	0511      	lsls	r1, r2, #20
 8002736:	d5c4      	bpl.n	80026c2 <HAL_UART_Receive+0x66>
        {
          /* Clear Receiver Timeout flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 8002738:	f44f 6200 	mov.w	r2, #2048	; 0x800
 800273c:	621a      	str	r2, [r3, #32]
 */
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
    uint32_t result;

   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800273e:	e853 2f00 	ldrex	r2, [r3]
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 8002742:	f422 7290 	bic.w	r2, r2, #288	; 0x120
 */
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
   uint32_t result;

   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002746:	e843 2100 	strex	r1, r2, [r3]
 800274a:	b139      	cbz	r1, 800275c <HAL_UART_Receive+0x100>
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800274c:	e853 2f00 	ldrex	r2, [r3]
 8002750:	f422 7290 	bic.w	r2, r2, #288	; 0x120
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002754:	e843 2100 	strex	r1, r2, [r3]
 8002758:	2900      	cmp	r1, #0
 800275a:	d1f7      	bne.n	800274c <HAL_UART_Receive+0xf0>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 800275c:	483a      	ldr	r0, [pc, #232]	; (8002848 <HAL_UART_Receive+0x1ec>)
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800275e:	f103 0208 	add.w	r2, r3, #8
 8002762:	e852 2f00 	ldrex	r2, [r2]
 8002766:	4002      	ands	r2, r0
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002768:	f103 0408 	add.w	r4, r3, #8
 800276c:	e844 2100 	strex	r1, r2, [r4]
 8002770:	2900      	cmp	r1, #0
 8002772:	d1f4      	bne.n	800275e <HAL_UART_Receive+0x102>

  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8002774:	6eea      	ldr	r2, [r5, #108]	; 0x6c
 8002776:	2a01      	cmp	r2, #1
 8002778:	d027      	beq.n	80027ca <HAL_UART_Receive+0x16e>
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  }

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800277a:	2300      	movs	r3, #0
  huart->RxState = HAL_UART_STATE_READY;
 800277c:	2220      	movs	r2, #32
 800277e:	f8c5 208c 	str.w	r2, [r5, #140]	; 0x8c

  /* Reset RxIsr function pointer */
  huart->RxISR = NULL;
 8002782:	676b      	str	r3, [r5, #116]	; 0x74
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002784:	66eb      	str	r3, [r5, #108]	; 0x6c
          __HAL_UNLOCK(huart);
 8002786:	f885 3084 	strb.w	r3, [r5, #132]	; 0x84
          huart->ErrorCode = HAL_UART_ERROR_RTO;
 800278a:	f8c5 2090 	str.w	r2, [r5, #144]	; 0x90
        huart->RxState = HAL_UART_STATE_READY;
 800278e:	2320      	movs	r3, #32
 8002790:	f8c5 308c 	str.w	r3, [r5, #140]	; 0x8c
        return HAL_TIMEOUT;
 8002794:	2003      	movs	r0, #3
 8002796:	e76d      	b.n	8002674 <HAL_UART_Receive+0x18>
        *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
 8002798:	6a63      	ldr	r3, [r4, #36]	; 0x24
 800279a:	4033      	ands	r3, r6
 800279c:	f828 3b02 	strh.w	r3, [r8], #2
        pdata16bits++;
 80027a0:	e79c      	b.n	80026dc <HAL_UART_Receive+0x80>
    huart->RxState = HAL_UART_STATE_READY;
 80027a2:	2320      	movs	r3, #32
 80027a4:	f8c5 308c 	str.w	r3, [r5, #140]	; 0x8c
    return HAL_OK;
 80027a8:	2000      	movs	r0, #0
 80027aa:	e763      	b.n	8002674 <HAL_UART_Receive+0x18>
    UART_MASK_COMPUTATION(huart);
 80027ac:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
 80027b0:	d014      	beq.n	80027dc <HAL_UART_Receive+0x180>
 80027b2:	f8a5 6060 	strh.w	r6, [r5, #96]	; 0x60
 80027b6:	e77c      	b.n	80026b2 <HAL_UART_Receive+0x56>
      pdata16bits = NULL;
 80027b8:	46b0      	mov	r8, r6
 80027ba:	26ff      	movs	r6, #255	; 0xff
 80027bc:	f8a5 6060 	strh.w	r6, [r5, #96]	; 0x60
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 80027c0:	e779      	b.n	80026b6 <HAL_UART_Receive+0x5a>
    UART_MASK_COMPUTATION(huart);
 80027c2:	26ff      	movs	r6, #255	; 0xff
 80027c4:	f8a5 6060 	strh.w	r6, [r5, #96]	; 0x60
 80027c8:	e773      	b.n	80026b2 <HAL_UART_Receive+0x56>
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80027ca:	e853 2f00 	ldrex	r2, [r3]
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 80027ce:	f022 0210 	bic.w	r2, r2, #16
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80027d2:	e843 2100 	strex	r1, r2, [r3]
 80027d6:	2900      	cmp	r1, #0
 80027d8:	d1f7      	bne.n	80027ca <HAL_UART_Receive+0x16e>
 80027da:	e7ce      	b.n	800277a <HAL_UART_Receive+0x11e>
    UART_MASK_COMPUTATION(huart);
 80027dc:	692b      	ldr	r3, [r5, #16]
 80027de:	2b00      	cmp	r3, #0
 80027e0:	f43f af64 	beq.w	80026ac <HAL_UART_Receive+0x50>
 80027e4:	263f      	movs	r6, #63	; 0x3f
 80027e6:	f8a5 6060 	strh.w	r6, [r5, #96]	; 0x60
 80027ea:	e762      	b.n	80026b2 <HAL_UART_Receive+0x56>
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 80027ec:	2208      	movs	r2, #8
 80027ee:	621a      	str	r2, [r3, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80027f0:	e853 2f00 	ldrex	r2, [r3]
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 80027f4:	f422 7290 	bic.w	r2, r2, #288	; 0x120
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80027f8:	e843 2100 	strex	r1, r2, [r3]
 80027fc:	2900      	cmp	r1, #0
 80027fe:	d1f7      	bne.n	80027f0 <HAL_UART_Receive+0x194>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 8002800:	4811      	ldr	r0, [pc, #68]	; (8002848 <HAL_UART_Receive+0x1ec>)
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002802:	f103 0208 	add.w	r2, r3, #8
 8002806:	e852 2f00 	ldrex	r2, [r2]
 800280a:	4002      	ands	r2, r0
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800280c:	f103 0408 	add.w	r4, r3, #8
 8002810:	e844 2100 	strex	r1, r2, [r4]
 8002814:	2900      	cmp	r1, #0
 8002816:	d1f4      	bne.n	8002802 <HAL_UART_Receive+0x1a6>
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8002818:	6eea      	ldr	r2, [r5, #108]	; 0x6c
 800281a:	2a01      	cmp	r2, #1
 800281c:	d00b      	beq.n	8002836 <HAL_UART_Receive+0x1da>
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800281e:	2300      	movs	r3, #0
  huart->RxState = HAL_UART_STATE_READY;
 8002820:	2120      	movs	r1, #32
          huart->ErrorCode = HAL_UART_ERROR_ORE;
 8002822:	2208      	movs	r2, #8
  huart->RxState = HAL_UART_STATE_READY;
 8002824:	f8c5 108c 	str.w	r1, [r5, #140]	; 0x8c
  huart->RxISR = NULL;
 8002828:	676b      	str	r3, [r5, #116]	; 0x74
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800282a:	66eb      	str	r3, [r5, #108]	; 0x6c
          __HAL_UNLOCK(huart);
 800282c:	f885 3084 	strb.w	r3, [r5, #132]	; 0x84
          huart->ErrorCode = HAL_UART_ERROR_ORE;
 8002830:	f8c5 2090 	str.w	r2, [r5, #144]	; 0x90
          return HAL_ERROR;
 8002834:	e7ab      	b.n	800278e <HAL_UART_Receive+0x132>
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002836:	e853 2f00 	ldrex	r2, [r3]
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800283a:	f022 0210 	bic.w	r2, r2, #16
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800283e:	e843 2100 	strex	r1, r2, [r3]
 8002842:	2900      	cmp	r1, #0
 8002844:	d1f7      	bne.n	8002836 <HAL_UART_Receive+0x1da>
 8002846:	e7ea      	b.n	800281e <HAL_UART_Receive+0x1c2>
 8002848:	effffffe 	.word	0xeffffffe

0800284c <UART_SetConfig>:
{
 800284c:	b538      	push	{r3, r4, r5, lr}
 800284e:	4604      	mov	r4, r0
  if (UART_INSTANCE_LOWPOWER(huart))
 8002850:	6803      	ldr	r3, [r0, #0]
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
 8002852:	6882      	ldr	r2, [r0, #8]
 8002854:	6900      	ldr	r0, [r0, #16]
 8002856:	6961      	ldr	r1, [r4, #20]
  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
 8002858:	681d      	ldr	r5, [r3, #0]
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
 800285a:	4302      	orrs	r2, r0
 800285c:	430a      	orrs	r2, r1
 800285e:	69e0      	ldr	r0, [r4, #28]
  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
 8002860:	49a6      	ldr	r1, [pc, #664]	; (8002afc <UART_SetConfig+0x2b0>)
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
 8002862:	4302      	orrs	r2, r0
  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
 8002864:	4029      	ands	r1, r5
 8002866:	430a      	orrs	r2, r1
 8002868:	601a      	str	r2, [r3, #0]
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 800286a:	685a      	ldr	r2, [r3, #4]
 800286c:	68e1      	ldr	r1, [r4, #12]
 800286e:	f422 5240 	bic.w	r2, r2, #12288	; 0x3000
 8002872:	430a      	orrs	r2, r1
  if (!(UART_INSTANCE_LOWPOWER(huart)))
 8002874:	49a2      	ldr	r1, [pc, #648]	; (8002b00 <UART_SetConfig+0x2b4>)
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8002876:	605a      	str	r2, [r3, #4]
  if (!(UART_INSTANCE_LOWPOWER(huart)))
 8002878:	428b      	cmp	r3, r1
  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
 800287a:	69a2      	ldr	r2, [r4, #24]
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 800287c:	6899      	ldr	r1, [r3, #8]
  if (!(UART_INSTANCE_LOWPOWER(huart)))
 800287e:	d06b      	beq.n	8002958 <UART_SetConfig+0x10c>
    tmpreg |= huart->Init.OneBitSampling;
 8002880:	6a25      	ldr	r5, [r4, #32]
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 8002882:	f021 416e 	bic.w	r1, r1, #3992977408	; 0xee000000
 8002886:	f421 6130 	bic.w	r1, r1, #2816	; 0xb00
    tmpreg |= huart->Init.OneBitSampling;
 800288a:	432a      	orrs	r2, r5
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 800288c:	430a      	orrs	r2, r1
 800288e:	609a      	str	r2, [r3, #8]
  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
 8002890:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8002892:	6a61      	ldr	r1, [r4, #36]	; 0x24
 8002894:	f022 020f 	bic.w	r2, r2, #15
 8002898:	430a      	orrs	r2, r1
 800289a:	62da      	str	r2, [r3, #44]	; 0x2c
  UART_GETCLOCKSOURCE(huart, clocksource);
 800289c:	4a99      	ldr	r2, [pc, #612]	; (8002b04 <UART_SetConfig+0x2b8>)
 800289e:	4293      	cmp	r3, r2
 80028a0:	d012      	beq.n	80028c8 <UART_SetConfig+0x7c>
 80028a2:	4a99      	ldr	r2, [pc, #612]	; (8002b08 <UART_SetConfig+0x2bc>)
 80028a4:	4293      	cmp	r3, r2
 80028a6:	d036      	beq.n	8002916 <UART_SetConfig+0xca>
 80028a8:	4a98      	ldr	r2, [pc, #608]	; (8002b0c <UART_SetConfig+0x2c0>)
 80028aa:	4293      	cmp	r3, r2
 80028ac:	f000 80fa 	beq.w	8002aa4 <UART_SetConfig+0x258>
 80028b0:	4a97      	ldr	r2, [pc, #604]	; (8002b10 <UART_SetConfig+0x2c4>)
 80028b2:	4293      	cmp	r3, r2
 80028b4:	f000 80a5 	beq.w	8002a02 <UART_SetConfig+0x1b6>
        ret = HAL_ERROR;
 80028b8:	2001      	movs	r0, #1
  huart->RxISR = NULL;
 80028ba:	2300      	movs	r3, #0
  huart->NbRxDataToProcess = 1;
 80028bc:	f04f 1201 	mov.w	r2, #65537	; 0x10001
  huart->TxISR = NULL;
 80028c0:	e9c4 331d 	strd	r3, r3, [r4, #116]	; 0x74
  huart->NbRxDataToProcess = 1;
 80028c4:	66a2      	str	r2, [r4, #104]	; 0x68
}
 80028c6:	bd38      	pop	{r3, r4, r5, pc}
  UART_GETCLOCKSOURCE(huart, clocksource);
 80028c8:	4b92      	ldr	r3, [pc, #584]	; (8002b14 <UART_SetConfig+0x2c8>)
 80028ca:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 80028ce:	f003 0303 	and.w	r3, r3, #3
 80028d2:	3b01      	subs	r3, #1
 80028d4:	2b02      	cmp	r3, #2
 80028d6:	f240 808e 	bls.w	80029f6 <UART_SetConfig+0x1aa>
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 80028da:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
 80028de:	f000 80fe 	beq.w	8002ade <UART_SetConfig+0x292>
        pclk = HAL_RCC_GetPCLK2Freq();
 80028e2:	f7ff fa55 	bl	8001d90 <HAL_RCC_GetPCLK2Freq>
    if (pclk != 0U)
 80028e6:	2800      	cmp	r0, #0
 80028e8:	f000 80da 	beq.w	8002aa0 <UART_SetConfig+0x254>
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 80028ec:	6a61      	ldr	r1, [r4, #36]	; 0x24
 80028ee:	6862      	ldr	r2, [r4, #4]
 80028f0:	4b89      	ldr	r3, [pc, #548]	; (8002b18 <UART_SetConfig+0x2cc>)
 80028f2:	f833 3011 	ldrh.w	r3, [r3, r1, lsl #1]
 80028f6:	fbb0 f0f3 	udiv	r0, r0, r3
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 80028fa:	f64f 71ef 	movw	r1, #65519	; 0xffef
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 80028fe:	eb00 0352 	add.w	r3, r0, r2, lsr #1
 8002902:	fbb3 f3f2 	udiv	r3, r3, r2
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 8002906:	f1a3 0210 	sub.w	r2, r3, #16
 800290a:	428a      	cmp	r2, r1
 800290c:	d8d4      	bhi.n	80028b8 <UART_SetConfig+0x6c>
        huart->Instance->BRR = (uint16_t)usartdiv;
 800290e:	6822      	ldr	r2, [r4, #0]
 8002910:	2000      	movs	r0, #0
 8002912:	60d3      	str	r3, [r2, #12]
 8002914:	e7d1      	b.n	80028ba <UART_SetConfig+0x6e>
  UART_GETCLOCKSOURCE(huart, clocksource);
 8002916:	4b7f      	ldr	r3, [pc, #508]	; (8002b14 <UART_SetConfig+0x2c8>)
 8002918:	4a80      	ldr	r2, [pc, #512]	; (8002b1c <UART_SetConfig+0x2d0>)
 800291a:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 800291e:	f003 030c 	and.w	r3, r3, #12
 8002922:	5cd3      	ldrb	r3, [r2, r3]
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8002924:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
 8002928:	d07d      	beq.n	8002a26 <UART_SetConfig+0x1da>
    switch (clocksource)
 800292a:	2b08      	cmp	r3, #8
 800292c:	d8c4      	bhi.n	80028b8 <UART_SetConfig+0x6c>
 800292e:	a201      	add	r2, pc, #4	; (adr r2, 8002934 <UART_SetConfig+0xe8>)
 8002930:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8002934:	08002a5f 	.word	0x08002a5f
 8002938:	080028e3 	.word	0x080028e3
 800293c:	08002adb 	.word	0x08002adb
 8002940:	080028b9 	.word	0x080028b9
 8002944:	08002a21 	.word	0x08002a21
 8002948:	080028b9 	.word	0x080028b9
 800294c:	080028b9 	.word	0x080028b9
 8002950:	080028b9 	.word	0x080028b9
 8002954:	08002acb 	.word	0x08002acb
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 8002958:	f021 416e 	bic.w	r1, r1, #3992977408	; 0xee000000
 800295c:	f421 6130 	bic.w	r1, r1, #2816	; 0xb00
 8002960:	430a      	orrs	r2, r1
 8002962:	609a      	str	r2, [r3, #8]
  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
 8002964:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8002966:	6a61      	ldr	r1, [r4, #36]	; 0x24
  UART_GETCLOCKSOURCE(huart, clocksource);
 8002968:	486a      	ldr	r0, [pc, #424]	; (8002b14 <UART_SetConfig+0x2c8>)
  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
 800296a:	f022 020f 	bic.w	r2, r2, #15
 800296e:	430a      	orrs	r2, r1
 8002970:	62da      	str	r2, [r3, #44]	; 0x2c
  UART_GETCLOCKSOURCE(huart, clocksource);
 8002972:	f8d0 3088 	ldr.w	r3, [r0, #136]	; 0x88
 8002976:	f403 6340 	and.w	r3, r3, #3072	; 0xc00
 800297a:	f5b3 6f00 	cmp.w	r3, #2048	; 0x800
 800297e:	f000 80aa 	beq.w	8002ad6 <UART_SetConfig+0x28a>
 8002982:	d80b      	bhi.n	800299c <UART_SetConfig+0x150>
 8002984:	2b00      	cmp	r3, #0
 8002986:	d039      	beq.n	80029fc <UART_SetConfig+0x1b0>
 8002988:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 800298c:	d194      	bne.n	80028b8 <UART_SetConfig+0x6c>
        pclk = HAL_RCC_GetSysClockFreq();
 800298e:	f7ff f8a3 	bl	8001ad8 <HAL_RCC_GetSysClockFreq>
    if (pclk != 0U)
 8002992:	2800      	cmp	r0, #0
 8002994:	f000 8084 	beq.w	8002aa0 <UART_SetConfig+0x254>
      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
 8002998:	6a61      	ldr	r1, [r4, #36]	; 0x24
 800299a:	e004      	b.n	80029a6 <UART_SetConfig+0x15a>
  UART_GETCLOCKSOURCE(huart, clocksource);
 800299c:	f5b3 6f40 	cmp.w	r3, #3072	; 0xc00
 80029a0:	d18a      	bne.n	80028b8 <UART_SetConfig+0x6c>
        pclk = (uint32_t) LSE_VALUE;
 80029a2:	f44f 4000 	mov.w	r0, #32768	; 0x8000
      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
 80029a6:	4b5c      	ldr	r3, [pc, #368]	; (8002b18 <UART_SetConfig+0x2cc>)
      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
 80029a8:	6865      	ldr	r5, [r4, #4]
      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
 80029aa:	f833 2011 	ldrh.w	r2, [r3, r1, lsl #1]
 80029ae:	fbb0 f3f2 	udiv	r3, r0, r2
      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
 80029b2:	eb05 0145 	add.w	r1, r5, r5, lsl #1
 80029b6:	4299      	cmp	r1, r3
 80029b8:	f63f af7e 	bhi.w	80028b8 <UART_SetConfig+0x6c>
 80029bc:	ebb3 3f05 	cmp.w	r3, r5, lsl #12
 80029c0:	f63f af7a 	bhi.w	80028b8 <UART_SetConfig+0x6c>
        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 80029c4:	2300      	movs	r3, #0
 80029c6:	4619      	mov	r1, r3
 80029c8:	f7fd fc26 	bl	8000218 <__aeabi_uldivmod>
 80029cc:	0209      	lsls	r1, r1, #8
 80029ce:	0203      	lsls	r3, r0, #8
 80029d0:	ea41 6110 	orr.w	r1, r1, r0, lsr #24
 80029d4:	0868      	lsrs	r0, r5, #1
 80029d6:	1818      	adds	r0, r3, r0
 80029d8:	462a      	mov	r2, r5
 80029da:	f04f 0300 	mov.w	r3, #0
 80029de:	f141 0100 	adc.w	r1, r1, #0
 80029e2:	f7fd fc19 	bl	8000218 <__aeabi_uldivmod>
        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
 80029e6:	4a4e      	ldr	r2, [pc, #312]	; (8002b20 <UART_SetConfig+0x2d4>)
 80029e8:	f5a0 7140 	sub.w	r1, r0, #768	; 0x300
 80029ec:	4291      	cmp	r1, r2
        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 80029ee:	4603      	mov	r3, r0
        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
 80029f0:	f63f af62 	bhi.w	80028b8 <UART_SetConfig+0x6c>
 80029f4:	e78b      	b.n	800290e <UART_SetConfig+0xc2>
 80029f6:	4a4b      	ldr	r2, [pc, #300]	; (8002b24 <UART_SetConfig+0x2d8>)
 80029f8:	5cd3      	ldrb	r3, [r2, r3]
  if (UART_INSTANCE_LOWPOWER(huart))
 80029fa:	e793      	b.n	8002924 <UART_SetConfig+0xd8>
        pclk = HAL_RCC_GetPCLK1Freq();
 80029fc:	f7ff f9b6 	bl	8001d6c <HAL_RCC_GetPCLK1Freq>
        break;
 8002a00:	e7c7      	b.n	8002992 <UART_SetConfig+0x146>
  UART_GETCLOCKSOURCE(huart, clocksource);
 8002a02:	4b44      	ldr	r3, [pc, #272]	; (8002b14 <UART_SetConfig+0x2c8>)
 8002a04:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002a08:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
 8002a0c:	2b80      	cmp	r3, #128	; 0x80
 8002a0e:	d06e      	beq.n	8002aee <UART_SetConfig+0x2a2>
 8002a10:	d85e      	bhi.n	8002ad0 <UART_SetConfig+0x284>
 8002a12:	b30b      	cbz	r3, 8002a58 <UART_SetConfig+0x20c>
 8002a14:	2b40      	cmp	r3, #64	; 0x40
 8002a16:	f47f af4f 	bne.w	80028b8 <UART_SetConfig+0x6c>
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8002a1a:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
 8002a1e:	d021      	beq.n	8002a64 <UART_SetConfig+0x218>
        pclk = HAL_RCC_GetSysClockFreq();
 8002a20:	f7ff f85a 	bl	8001ad8 <HAL_RCC_GetSysClockFreq>
        break;
 8002a24:	e75f      	b.n	80028e6 <UART_SetConfig+0x9a>
    switch (clocksource)
 8002a26:	2b08      	cmp	r3, #8
 8002a28:	f63f af46 	bhi.w	80028b8 <UART_SetConfig+0x6c>
 8002a2c:	a201      	add	r2, pc, #4	; (adr r2, 8002a34 <UART_SetConfig+0x1e8>)
 8002a2e:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8002a32:	bf00      	nop
 8002a34:	08002ae5 	.word	0x08002ae5
 8002a38:	08002adf 	.word	0x08002adf
 8002a3c:	08002aeb 	.word	0x08002aeb
 8002a40:	080028b9 	.word	0x080028b9
 8002a44:	08002a65 	.word	0x08002a65
 8002a48:	080028b9 	.word	0x080028b9
 8002a4c:	080028b9 	.word	0x080028b9
 8002a50:	080028b9 	.word	0x080028b9
 8002a54:	08002a6d 	.word	0x08002a6d
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8002a58:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
 8002a5c:	d042      	beq.n	8002ae4 <UART_SetConfig+0x298>
        pclk = HAL_RCC_GetPCLK1Freq();
 8002a5e:	f7ff f985 	bl	8001d6c <HAL_RCC_GetPCLK1Freq>
        break;
 8002a62:	e740      	b.n	80028e6 <UART_SetConfig+0x9a>
        pclk = HAL_RCC_GetSysClockFreq();
 8002a64:	f7ff f838 	bl	8001ad8 <HAL_RCC_GetSysClockFreq>
    if (pclk != 0U)
 8002a68:	b1d0      	cbz	r0, 8002aa0 <UART_SetConfig+0x254>
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 8002a6a:	6a61      	ldr	r1, [r4, #36]	; 0x24
 8002a6c:	6862      	ldr	r2, [r4, #4]
 8002a6e:	4b2a      	ldr	r3, [pc, #168]	; (8002b18 <UART_SetConfig+0x2cc>)
 8002a70:	f833 1011 	ldrh.w	r1, [r3, r1, lsl #1]
 8002a74:	fbb0 f0f1 	udiv	r0, r0, r1
 8002a78:	0853      	lsrs	r3, r2, #1
 8002a7a:	eb03 0040 	add.w	r0, r3, r0, lsl #1
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 8002a7e:	f64f 73ef 	movw	r3, #65519	; 0xffef
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 8002a82:	fbb0 f0f2 	udiv	r0, r0, r2
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 8002a86:	f1a0 0210 	sub.w	r2, r0, #16
 8002a8a:	429a      	cmp	r2, r3
 8002a8c:	f63f af14 	bhi.w	80028b8 <UART_SetConfig+0x6c>
        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
 8002a90:	f020 030f 	bic.w	r3, r0, #15
        huart->Instance->BRR = brrtemp;
 8002a94:	6822      	ldr	r2, [r4, #0]
        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
 8002a96:	b29b      	uxth	r3, r3
        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
 8002a98:	f3c0 0042 	ubfx	r0, r0, #1, #3
        huart->Instance->BRR = brrtemp;
 8002a9c:	4318      	orrs	r0, r3
 8002a9e:	60d0      	str	r0, [r2, #12]
 8002aa0:	2000      	movs	r0, #0
 8002aa2:	e70a      	b.n	80028ba <UART_SetConfig+0x6e>
  UART_GETCLOCKSOURCE(huart, clocksource);
 8002aa4:	4b1b      	ldr	r3, [pc, #108]	; (8002b14 <UART_SetConfig+0x2c8>)
 8002aa6:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002aaa:	f003 0330 	and.w	r3, r3, #48	; 0x30
 8002aae:	2b20      	cmp	r3, #32
 8002ab0:	d01d      	beq.n	8002aee <UART_SetConfig+0x2a2>
 8002ab2:	d804      	bhi.n	8002abe <UART_SetConfig+0x272>
 8002ab4:	2b00      	cmp	r3, #0
 8002ab6:	d0cf      	beq.n	8002a58 <UART_SetConfig+0x20c>
 8002ab8:	2b10      	cmp	r3, #16
 8002aba:	d0ae      	beq.n	8002a1a <UART_SetConfig+0x1ce>
 8002abc:	e6fc      	b.n	80028b8 <UART_SetConfig+0x6c>
 8002abe:	2b30      	cmp	r3, #48	; 0x30
 8002ac0:	f47f aefa 	bne.w	80028b8 <UART_SetConfig+0x6c>
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8002ac4:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
 8002ac8:	d0d0      	beq.n	8002a6c <UART_SetConfig+0x220>
    switch (clocksource)
 8002aca:	f44f 4000 	mov.w	r0, #32768	; 0x8000
 8002ace:	e70e      	b.n	80028ee <UART_SetConfig+0xa2>
  UART_GETCLOCKSOURCE(huart, clocksource);
 8002ad0:	2bc0      	cmp	r3, #192	; 0xc0
 8002ad2:	d0f7      	beq.n	8002ac4 <UART_SetConfig+0x278>
 8002ad4:	e6f0      	b.n	80028b8 <UART_SetConfig+0x6c>
 8002ad6:	4814      	ldr	r0, [pc, #80]	; (8002b28 <UART_SetConfig+0x2dc>)
 8002ad8:	e765      	b.n	80029a6 <UART_SetConfig+0x15a>
        pclk = (uint32_t) HSI_VALUE;
 8002ada:	4813      	ldr	r0, [pc, #76]	; (8002b28 <UART_SetConfig+0x2dc>)
 8002adc:	e707      	b.n	80028ee <UART_SetConfig+0xa2>
        pclk = HAL_RCC_GetPCLK2Freq();
 8002ade:	f7ff f957 	bl	8001d90 <HAL_RCC_GetPCLK2Freq>
        break;
 8002ae2:	e7c1      	b.n	8002a68 <UART_SetConfig+0x21c>
        pclk = HAL_RCC_GetPCLK1Freq();
 8002ae4:	f7ff f942 	bl	8001d6c <HAL_RCC_GetPCLK1Freq>
        break;
 8002ae8:	e7be      	b.n	8002a68 <UART_SetConfig+0x21c>
        pclk = (uint32_t) HSI_VALUE;
 8002aea:	480f      	ldr	r0, [pc, #60]	; (8002b28 <UART_SetConfig+0x2dc>)
 8002aec:	e7be      	b.n	8002a6c <UART_SetConfig+0x220>
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8002aee:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
        pclk = (uint32_t) HSI_VALUE;
 8002af2:	480d      	ldr	r0, [pc, #52]	; (8002b28 <UART_SetConfig+0x2dc>)
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8002af4:	f47f aefb 	bne.w	80028ee <UART_SetConfig+0xa2>
 8002af8:	e7b8      	b.n	8002a6c <UART_SetConfig+0x220>
 8002afa:	bf00      	nop
 8002afc:	cfff69f3 	.word	0xcfff69f3
 8002b00:	40008000 	.word	0x40008000
 8002b04:	40013800 	.word	0x40013800
 8002b08:	40004400 	.word	0x40004400
 8002b0c:	40004800 	.word	0x40004800
 8002b10:	40004c00 	.word	0x40004c00
 8002b14:	40021000 	.word	0x40021000
 8002b18:	08003094 	.word	0x08003094
 8002b1c:	08003084 	.word	0x08003084
 8002b20:	000ffcff 	.word	0x000ffcff
 8002b24:	08003080 	.word	0x08003080
 8002b28:	00f42400 	.word	0x00f42400

08002b2c <UART_AdvFeatureConfig>:
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
 8002b2c:	6a83      	ldr	r3, [r0, #40]	; 0x28
 8002b2e:	071a      	lsls	r2, r3, #28
{
 8002b30:	b410      	push	{r4}
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
 8002b32:	d506      	bpl.n	8002b42 <UART_AdvFeatureConfig+0x16>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
 8002b34:	6801      	ldr	r1, [r0, #0]
 8002b36:	6b84      	ldr	r4, [r0, #56]	; 0x38
 8002b38:	684a      	ldr	r2, [r1, #4]
 8002b3a:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
 8002b3e:	4322      	orrs	r2, r4
 8002b40:	604a      	str	r2, [r1, #4]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
 8002b42:	07dc      	lsls	r4, r3, #31
 8002b44:	d506      	bpl.n	8002b54 <UART_AdvFeatureConfig+0x28>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
 8002b46:	6801      	ldr	r1, [r0, #0]
 8002b48:	6ac4      	ldr	r4, [r0, #44]	; 0x2c
 8002b4a:	684a      	ldr	r2, [r1, #4]
 8002b4c:	f422 3200 	bic.w	r2, r2, #131072	; 0x20000
 8002b50:	4322      	orrs	r2, r4
 8002b52:	604a      	str	r2, [r1, #4]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
 8002b54:	0799      	lsls	r1, r3, #30
 8002b56:	d506      	bpl.n	8002b66 <UART_AdvFeatureConfig+0x3a>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
 8002b58:	6801      	ldr	r1, [r0, #0]
 8002b5a:	6b04      	ldr	r4, [r0, #48]	; 0x30
 8002b5c:	684a      	ldr	r2, [r1, #4]
 8002b5e:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
 8002b62:	4322      	orrs	r2, r4
 8002b64:	604a      	str	r2, [r1, #4]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
 8002b66:	075a      	lsls	r2, r3, #29
 8002b68:	d506      	bpl.n	8002b78 <UART_AdvFeatureConfig+0x4c>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
 8002b6a:	6801      	ldr	r1, [r0, #0]
 8002b6c:	6b44      	ldr	r4, [r0, #52]	; 0x34
 8002b6e:	684a      	ldr	r2, [r1, #4]
 8002b70:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 8002b74:	4322      	orrs	r2, r4
 8002b76:	604a      	str	r2, [r1, #4]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
 8002b78:	06dc      	lsls	r4, r3, #27
 8002b7a:	d506      	bpl.n	8002b8a <UART_AdvFeatureConfig+0x5e>
    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
 8002b7c:	6801      	ldr	r1, [r0, #0]
 8002b7e:	6bc4      	ldr	r4, [r0, #60]	; 0x3c
 8002b80:	688a      	ldr	r2, [r1, #8]
 8002b82:	f422 5280 	bic.w	r2, r2, #4096	; 0x1000
 8002b86:	4322      	orrs	r2, r4
 8002b88:	608a      	str	r2, [r1, #8]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
 8002b8a:	0699      	lsls	r1, r3, #26
 8002b8c:	d506      	bpl.n	8002b9c <UART_AdvFeatureConfig+0x70>
    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
 8002b8e:	6801      	ldr	r1, [r0, #0]
 8002b90:	6c04      	ldr	r4, [r0, #64]	; 0x40
 8002b92:	688a      	ldr	r2, [r1, #8]
 8002b94:	f422 5200 	bic.w	r2, r2, #8192	; 0x2000
 8002b98:	4322      	orrs	r2, r4
 8002b9a:	608a      	str	r2, [r1, #8]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
 8002b9c:	065a      	lsls	r2, r3, #25
 8002b9e:	d509      	bpl.n	8002bb4 <UART_AdvFeatureConfig+0x88>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
 8002ba0:	6801      	ldr	r1, [r0, #0]
 8002ba2:	6c44      	ldr	r4, [r0, #68]	; 0x44
 8002ba4:	684a      	ldr	r2, [r1, #4]
 8002ba6:	f422 1280 	bic.w	r2, r2, #1048576	; 0x100000
 8002baa:	4322      	orrs	r2, r4
    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
 8002bac:	f5b4 1f80 	cmp.w	r4, #1048576	; 0x100000
    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
 8002bb0:	604a      	str	r2, [r1, #4]
    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
 8002bb2:	d00b      	beq.n	8002bcc <UART_AdvFeatureConfig+0xa0>
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
 8002bb4:	061b      	lsls	r3, r3, #24
 8002bb6:	d506      	bpl.n	8002bc6 <UART_AdvFeatureConfig+0x9a>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
 8002bb8:	6802      	ldr	r2, [r0, #0]
 8002bba:	6cc1      	ldr	r1, [r0, #76]	; 0x4c
 8002bbc:	6853      	ldr	r3, [r2, #4]
 8002bbe:	f423 2300 	bic.w	r3, r3, #524288	; 0x80000
 8002bc2:	430b      	orrs	r3, r1
 8002bc4:	6053      	str	r3, [r2, #4]
}
 8002bc6:	f85d 4b04 	ldr.w	r4, [sp], #4
 8002bca:	4770      	bx	lr
      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
 8002bcc:	684a      	ldr	r2, [r1, #4]
 8002bce:	6c84      	ldr	r4, [r0, #72]	; 0x48
 8002bd0:	f422 02c0 	bic.w	r2, r2, #6291456	; 0x600000
 8002bd4:	4322      	orrs	r2, r4
 8002bd6:	604a      	str	r2, [r1, #4]
 8002bd8:	e7ec      	b.n	8002bb4 <UART_AdvFeatureConfig+0x88>
 8002bda:	bf00      	nop

08002bdc <UART_CheckIdleState>:
{
 8002bdc:	b538      	push	{r3, r4, r5, lr}
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8002bde:	2300      	movs	r3, #0
{
 8002be0:	4604      	mov	r4, r0
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8002be2:	f8c0 3090 	str.w	r3, [r0, #144]	; 0x90
  tickstart = HAL_GetTick();
 8002be6:	f7fe f877 	bl	8000cd8 <HAL_GetTick>
  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
 8002bea:	6822      	ldr	r2, [r4, #0]
 8002bec:	6813      	ldr	r3, [r2, #0]
 8002bee:	071b      	lsls	r3, r3, #28
  tickstart = HAL_GetTick();
 8002bf0:	4605      	mov	r5, r0
  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
 8002bf2:	d40e      	bmi.n	8002c12 <UART_CheckIdleState+0x36>
  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
 8002bf4:	6813      	ldr	r3, [r2, #0]
 8002bf6:	0759      	lsls	r1, r3, #29
 8002bf8:	d432      	bmi.n	8002c60 <UART_CheckIdleState+0x84>
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002bfa:	2300      	movs	r3, #0
  huart->gState = HAL_UART_STATE_READY;
 8002bfc:	2220      	movs	r2, #32
  __HAL_UNLOCK(huart);
 8002bfe:	f884 3084 	strb.w	r3, [r4, #132]	; 0x84
  huart->gState = HAL_UART_STATE_READY;
 8002c02:	f8c4 2088 	str.w	r2, [r4, #136]	; 0x88
  return HAL_OK;
 8002c06:	4618      	mov	r0, r3
  huart->RxState = HAL_UART_STATE_READY;
 8002c08:	f8c4 208c 	str.w	r2, [r4, #140]	; 0x8c
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002c0c:	66e3      	str	r3, [r4, #108]	; 0x6c
  huart->RxEventType = HAL_UART_RXEVENT_TC;
 8002c0e:	6723      	str	r3, [r4, #112]	; 0x70
}
 8002c10:	bd38      	pop	{r3, r4, r5, pc}
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8002c12:	69d3      	ldr	r3, [r2, #28]
 8002c14:	0298      	lsls	r0, r3, #10
 8002c16:	d4ed      	bmi.n	8002bf4 <UART_CheckIdleState+0x18>
 8002c18:	e00c      	b.n	8002c34 <UART_CheckIdleState+0x58>
      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
 8002c1a:	6819      	ldr	r1, [r3, #0]
 8002c1c:	0749      	lsls	r1, r1, #29
 8002c1e:	461a      	mov	r2, r3
 8002c20:	d505      	bpl.n	8002c2e <UART_CheckIdleState+0x52>
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
 8002c22:	69d9      	ldr	r1, [r3, #28]
 8002c24:	0708      	lsls	r0, r1, #28
 8002c26:	d44f      	bmi.n	8002cc8 <UART_CheckIdleState+0xec>
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
 8002c28:	69d9      	ldr	r1, [r3, #28]
 8002c2a:	0509      	lsls	r1, r1, #20
 8002c2c:	d47a      	bmi.n	8002d24 <UART_CheckIdleState+0x148>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8002c2e:	69db      	ldr	r3, [r3, #28]
 8002c30:	0298      	lsls	r0, r3, #10
 8002c32:	d4df      	bmi.n	8002bf4 <UART_CheckIdleState+0x18>
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8002c34:	f7fe f850 	bl	8000cd8 <HAL_GetTick>
 8002c38:	1b43      	subs	r3, r0, r5
 8002c3a:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
 8002c3e:	6823      	ldr	r3, [r4, #0]
 8002c40:	d3eb      	bcc.n	8002c1a <UART_CheckIdleState+0x3e>
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002c42:	e853 2f00 	ldrex	r2, [r3]
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
 8002c46:	f022 0280 	bic.w	r2, r2, #128	; 0x80
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002c4a:	e843 2100 	strex	r1, r2, [r3]
 8002c4e:	2900      	cmp	r1, #0
 8002c50:	d1f7      	bne.n	8002c42 <UART_CheckIdleState+0x66>
      huart->gState = HAL_UART_STATE_READY;
 8002c52:	2320      	movs	r3, #32
      __HAL_UNLOCK(huart);
 8002c54:	f884 1084 	strb.w	r1, [r4, #132]	; 0x84
      huart->gState = HAL_UART_STATE_READY;
 8002c58:	f8c4 3088 	str.w	r3, [r4, #136]	; 0x88
      return HAL_TIMEOUT;
 8002c5c:	2003      	movs	r0, #3
}
 8002c5e:	bd38      	pop	{r3, r4, r5, pc}
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8002c60:	69d3      	ldr	r3, [r2, #28]
 8002c62:	025b      	lsls	r3, r3, #9
 8002c64:	d4c9      	bmi.n	8002bfa <UART_CheckIdleState+0x1e>
 8002c66:	e00d      	b.n	8002c84 <UART_CheckIdleState+0xa8>
      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
 8002c68:	681a      	ldr	r2, [r3, #0]
 8002c6a:	0750      	lsls	r0, r2, #29
 8002c6c:	d507      	bpl.n	8002c7e <UART_CheckIdleState+0xa2>
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
 8002c6e:	69da      	ldr	r2, [r3, #28]
 8002c70:	0711      	lsls	r1, r2, #28
 8002c72:	f100 8085 	bmi.w	8002d80 <UART_CheckIdleState+0x1a4>
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
 8002c76:	69da      	ldr	r2, [r3, #28]
 8002c78:	0512      	lsls	r2, r2, #20
 8002c7a:	f100 80af 	bmi.w	8002ddc <UART_CheckIdleState+0x200>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8002c7e:	69db      	ldr	r3, [r3, #28]
 8002c80:	025b      	lsls	r3, r3, #9
 8002c82:	d4ba      	bmi.n	8002bfa <UART_CheckIdleState+0x1e>
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8002c84:	f7fe f828 	bl	8000cd8 <HAL_GetTick>
 8002c88:	1b43      	subs	r3, r0, r5
 8002c8a:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
 8002c8e:	6823      	ldr	r3, [r4, #0]
 8002c90:	d3ea      	bcc.n	8002c68 <UART_CheckIdleState+0x8c>
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002c92:	e853 2f00 	ldrex	r2, [r3]
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 8002c96:	f422 7290 	bic.w	r2, r2, #288	; 0x120
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002c9a:	e843 2100 	strex	r1, r2, [r3]
 8002c9e:	2900      	cmp	r1, #0
 8002ca0:	d1f7      	bne.n	8002c92 <UART_CheckIdleState+0xb6>
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002ca2:	f103 0208 	add.w	r2, r3, #8
 8002ca6:	e852 2f00 	ldrex	r2, [r2]
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8002caa:	f022 0201 	bic.w	r2, r2, #1
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002cae:	f103 0008 	add.w	r0, r3, #8
 8002cb2:	e840 2100 	strex	r1, r2, [r0]
 8002cb6:	2900      	cmp	r1, #0
 8002cb8:	d1f3      	bne.n	8002ca2 <UART_CheckIdleState+0xc6>
      huart->RxState = HAL_UART_STATE_READY;
 8002cba:	2320      	movs	r3, #32
      __HAL_UNLOCK(huart);
 8002cbc:	f884 1084 	strb.w	r1, [r4, #132]	; 0x84
      huart->RxState = HAL_UART_STATE_READY;
 8002cc0:	f8c4 308c 	str.w	r3, [r4, #140]	; 0x8c
      return HAL_TIMEOUT;
 8002cc4:	2003      	movs	r0, #3
}
 8002cc6:	bd38      	pop	{r3, r4, r5, pc}
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 8002cc8:	2208      	movs	r2, #8
 8002cca:	621a      	str	r2, [r3, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002ccc:	e853 2f00 	ldrex	r2, [r3]
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 8002cd0:	f422 7290 	bic.w	r2, r2, #288	; 0x120
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002cd4:	e843 2100 	strex	r1, r2, [r3]
 8002cd8:	2900      	cmp	r1, #0
 8002cda:	d1f7      	bne.n	8002ccc <UART_CheckIdleState+0xf0>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 8002cdc:	4856      	ldr	r0, [pc, #344]	; (8002e38 <UART_CheckIdleState+0x25c>)
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002cde:	f103 0208 	add.w	r2, r3, #8
 8002ce2:	e852 2f00 	ldrex	r2, [r2]
 8002ce6:	4002      	ands	r2, r0
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002ce8:	f103 0508 	add.w	r5, r3, #8
 8002cec:	e845 2100 	strex	r1, r2, [r5]
 8002cf0:	2900      	cmp	r1, #0
 8002cf2:	d1f4      	bne.n	8002cde <UART_CheckIdleState+0x102>
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8002cf4:	6ee2      	ldr	r2, [r4, #108]	; 0x6c
 8002cf6:	2a01      	cmp	r2, #1
 8002cf8:	d00b      	beq.n	8002d12 <UART_CheckIdleState+0x136>
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002cfa:	2200      	movs	r2, #0
  huart->RxState = HAL_UART_STATE_READY;
 8002cfc:	2020      	movs	r0, #32
          huart->ErrorCode = HAL_UART_ERROR_ORE;
 8002cfe:	2108      	movs	r1, #8
  huart->RxState = HAL_UART_STATE_READY;
 8002d00:	f8c4 008c 	str.w	r0, [r4, #140]	; 0x8c
  huart->RxISR = NULL;
 8002d04:	6762      	str	r2, [r4, #116]	; 0x74
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002d06:	66e2      	str	r2, [r4, #108]	; 0x6c
          __HAL_UNLOCK(huart);
 8002d08:	f884 2084 	strb.w	r2, [r4, #132]	; 0x84
          huart->ErrorCode = HAL_UART_ERROR_ORE;
 8002d0c:	f8c4 1090 	str.w	r1, [r4, #144]	; 0x90
          return HAL_ERROR;
 8002d10:	e797      	b.n	8002c42 <UART_CheckIdleState+0x66>
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002d12:	e853 2f00 	ldrex	r2, [r3]
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8002d16:	f022 0210 	bic.w	r2, r2, #16
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002d1a:	e843 2100 	strex	r1, r2, [r3]
 8002d1e:	2900      	cmp	r1, #0
 8002d20:	d1f7      	bne.n	8002d12 <UART_CheckIdleState+0x136>
 8002d22:	e7ea      	b.n	8002cfa <UART_CheckIdleState+0x11e>
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 8002d24:	f44f 6200 	mov.w	r2, #2048	; 0x800
 8002d28:	621a      	str	r2, [r3, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002d2a:	e853 2f00 	ldrex	r2, [r3]
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 8002d2e:	f422 7290 	bic.w	r2, r2, #288	; 0x120
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002d32:	e843 2100 	strex	r1, r2, [r3]
 8002d36:	2900      	cmp	r1, #0
 8002d38:	d1f7      	bne.n	8002d2a <UART_CheckIdleState+0x14e>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 8002d3a:	483f      	ldr	r0, [pc, #252]	; (8002e38 <UART_CheckIdleState+0x25c>)
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002d3c:	f103 0208 	add.w	r2, r3, #8
 8002d40:	e852 2f00 	ldrex	r2, [r2]
 8002d44:	4002      	ands	r2, r0
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002d46:	f103 0508 	add.w	r5, r3, #8
 8002d4a:	e845 2100 	strex	r1, r2, [r5]
 8002d4e:	2900      	cmp	r1, #0
 8002d50:	d1f4      	bne.n	8002d3c <UART_CheckIdleState+0x160>
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8002d52:	6ee2      	ldr	r2, [r4, #108]	; 0x6c
 8002d54:	2a01      	cmp	r2, #1
 8002d56:	d00a      	beq.n	8002d6e <UART_CheckIdleState+0x192>
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002d58:	2200      	movs	r2, #0
  huart->RxState = HAL_UART_STATE_READY;
 8002d5a:	2120      	movs	r1, #32
 8002d5c:	f8c4 108c 	str.w	r1, [r4, #140]	; 0x8c
  huart->RxISR = NULL;
 8002d60:	6762      	str	r2, [r4, #116]	; 0x74
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002d62:	66e2      	str	r2, [r4, #108]	; 0x6c
          __HAL_UNLOCK(huart);
 8002d64:	f884 2084 	strb.w	r2, [r4, #132]	; 0x84
          huart->ErrorCode = HAL_UART_ERROR_RTO;
 8002d68:	f8c4 1090 	str.w	r1, [r4, #144]	; 0x90
          return HAL_TIMEOUT;
 8002d6c:	e769      	b.n	8002c42 <UART_CheckIdleState+0x66>
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002d6e:	e853 2f00 	ldrex	r2, [r3]
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8002d72:	f022 0210 	bic.w	r2, r2, #16
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002d76:	e843 2100 	strex	r1, r2, [r3]
 8002d7a:	2900      	cmp	r1, #0
 8002d7c:	d1f7      	bne.n	8002d6e <UART_CheckIdleState+0x192>
 8002d7e:	e7eb      	b.n	8002d58 <UART_CheckIdleState+0x17c>
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 8002d80:	2208      	movs	r2, #8
 8002d82:	621a      	str	r2, [r3, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002d84:	e853 2f00 	ldrex	r2, [r3]
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 8002d88:	f422 7290 	bic.w	r2, r2, #288	; 0x120
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002d8c:	e843 2100 	strex	r1, r2, [r3]
 8002d90:	2900      	cmp	r1, #0
 8002d92:	d1f7      	bne.n	8002d84 <UART_CheckIdleState+0x1a8>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 8002d94:	4828      	ldr	r0, [pc, #160]	; (8002e38 <UART_CheckIdleState+0x25c>)
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002d96:	f103 0208 	add.w	r2, r3, #8
 8002d9a:	e852 2f00 	ldrex	r2, [r2]
 8002d9e:	4002      	ands	r2, r0
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002da0:	f103 0508 	add.w	r5, r3, #8
 8002da4:	e845 2100 	strex	r1, r2, [r5]
 8002da8:	2900      	cmp	r1, #0
 8002daa:	d1f4      	bne.n	8002d96 <UART_CheckIdleState+0x1ba>
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8002dac:	6ee2      	ldr	r2, [r4, #108]	; 0x6c
 8002dae:	2a01      	cmp	r2, #1
 8002db0:	d00b      	beq.n	8002dca <UART_CheckIdleState+0x1ee>
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002db2:	2200      	movs	r2, #0
  huart->RxState = HAL_UART_STATE_READY;
 8002db4:	2020      	movs	r0, #32
          huart->ErrorCode = HAL_UART_ERROR_ORE;
 8002db6:	2108      	movs	r1, #8
  huart->RxState = HAL_UART_STATE_READY;
 8002db8:	f8c4 008c 	str.w	r0, [r4, #140]	; 0x8c
  huart->RxISR = NULL;
 8002dbc:	6762      	str	r2, [r4, #116]	; 0x74
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002dbe:	66e2      	str	r2, [r4, #108]	; 0x6c
          __HAL_UNLOCK(huart);
 8002dc0:	f884 2084 	strb.w	r2, [r4, #132]	; 0x84
          huart->ErrorCode = HAL_UART_ERROR_ORE;
 8002dc4:	f8c4 1090 	str.w	r1, [r4, #144]	; 0x90
          return HAL_ERROR;
 8002dc8:	e763      	b.n	8002c92 <UART_CheckIdleState+0xb6>
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002dca:	e853 2f00 	ldrex	r2, [r3]
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8002dce:	f022 0210 	bic.w	r2, r2, #16
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002dd2:	e843 2100 	strex	r1, r2, [r3]
 8002dd6:	2900      	cmp	r1, #0
 8002dd8:	d1f7      	bne.n	8002dca <UART_CheckIdleState+0x1ee>
 8002dda:	e7ea      	b.n	8002db2 <UART_CheckIdleState+0x1d6>
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 8002ddc:	f44f 6200 	mov.w	r2, #2048	; 0x800
 8002de0:	621a      	str	r2, [r3, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002de2:	e853 2f00 	ldrex	r2, [r3]
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 8002de6:	f422 7290 	bic.w	r2, r2, #288	; 0x120
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002dea:	e843 2100 	strex	r1, r2, [r3]
 8002dee:	2900      	cmp	r1, #0
 8002df0:	d1f7      	bne.n	8002de2 <UART_CheckIdleState+0x206>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 8002df2:	4811      	ldr	r0, [pc, #68]	; (8002e38 <UART_CheckIdleState+0x25c>)
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002df4:	f103 0208 	add.w	r2, r3, #8
 8002df8:	e852 2f00 	ldrex	r2, [r2]
 8002dfc:	4002      	ands	r2, r0
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002dfe:	f103 0508 	add.w	r5, r3, #8
 8002e02:	e845 2100 	strex	r1, r2, [r5]
 8002e06:	2900      	cmp	r1, #0
 8002e08:	d1f4      	bne.n	8002df4 <UART_CheckIdleState+0x218>
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8002e0a:	6ee2      	ldr	r2, [r4, #108]	; 0x6c
 8002e0c:	2a01      	cmp	r2, #1
 8002e0e:	d00a      	beq.n	8002e26 <UART_CheckIdleState+0x24a>
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002e10:	2200      	movs	r2, #0
  huart->RxState = HAL_UART_STATE_READY;
 8002e12:	2120      	movs	r1, #32
 8002e14:	f8c4 108c 	str.w	r1, [r4, #140]	; 0x8c
  huart->RxISR = NULL;
 8002e18:	6762      	str	r2, [r4, #116]	; 0x74
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002e1a:	66e2      	str	r2, [r4, #108]	; 0x6c
          __HAL_UNLOCK(huart);
 8002e1c:	f884 2084 	strb.w	r2, [r4, #132]	; 0x84
          huart->ErrorCode = HAL_UART_ERROR_RTO;
 8002e20:	f8c4 1090 	str.w	r1, [r4, #144]	; 0x90
          return HAL_TIMEOUT;
 8002e24:	e735      	b.n	8002c92 <UART_CheckIdleState+0xb6>
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002e26:	e853 2f00 	ldrex	r2, [r3]
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8002e2a:	f022 0210 	bic.w	r2, r2, #16
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002e2e:	e843 2100 	strex	r1, r2, [r3]
 8002e32:	2900      	cmp	r1, #0
 8002e34:	d1f7      	bne.n	8002e26 <UART_CheckIdleState+0x24a>
 8002e36:	e7eb      	b.n	8002e10 <UART_CheckIdleState+0x234>
 8002e38:	effffffe 	.word	0xeffffffe

08002e3c <HAL_UART_Init>:
  if (huart == NULL)
 8002e3c:	b380      	cbz	r0, 8002ea0 <HAL_UART_Init+0x64>
  if (huart->gState == HAL_UART_STATE_RESET)
 8002e3e:	f8d0 3088 	ldr.w	r3, [r0, #136]	; 0x88
{
 8002e42:	b510      	push	{r4, lr}
 8002e44:	4604      	mov	r4, r0
  if (huart->gState == HAL_UART_STATE_RESET)
 8002e46:	b333      	cbz	r3, 8002e96 <HAL_UART_Init+0x5a>
  __HAL_UART_DISABLE(huart);
 8002e48:	6822      	ldr	r2, [r4, #0]
  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
 8002e4a:	6aa1      	ldr	r1, [r4, #40]	; 0x28
  huart->gState = HAL_UART_STATE_BUSY;
 8002e4c:	2324      	movs	r3, #36	; 0x24
 8002e4e:	f8c4 3088 	str.w	r3, [r4, #136]	; 0x88
  __HAL_UART_DISABLE(huart);
 8002e52:	6813      	ldr	r3, [r2, #0]
 8002e54:	f023 0301 	bic.w	r3, r3, #1
 8002e58:	6013      	str	r3, [r2, #0]
  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
 8002e5a:	b9c1      	cbnz	r1, 8002e8e <HAL_UART_Init+0x52>
  if (UART_SetConfig(huart) == HAL_ERROR)
 8002e5c:	4620      	mov	r0, r4
 8002e5e:	f7ff fcf5 	bl	800284c <UART_SetConfig>
 8002e62:	2801      	cmp	r0, #1
 8002e64:	d011      	beq.n	8002e8a <HAL_UART_Init+0x4e>
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8002e66:	6823      	ldr	r3, [r4, #0]
 8002e68:	685a      	ldr	r2, [r3, #4]
 8002e6a:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8002e6e:	605a      	str	r2, [r3, #4]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8002e70:	689a      	ldr	r2, [r3, #8]
 8002e72:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 8002e76:	609a      	str	r2, [r3, #8]
  __HAL_UART_ENABLE(huart);
 8002e78:	681a      	ldr	r2, [r3, #0]
 8002e7a:	f042 0201 	orr.w	r2, r2, #1
  return (UART_CheckIdleState(huart));
 8002e7e:	4620      	mov	r0, r4
  __HAL_UART_ENABLE(huart);
 8002e80:	601a      	str	r2, [r3, #0]
}
 8002e82:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
  return (UART_CheckIdleState(huart));
 8002e86:	f7ff bea9 	b.w	8002bdc <UART_CheckIdleState>
}
 8002e8a:	2001      	movs	r0, #1
 8002e8c:	bd10      	pop	{r4, pc}
    UART_AdvFeatureConfig(huart);
 8002e8e:	4620      	mov	r0, r4
 8002e90:	f7ff fe4c 	bl	8002b2c <UART_AdvFeatureConfig>
 8002e94:	e7e2      	b.n	8002e5c <HAL_UART_Init+0x20>
    huart->Lock = HAL_UNLOCKED;
 8002e96:	f880 3084 	strb.w	r3, [r0, #132]	; 0x84
    HAL_UART_MspInit(huart);
 8002e9a:	f7fd fdf9 	bl	8000a90 <HAL_UART_MspInit>
 8002e9e:	e7d3      	b.n	8002e48 <HAL_UART_Init+0xc>
}
 8002ea0:	2001      	movs	r0, #1
 8002ea2:	4770      	bx	lr

08002ea4 <HAL_UARTEx_DisableFifoMode>:

  /* Check parameters */
  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));

  /* Process Locked */
  __HAL_LOCK(huart);
 8002ea4:	f890 3084 	ldrb.w	r3, [r0, #132]	; 0x84
 8002ea8:	2b01      	cmp	r3, #1
 8002eaa:	d017      	beq.n	8002edc <HAL_UARTEx_DisableFifoMode+0x38>

  huart->gState = HAL_UART_STATE_BUSY;

  /* Save actual UART configuration */
  tmpcr1 = READ_REG(huart->Instance->CR1);
 8002eac:	6802      	ldr	r2, [r0, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 8002eae:	2324      	movs	r3, #36	; 0x24
{
 8002eb0:	b410      	push	{r4}
  huart->gState = HAL_UART_STATE_BUSY;
 8002eb2:	f8c0 3088 	str.w	r3, [r0, #136]	; 0x88
  tmpcr1 = READ_REG(huart->Instance->CR1);
 8002eb6:	6811      	ldr	r1, [r2, #0]

  /* Disable UART */
  __HAL_UART_DISABLE(huart);
 8002eb8:	6814      	ldr	r4, [r2, #0]

  /* Disable FIFO mode */
  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
  huart->FifoMode = UART_FIFOMODE_DISABLE;
 8002eba:	2300      	movs	r3, #0
  __HAL_UART_DISABLE(huart);
 8002ebc:	f024 0401 	bic.w	r4, r4, #1
  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
 8002ec0:	f021 5100 	bic.w	r1, r1, #536870912	; 0x20000000
  __HAL_UART_DISABLE(huart);
 8002ec4:	6014      	str	r4, [r2, #0]
  huart->FifoMode = UART_FIFOMODE_DISABLE;
 8002ec6:	6643      	str	r3, [r0, #100]	; 0x64

  /* Restore UART configuration */
  WRITE_REG(huart->Instance->CR1, tmpcr1);
 8002ec8:	6011      	str	r1, [r2, #0]

  huart->gState = HAL_UART_STATE_READY;

  /* Process Unlocked */
  __HAL_UNLOCK(huart);
 8002eca:	f880 3084 	strb.w	r3, [r0, #132]	; 0x84
  huart->gState = HAL_UART_STATE_READY;
 8002ece:	2220      	movs	r2, #32
 8002ed0:	f8c0 2088 	str.w	r2, [r0, #136]	; 0x88

  return HAL_OK;
}
 8002ed4:	f85d 4b04 	ldr.w	r4, [sp], #4
  return HAL_OK;
 8002ed8:	4618      	mov	r0, r3
}
 8002eda:	4770      	bx	lr
  __HAL_LOCK(huart);
 8002edc:	2002      	movs	r0, #2
}
 8002ede:	4770      	bx	lr

08002ee0 <HAL_UARTEx_SetTxFifoThreshold>:
  /* Check parameters */
  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));

  /* Process Locked */
  __HAL_LOCK(huart);
 8002ee0:	f890 2084 	ldrb.w	r2, [r0, #132]	; 0x84
 8002ee4:	2a01      	cmp	r2, #1
 8002ee6:	d037      	beq.n	8002f58 <HAL_UARTEx_SetTxFifoThreshold+0x78>

  huart->gState = HAL_UART_STATE_BUSY;
 8002ee8:	4603      	mov	r3, r0

  /* Save actual UART configuration */
  tmpcr1 = READ_REG(huart->Instance->CR1);
 8002eea:	6802      	ldr	r2, [r0, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 8002eec:	2024      	movs	r0, #36	; 0x24
{
 8002eee:	b530      	push	{r4, r5, lr}
  huart->gState = HAL_UART_STATE_BUSY;
 8002ef0:	f8c3 0088 	str.w	r0, [r3, #136]	; 0x88
  tmpcr1 = READ_REG(huart->Instance->CR1);
 8002ef4:	6814      	ldr	r4, [r2, #0]

  /* Disable UART */
  __HAL_UART_DISABLE(huart);
 8002ef6:	6810      	ldr	r0, [r2, #0]
 8002ef8:	f020 0001 	bic.w	r0, r0, #1
 8002efc:	6010      	str	r0, [r2, #0]

  /* Update TX threshold configuration */
  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
 8002efe:	6890      	ldr	r0, [r2, #8]
 8002f00:	f020 4060 	bic.w	r0, r0, #3758096384	; 0xe0000000
 8002f04:	4301      	orrs	r1, r0
  uint8_t rx_fifo_threshold;
  uint8_t tx_fifo_threshold;
  static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};

  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
 8002f06:	6e58      	ldr	r0, [r3, #100]	; 0x64
  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
 8002f08:	6091      	str	r1, [r2, #8]
  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
 8002f0a:	b310      	cbz	r0, 8002f52 <HAL_UARTEx_SetTxFifoThreshold+0x72>
  }
  else
  {
    rx_fifo_depth = RX_FIFO_DEPTH;
    tx_fifo_depth = TX_FIFO_DEPTH;
    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
 8002f0c:	6891      	ldr	r1, [r2, #8]
    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
 8002f0e:	6890      	ldr	r0, [r2, #8]
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
                               (uint16_t)denominator[tx_fifo_threshold];
 8002f10:	4d12      	ldr	r5, [pc, #72]	; (8002f5c <HAL_UARTEx_SetTxFifoThreshold+0x7c>)
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 8002f12:	f3c1 6c42 	ubfx	ip, r1, #25, #3
    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
 8002f16:	ea4f 7e50 	mov.w	lr, r0, lsr #29
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
 8002f1a:	4911      	ldr	r1, [pc, #68]	; (8002f60 <HAL_UARTEx_SetTxFifoThreshold+0x80>)
 8002f1c:	f811 000e 	ldrb.w	r0, [r1, lr]
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 8002f20:	f811 100c 	ldrb.w	r1, [r1, ip]
                               (uint16_t)denominator[tx_fifo_threshold];
 8002f24:	f815 e00e 	ldrb.w	lr, [r5, lr]
                               (uint16_t)denominator[rx_fifo_threshold];
 8002f28:	f815 500c 	ldrb.w	r5, [r5, ip]
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
 8002f2c:	00c0      	lsls	r0, r0, #3
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 8002f2e:	00c9      	lsls	r1, r1, #3
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
 8002f30:	fbb0 f0fe 	udiv	r0, r0, lr
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 8002f34:	fbb1 f1f5 	udiv	r1, r1, r5
 8002f38:	f8a3 1068 	strh.w	r1, [r3, #104]	; 0x68
  __HAL_UNLOCK(huart);
 8002f3c:	2100      	movs	r1, #0
 8002f3e:	f8a3 006a 	strh.w	r0, [r3, #106]	; 0x6a
  huart->gState = HAL_UART_STATE_READY;
 8002f42:	2520      	movs	r5, #32
  WRITE_REG(huart->Instance->CR1, tmpcr1);
 8002f44:	6014      	str	r4, [r2, #0]
  __HAL_UNLOCK(huart);
 8002f46:	f883 1084 	strb.w	r1, [r3, #132]	; 0x84
  return HAL_OK;
 8002f4a:	4608      	mov	r0, r1
  huart->gState = HAL_UART_STATE_READY;
 8002f4c:	f8c3 5088 	str.w	r5, [r3, #136]	; 0x88
}
 8002f50:	bd30      	pop	{r4, r5, pc}
    huart->NbRxDataToProcess = 1U;
 8002f52:	2101      	movs	r1, #1
    huart->NbTxDataToProcess = 1U;
 8002f54:	4608      	mov	r0, r1
 8002f56:	e7ef      	b.n	8002f38 <HAL_UARTEx_SetTxFifoThreshold+0x58>
  __HAL_LOCK(huart);
 8002f58:	2002      	movs	r0, #2
}
 8002f5a:	4770      	bx	lr
 8002f5c:	080030ac 	.word	0x080030ac
 8002f60:	080030b4 	.word	0x080030b4

08002f64 <HAL_UARTEx_SetRxFifoThreshold>:
  __HAL_LOCK(huart);
 8002f64:	f890 2084 	ldrb.w	r2, [r0, #132]	; 0x84
 8002f68:	2a01      	cmp	r2, #1
 8002f6a:	d037      	beq.n	8002fdc <HAL_UARTEx_SetRxFifoThreshold+0x78>
  huart->gState = HAL_UART_STATE_BUSY;
 8002f6c:	4603      	mov	r3, r0
  tmpcr1 = READ_REG(huart->Instance->CR1);
 8002f6e:	6802      	ldr	r2, [r0, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 8002f70:	2024      	movs	r0, #36	; 0x24
{
 8002f72:	b530      	push	{r4, r5, lr}
  huart->gState = HAL_UART_STATE_BUSY;
 8002f74:	f8c3 0088 	str.w	r0, [r3, #136]	; 0x88
  tmpcr1 = READ_REG(huart->Instance->CR1);
 8002f78:	6814      	ldr	r4, [r2, #0]
  __HAL_UART_DISABLE(huart);
 8002f7a:	6810      	ldr	r0, [r2, #0]
 8002f7c:	f020 0001 	bic.w	r0, r0, #1
 8002f80:	6010      	str	r0, [r2, #0]
  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
 8002f82:	6890      	ldr	r0, [r2, #8]
 8002f84:	f020 6060 	bic.w	r0, r0, #234881024	; 0xe000000
 8002f88:	4301      	orrs	r1, r0
  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
 8002f8a:	6e58      	ldr	r0, [r3, #100]	; 0x64
  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
 8002f8c:	6091      	str	r1, [r2, #8]
  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
 8002f8e:	b310      	cbz	r0, 8002fd6 <HAL_UARTEx_SetRxFifoThreshold+0x72>
    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
 8002f90:	6891      	ldr	r1, [r2, #8]
    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
 8002f92:	6890      	ldr	r0, [r2, #8]
                               (uint16_t)denominator[tx_fifo_threshold];
 8002f94:	4d12      	ldr	r5, [pc, #72]	; (8002fe0 <HAL_UARTEx_SetRxFifoThreshold+0x7c>)
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 8002f96:	f3c1 6c42 	ubfx	ip, r1, #25, #3
    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
 8002f9a:	ea4f 7e50 	mov.w	lr, r0, lsr #29
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
 8002f9e:	4911      	ldr	r1, [pc, #68]	; (8002fe4 <HAL_UARTEx_SetRxFifoThreshold+0x80>)
 8002fa0:	f811 000e 	ldrb.w	r0, [r1, lr]
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 8002fa4:	f811 100c 	ldrb.w	r1, [r1, ip]
                               (uint16_t)denominator[tx_fifo_threshold];
 8002fa8:	f815 e00e 	ldrb.w	lr, [r5, lr]
                               (uint16_t)denominator[rx_fifo_threshold];
 8002fac:	f815 500c 	ldrb.w	r5, [r5, ip]
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
 8002fb0:	00c0      	lsls	r0, r0, #3
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 8002fb2:	00c9      	lsls	r1, r1, #3
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
 8002fb4:	fbb0 f0fe 	udiv	r0, r0, lr
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 8002fb8:	fbb1 f1f5 	udiv	r1, r1, r5
 8002fbc:	f8a3 1068 	strh.w	r1, [r3, #104]	; 0x68
  __HAL_UNLOCK(huart);
 8002fc0:	2100      	movs	r1, #0
 8002fc2:	f8a3 006a 	strh.w	r0, [r3, #106]	; 0x6a
  huart->gState = HAL_UART_STATE_READY;
 8002fc6:	2520      	movs	r5, #32
  WRITE_REG(huart->Instance->CR1, tmpcr1);
 8002fc8:	6014      	str	r4, [r2, #0]
  __HAL_UNLOCK(huart);
 8002fca:	f883 1084 	strb.w	r1, [r3, #132]	; 0x84
  return HAL_OK;
 8002fce:	4608      	mov	r0, r1
  huart->gState = HAL_UART_STATE_READY;
 8002fd0:	f8c3 5088 	str.w	r5, [r3, #136]	; 0x88
}
 8002fd4:	bd30      	pop	{r4, r5, pc}
    huart->NbRxDataToProcess = 1U;
 8002fd6:	2101      	movs	r1, #1
    huart->NbTxDataToProcess = 1U;
 8002fd8:	4608      	mov	r0, r1
 8002fda:	e7ef      	b.n	8002fbc <HAL_UARTEx_SetRxFifoThreshold+0x58>
  __HAL_LOCK(huart);
 8002fdc:	2002      	movs	r0, #2
}
 8002fde:	4770      	bx	lr
 8002fe0:	080030ac 	.word	0x080030ac
 8002fe4:	080030b4 	.word	0x080030b4

08002fe8 <__libc_init_array>:
 8002fe8:	b570      	push	{r4, r5, r6, lr}
 8002fea:	4d0d      	ldr	r5, [pc, #52]	; (8003020 <__libc_init_array+0x38>)
 8002fec:	4c0d      	ldr	r4, [pc, #52]	; (8003024 <__libc_init_array+0x3c>)
 8002fee:	1b64      	subs	r4, r4, r5
 8002ff0:	10a4      	asrs	r4, r4, #2
 8002ff2:	2600      	movs	r6, #0
 8002ff4:	42a6      	cmp	r6, r4
 8002ff6:	d109      	bne.n	800300c <__libc_init_array+0x24>
 8002ff8:	4d0b      	ldr	r5, [pc, #44]	; (8003028 <__libc_init_array+0x40>)
 8002ffa:	4c0c      	ldr	r4, [pc, #48]	; (800302c <__libc_init_array+0x44>)
 8002ffc:	f000 f820 	bl	8003040 <_init>
 8003000:	1b64      	subs	r4, r4, r5
 8003002:	10a4      	asrs	r4, r4, #2
 8003004:	2600      	movs	r6, #0
 8003006:	42a6      	cmp	r6, r4
 8003008:	d105      	bne.n	8003016 <__libc_init_array+0x2e>
 800300a:	bd70      	pop	{r4, r5, r6, pc}
 800300c:	f855 3b04 	ldr.w	r3, [r5], #4
 8003010:	4798      	blx	r3
 8003012:	3601      	adds	r6, #1
 8003014:	e7ee      	b.n	8002ff4 <__libc_init_array+0xc>
 8003016:	f855 3b04 	ldr.w	r3, [r5], #4
 800301a:	4798      	blx	r3
 800301c:	3601      	adds	r6, #1
 800301e:	e7f2      	b.n	8003006 <__libc_init_array+0x1e>
 8003020:	080030c4 	.word	0x080030c4
 8003024:	080030c4 	.word	0x080030c4
 8003028:	080030c4 	.word	0x080030c4
 800302c:	080030c8 	.word	0x080030c8

08003030 <memset>:
 8003030:	4402      	add	r2, r0
 8003032:	4603      	mov	r3, r0
 8003034:	4293      	cmp	r3, r2
 8003036:	d100      	bne.n	800303a <memset+0xa>
 8003038:	4770      	bx	lr
 800303a:	f803 1b01 	strb.w	r1, [r3], #1
 800303e:	e7f9      	b.n	8003034 <memset+0x4>

08003040 <_init>:
 8003040:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8003042:	bf00      	nop
 8003044:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8003046:	bc08      	pop	{r3}
 8003048:	469e      	mov	lr, r3
 800304a:	4770      	bx	lr

0800304c <_fini>:
 800304c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800304e:	bf00      	nop
 8003050:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8003052:	bc08      	pop	{r3}
 8003054:	469e      	mov	lr, r3
 8003056:	4770      	bx	lr